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2022-10-15soc/intel/apollolake: Lock down Global SMISean Rhodes
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9377c3b65aa342f754c303148b0b8d826d05bb94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67662 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-15soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdownSean Rhodes
Configure FSP S UPDs to allow coreboot to handle the lockdown. The main change here is setting `Write Protection Support` to 0, as the default is Enabled, which shouldn't allow writes (even though it seems to). The UPDs are identical on APL and GLK, but all ones configured in this patch have been there since their initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1f6e5344cab2af7aa6001b9ec0f07b043a9caa8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-15treewide: Use 'fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk'Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaecb83c3bc9c75dab427a3ca54da1e6a8f87cf9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-15treewide: Use 'fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk'Felix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id3002dc976b82f71b1f60a6e32b16d60a7bbbead Reviewed-on: https://review.coreboot.org/c/coreboot/+/68427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-14soc/intel/alderlake: Create helper header file for UFSSubrata Banik
This patch creates helper header file (ufs.h) for UFS to keep required registers details and ACPI device id for UFS. BUG=none TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If08c54eb706876a4255542a708aa5fcd8bf43c55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68299 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-14soc/intel/alderlake: Add UFS PCR IDSubrata Banik
Add UFS PID (`PID_UFSX2`) value 0x50. BUG=none TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I229469475cd116bf911b6530c3c819d00c808aa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68298 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14soc/intel/alderlake: Fix unknown voltage in SMBIOSZhixing Ma
The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed, and upgrade (socket type). This patch implements voltage function. Refer to SMBIOS spec sheet for documentation: https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf BUG=NONE BRANCH=firmware-brya-14505.B TEST=Boot and verified that SMBIOS processor voltage value is correct. Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I77712b72fa47bdcb56ffddeff15cff9f3b3bbe86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68023 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14soc/intel/alderlake: Fix unknown max speed in SMBIOSZhixing Ma
The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed, and upgrade (socket type). This patch implements max speed function. Refer to SMBIOS spec sheet for documentation: https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf BUG=NONE BRANCH=firmware-brya-14505.B TEST=Boot and verified that SMBIOS max speed value is correct. Signed-off-by: Zhixing Ma <zhixing.ma@intel.com> Change-Id: I09bcccc6f97238f7328224af8b852751114896fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/67913 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-13payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarityElyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I80f3d2c90c58daa62651f6fd635c043b1ce38b84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12soc/intel: Kconfig: Correct UART source clock value in commentWonkyu Kim
Correct UART source clock value in comment from 120 MHz to 100 MHz. BUG=b:249530903 Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ifc17357051ae0b3bc663da467b4fc809a46024d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68286 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-12treewide: Use 'fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ic48c5c165732c8397c06a2362191a94ae5805cf1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7ddb4ea792b9a2153b7c77d2978d9e1c4544535d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'pm2_cnt_len' for 'x_pm2_cnt_blk.bit_width'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I040ddab8845cc2191c6ca5af7f132ec8a504bccf Reviewed-on: https://review.coreboot.org/c/coreboot/+/68274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'gpe0_blk' for 'x_gpe0_blk.addrl'Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I05d5097097b925a7bc8058f4c23e7c13a49f03c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12treewide: Use 'fadt->pm_tmr_len' for 'x_pm_tmr_blk.bit_width'Elyes Haouas
Change-Id: Id4e2939b74ec93f50a4bedd0069090f0775b0556 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-12soc/intel/ehl: Fix incorrect access to MAC_MDIO_DATA registerMario Scheithauer
Function 'setbits16' performs an 'OR' operation with the new data and the origin register entry. This can lead to an incorrect value in the register which can then lead to issues. Change-Id: I0212420be770e2ffdabebbfaf5dfbf8d99d25915 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-10-12soc/intel/ehl: Support maximum memory frequency selectionChristian Gmeiner
Makes it possible to configure the maximum allowed/supported DDR memory frequency on a per mainboard basis. Test - Define maximum memory frequency in mainboard devicetree.cb - Boot into Linux and run 'sudo dmidecode --type 17' to check memory speed - Boot into Linux and run 'phoronix-test-suite benchmark ramspeed' Change-Id: I9e0c7225e2141e675a20b8e3f0dbe8c0b3a29b28 Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68097 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-07soc/intel/apollolake: Add UFS InterruptSean Rhodes
According to Intel document number 336561, GLK has UFS (0x1d), so add the PCI interrupt. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I68bac590bd1a9a0b8213440e882c8f431f06c95f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67680 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07soc/intel/apollolake: Remove SD Card interrupt for GLKSean Rhodes
According to Intel document number 336561, G, SD Card (0x1b) does not exist on GLK, so remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6921fc3db430c76ec54cf832ce51c627a507385c Reviewed-on: https://review.coreboot.org/c/coreboot/+/67679 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07soc/intel/ehl: Set Ethernet controller to D0 power stateMario Scheithauer
To be able to change the MAC addresses, it is necessary that the controllers are in D0 power state. As of FSP MR3, Intel has set the controllers to D3 power state at the end of FSP-S TSN GbE initialization. This patch sets the state back to D0 before the programming of the MAC addresses. Test: - Build coreboot with FSP MR4 for mc_ehl2 mainboard - Boot into Linux and check MAC addr via 'ip a' Change-Id: I4002d58eb4332ba45c35d07820900dfd2c637f21 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-10-07soc/intel/alderlake: Support Raptor Lake VR Fast VMODEJeremy Compostella
RaptorLake introduces the support of the Voltage Regulator Fast Vmode feature. When enabled, it makes the SoC throttle when the current exceeds the I_TRIP threshold. This threshold should be between Iccmax.app and Iccmax and take into account the specification of the Voltage Regulator of the system. This change provides a mean to: 1. Enable the feature via the `vr_config->enable_fast_vmode'. If no I_TRIP value is supplied FSPs picks an adapted I_TRIP value for the current SoC assuming a Voltage Regulator error accuracy of 6.5%. 2. Set the I_TRIP threshold via the `vr_config->fast_vmode_i_trip' field. These new fields are considered independent from the other `vr_config' fields so that the board configuration does not have to unnecessarily supply other VR settings to enable Fast VMode. Information about the Fast VMode Feature can be found in the following Intel documents: - 627270 ADL and RPL Processor Family Core and Uncore BIOS Specification - 724220 RaptorLake Platform Fast V-Mode - 686872 RaptorLake Lake U P H Platform BUG=b:243120082 BRANCH=firmware-brya-14505.B TEST=Read I_TRIP from the Pcode and verify consistency with a few `enable_fast_vmode' and `fast_vmode_i_trip' settings. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/66917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06treewide: use predicates to check for enabled pci devicesFabio Aiuto
use functions to check for pci devices instead of open-coded solution. TEST: compiled and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: Idb992904112db611119b2d33c8b1dd912b2c8539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68102 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-06soc/intel/apollolake/acpi: Add PCIEXBAR to MCHCSean Rhodes
The values in this patch were found in the following datasheets: * 334819 (APL) * 336561 (GLK) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I14c5933b9022703c8951da7c6a26eb703258ec37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-06soc/intel/meteorlake: Make use of is_devfn_enabled() functionSridhar Siricilla
The patch uses is_devfn_enabled() function to enable the TBT PCIe ports through FSP-M and FSP-S UPDs. Also, removes unused tbt_pcie_port_disable array member from soc_intel_meteorlake_config struct. TEST=Build coreboot for Google/Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ie55e196bd8f682864b8f74dbe253f345d7184753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-06soc/intel/cmn/gfx: Add missing CML-U IGD device IDsMichał Żygowski
Intel Core i5-10210U can have the following IGD Device IDs 0x9B21/0x9B41/0x9BAC/0x9BCA/0x9BCC according to Intel ARK. Some of these IDs were not present in coreboot source nor hooked to the common graphics driver. Add the missing IDs so that the graphics driver will probe on the mentioned processor and detect the framebuffer. TEST=Boot Protectli VP4650 with i5-10210U and see framebuffer is detected when using FSP GOP and libgfxinit. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iee720a272367aead31c8c8fa712bade1b6e53948 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67975 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-04soc/intel/alderlake: Fix UFS OCP fabric timeoutMeera Ravindranath
The delayed return of certain fetch instruction from memory to the UFS causes the OCP fabric to timeout on the transaction and become non-responsive. As recommended by the SoC and IP teams,program the OCP fabric register to avoid the timeout in the OCP fabric. This patch adds the following changes 1. Program the OCP fabric registers in the PS0 routine. 2. Move the ssdt contents of UFS to dsdt asl code to avoid duplication of UFS device creation BUG=b:240222922 TEST=Build and boot Nirwen UFS board, observe no system hang during Chrome PLT test. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I949a4538ea5c5c378a4e8ff7bb88546db1412df2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-09-30soc/intel/adl: Add config option to enable FSP-S SATA test modeLean Sheng Tan
For further info on SATA test mode, please refer to this doc: https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/sata-mqst-setup-paper.pdf Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I6ef79fc5723348d5fd10b2ac0847191fa4f37f41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67410 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-29treewide: use is_enabled_cpu() on cycles over device listFabio Aiuto
use is_enabled_cpu() on cycles over device list to check whether the current device is enabled cpu. TEST: compile test and qemu run successfully with coreinfo payload Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: If64bd18f006b6f5fecef4f606c1df7d3a4d42883 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67797 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-27acpi/acpi_pm.c: refactor acpi_pm_state_for_* functionsFabio Aiuto
Use just one function to get the chipset powerstate and add an argument to specify the powerstate claimer {RTC,ELOG,WAKE} and adjust the failure log accordingly. TEST: compile tested and qemu emulation successfully run Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: I8addc0b05f9e360afc52091c4bb731341d7213cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/67618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-22soc/common/lockdown: Guard sa_lock_pamSean Rhodes
Guard sa_lock_pam with PAM0_REGISTER so it doesn't run on platforms that don't select this. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5055d09c634851e9f869ab0b67a7bcab130f928c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66492 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22soc/intel/common/pch: Add a block specific to Apollo LakeSean Rhodes
Add SOC_INTEL_COMMON_PCH_CLIENT which is specific to Apollo Lake. This is used to select the options that Apollo Lake requires, without the ones specific to a PCH as Apollo Lake doesn't have a PCH. This change also enables SOC_INTEL_COMMON_PCH_LOCKDOWN for Apollo Lake. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I084a05f904a19f3b7e9a071636659670aa45bf3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/65245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-22common/block/fast_spi: Add extended BIOS window as reserved regionWerner Zeh
The fast SPI driver reports the BIOS window as reserved so that the OS is aware of this region. Now that platforms which supports an extended BIOS window are added to this driver, add the extended range as reserved as well if it is enabled. And since this is now handled in the SPI driver itself, remove the extended BIOS region reporting from common systemagent code. Change-Id: Ib5c735bffcb389be07c876d7b5b2d88c545a0b03 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-22soc/intel/spi: Move BIOS flash SPI controllers to fast SPI driverWerner Zeh
There are two classes of SPI controllers on Intel chipsets: * generic usable SPI controllers * SPI controller hosting the BIOS flash (fast SPI controller) While the first class can be used for generic peripheral attachment the second class mostly controls the BIOS flash and a TPM device (if enabled). The generic SPI driver is not fully applicable to the fast SPI controller. In addition, the fast SPI controller reports the reserved MMIO range used for the BIOS flash mapping so that the OS is aware of this range. This patch moves the fast SPI controller of all known SoCs to the fast SPI driver in common code. In addition, the PCI device for the fast SPI controller is removed from the function 'spi_soc_devfn_to_bus' as this is a callback of the generic SPI driver. Change-Id: Ia881c1d274acdcf7f042dd8284048a7dd018a84b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-21soc/intel/meteorlake: Skip the TCSS D3 cold entry sequencezhaojohn
This patch provides a workaround which skips requesting IOM for D3 cold entry sequence. BUG=b:244082753 TEST=Verified MUX configuration after hot plugging Type-C devices on Rex and MTL RVP boards. Change-Id: I17bcde75360c4b2b40885d355702e3e5f45d770a Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-20Revert "soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdown"Tim Wawrzynczak
This reverts commit 7ef5376123d4d0ebb811795fcee1de7066f65a0f. Reason for revert: It was merged before its dependencies so now master is broken. Change-Id: Ia270efaed4f5c9d0c7b9761ae22dec55f57f74cf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67285 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-20soc/intel/alderlake: Explicitly disable Energy Efficiency TurboJeremy Compostella
FSP silicon 3347 changed the default value of the EnergyEfficientTurbo Updateable Product Data (UPD), enabling the Energy Efficient Turbo feature by default. This feature prevents the cores from entering Turbo frequency under heavy load. As a result of this FSP change, coreboot explicitly disables this feature to stay consistent with commit `caa5f59279e Revert "soc/intel/alderlake: Enable energy efficiency turbo mode"'. BRANCH=firmware-brya-14505.B BUG=b:246831841 TEST=verify that bit 19 of MSR 0x1fc is set. 'iotools rdmsr 0 0x1fc' Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I7498f87eb4be666b34cfccd0449a2b67a92eb9db Reviewed-on: https://review.coreboot.org/c/coreboot/+/67650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-09-20soc/intel/alderlake: Add power state thresholdsGaggery Tsai
This patch adds power state 1/2/3 threshold setting interfaces and pass the settings to FSP. BUG=b:229803757 BRANCH=None TEST=Add psi1threshold and psi2threshold to overridetree.cb and enable FSP log to ensure the settings are incorrect. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: I0330ede4394ebc2d3d32e4b78297c3cb328660d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-19soc/intel/apollolake: LZ4 Compress FSP-MArthur Heymans
FSP-M is not run XIP so it can be compressed. This more than halves the binary size. 364544 bytes -> 168616 bytes. On the up/squared this also results in a 83ms speedup. TESTED: up/squared boots. Change-Id: Ic76b51f0f3007b59ccb9f76b6a57bb9265dab833 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-09-19soc/intel/apollolake: Add bits of GEN_PMCON2 registerSean Rhodes
The values in this patch were found in the following datasheets: * 334819 (APL) * 336561 (GLK) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie7d40395d754b2abdf9079d6ee5e8ab8c536d449 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67661 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-19soc/intel/apollolake: Configure FSP UPDs to allow coreboot to lockdownSean Rhodes
Configure FSP S UPDs to allow coreboot to handle the lockdown. The main change here is setting `Write Protection Support` to 0, as the default is Enabled, which shouldn't allow writes (even though it seems to). The UPDs are identical on APL and GLK, but all ones configured in this patch have been there since their initial releases. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I35185b498315511f3236758caebfe2f9c28fd04a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65039 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-16soc/intel/cnl: Add Cometlake-H/S Q0 (10+2) CPU IDJeremy Soller
The Q0 stepping has a different ID than P1. Reference: CML EDS Volume 1 (Intel doc #606599) Change-Id: Id1da42aa93ab3440ae743d943a00713b7df3f453 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-16soc/intel/alderlake: Set FSP-S GnaEnable based on devicetreeJeremy Soller
Change-Id: Ifd25416c55c4dba1709f74cdedc0c58e881d6266 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-16soc/intel/common: Update comment on HFSTS1.spi_protection_modeSridhar Siricilla
The patch updates comment on HFSTS1.spi_protection_mode. The spi_protection_mode indicates SPI protection status as well as EOM status (in a single staged EOM flow). Starting from TGL platform, staged EOM flow is introduced. In this flow, spi_protection_mode alone doesn't indicate the EOM status. For information on EOM status, please refer secton# 3.6.1 in doc# 612229. TEST=Build code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I19df5cfaa6d49963bbfb3f8bc692d847e58c4420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-16Revert "drivers/wifi: Move MTL Magnetar CNVi DIDs from SoC to generic driver"Subrata Banik
This reverts commit 510a55d4eeaeb32047c17328ef238b55b89e7296. Reason for revert: Observed `missing read resource` issue for cnvi device BUG=b:244687646 TEST=No error seen in AP log while booting Google/rex Without this patch: [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 [ERROR] GENERIC: 0.0 missing read_resources [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 done With this patch: [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 [SPEW ] PCI: 00:14.3 read_resources bus 0 link: 0 done Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1e881313729f1088cffa7c161722ee79bb9acc49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67566 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-16soc/intel/meteorlake: Enable `SOC_INTEL_COMMON_BLOCK_CNVI` configSubrata Banik
TEST=Able to build and boot Google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I64aab8391f89414754785cea47671f3350324297 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-15soc/intel/skylake: Assign device ops in chipset devicetreeNico Huber
Some PCI IDs were missing, and at least one (SPT's fast SPI device in a generic SPI driver) was wrong. Hence, this patch actually changes behavior depending on the devices actually present in a machine. In this patch the Skylake devicetree is written in a single-line style. Alternative, the device operations could be put on a separate line, e.g. device pci 00.0 alias system_agent on ops systemagent_ops end Tested on Kontron/bSL6. Notable in the log diff is that the CSE and SATA drivers are hooked up now. Change-Id: I8635fc53ca617b029d6fe1845eaef6c5c749db82 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-15soc/intel/xeon_sp: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I664f5b7d354b0d9a7144c25604ae4efbdd9ba9a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-09-15soc/intel/meteorlake: Use "if (!ptr)" in preference to "if (ptr == NULL)"Elyes Haouas
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ia2508abe62a194f2921d5535937ba82a60967ca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-14soc/intel/cannonlake: Read HPR_CAUSE0 registerAngel Pons
Log the Host Partition Reset Causes (HPR_CAUSE0) register, as done on newer platforms. Change-Id: I35261cefae67649fb7824e5ef3d7eb10add36a53 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-09-14timer: Change timer util functions to 64-bitRob Barnes
Since mono_time is now 64-bit, the utility functions interfacing with mono_time should also be 64-bit so precision isn't lost. Fixed build errors related to printing the now int64_t result of stopwatch_duration_[m|u]secs in various places. BUG=b:237082996 BRANCH=All TEST=Boot dewatt Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-14soc/intel/mtl: Fix GPIO group pad base for ACPIKapil Porwal
This patch fixes MeteorLake GPIO PINCTRL entries as per 5.15 kernel pintrl driver: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.15/drivers/pinctrl/intel/pinctrl-meteorlake.c In order to support using ACPI GPIOs it is necessary for coreboot to be compatible with this implementation. The GPIO groups that are usable by the OS are declared with a pad base which is then used to compute the number for ACPI GPIOs. BUG=b:232573696 TEST=Tested on Google Rex board. After this change, driver rt5682s is able to claim pinctrl IRQ 358 corresponding to GPP_B06. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Icabbe9e125ee9efaf0eef4c4cdc8be9f734aa703 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67565 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-14soc/intel/meteorlake/retimer: Change loglevel prefixIvy Jian
This message is not really an error message, so BIOS_ERR is inappropriate. Since the message is informational, switch to BIOS_INFO instead. BUG=b:244687646 TEST=emerge-rex coreboot before [ERROR] USB Type-C 0 mapped to EC port 0 after [INFO] USB Type-C 0 mapped to EC port 0 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Ia08fd45dd484c79d81527ea46cfaaa5a01a410c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67536 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-14soc/intel/meteorlake: Enable TcssDma1EnIvy Jian
Adding support enables/disables TcssDma1En by usb4_params. BUG=b:244687646 TEST= TcssDma1En is enabled as expected. before patch [SPEW ] PCI: 00:0d.2 [8086/0000] bus ops [DEBUG] PCI: 00:0d.2 [8086/7ec2] enabled [INFO ] PCI: Static device PCI: 00:0d.3 not found, disabling it. after patch [SPEW ] PCI: 00:0d.2 [8086/0000] bus ops [DEBUG] PCI: 00:0d.2 [8086/7ec2] enabled [SPEW ] PCI: 00:0d.3 [8086/0000] bus ops [DEBUG] PCI: 00:0d.3 [8086/7ec3] enabled Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I9cd8fc3819f533e9581fea19d4da48283888cc04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67534 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-14soc/intel/meteorlake: Enable tbtPcie2/3Ivy Jian
Adding support enables/disables tbtPcie2/3 by usb4_params. BUG=b:244687646 TEST= TRP2/3 are enabled as expected. before patch [INFO ] PCI: Static device PCI: 00:07.2 not found, disabling it. [INFO ] PCI: Static device PCI: 00:07.3 not found, disabling it. after patch [DEBUG] PCI: 00:07.2 subordinate bus PCI Express [DEBUG] PCI: 00:07.2 [8086/7ec6] enabled [DEBUG] PCI: 00:07.3 subordinate bus PCI Express [DEBUG] PCI: 00:07.3 [8086/7ec7] enabled Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Ia1bdc9b5c0533bdddae67b8039103162a57fdc39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67530 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-12src/soc/intel/mtl: Remove Storage UPDSrinidhi N Kaushik
This change removes all references to HybridStorageMode UPD since it has been deprecated starting from FSP v2344_00 BUG=b:245167089 TEST=build coreboot mtlrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I16eb33cb1260484b0651d40211323c6ae986a546 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-12soc/intel/adl: Disable D3cold when legacy S3 is enabledLean Sheng Tan
D3Cold isn't supported in S3. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I072f47737ef38c44b6a676019e9a73868ff17e5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67413 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-10soc/intel/meteorlake: Hook up common code for thermal configurationSubrata Banik
Thermal configuration registers are now located behind PMC PWRMBASE for MeteorLake as well (same as ADL). Hence, using thermal common code to sets the thermal low threshold as per mainboard provided `pch_thermal_trip`. Note: These thermal configuration registers are RW/O hence, setting those early prior to FSP-S helps coreboot to set the desired low thermal threshold for the platform. TEST=Dump thermal configuration registers PWRMBASE+0x150c etc on Google/rex prior to FSP-S shows that registers are now programmed based on 'pch_thermal_trip' and lock register BIT31 is set. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1d6b179a1ed43f00416d90490e0a91710648655e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67462 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-10soc/intel/meteorlake: Update `pch_thermal_trip` for MTLSubrata Banik
This patch updates `pch_thermal_trip` as per Intel MTL vol1 chapter 14. Additionally, dropped the `FIXME` tag for `pch_thermal_trip`. TEST=Able to boot the Google/rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I86f97c9245fe953832d3b408aa902d6a41e55651 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67461 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-09-10soc/intel/meteorlake: Drop redundant `MCHBAR` programming in romstageSubrata Banik
This patch drops redundant MCHBAR programming in romstage as bootblock already done with MCHBAR setting up. TEST=Able to boot Google/Rex to ChromeOS and MCHBAR is set to correct value as per iomap.h Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic2c05f47ab22dc7fe087782a1ce9b7b692ea157e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-10soc/intel/meteorlake: Disable FSP UPDs related to virtualizationSubrata Banik
This patch disables FSP UPDs (`VtdDisable` and `VmxEnable`) as kernel cmdline still passes `intel_iommu=off` to turn off virtualization. BUG=b:241746156 TEST=Able to boot Google/rex to ChromeOS UI. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I21e178a93e311889f2ab7d1a08230d21b051f45e Reviewed-on: https://review.coreboot.org/c/coreboot/+/67452 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-08soc/intel/meteorlake: Hook up PAVP to KconfigSubrata Banik
Expose configuration of Intel PAVP (Protected Audio-Video Path, a digital rights protection/management (DRM) technology for multimedia content) to Kconfig. TEST=Able to boot Google/rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I416346995d744990054c8e0c839ada82c84b7550 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67423 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08soc/intel/common/smbus: Add missing ID for GLKSean Rhodes
PCI ID taken from Intel doc #569262. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I31d4b7edf3288794c86a6d2b78acdc4cf0ac611f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67405 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08soc/intel/commmon/fast_spi: Add missing ID for GLKSean Rhodes
PCI ID taken from Intel doc #569262. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5812e536f3e1c49a272a0b337cc69f3d8f30677f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67402 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-08soc/intel/alderlake: add power limits for Alder Lake-N 7W socSimon Yang
Missing power limit setting for Alder-Lake-N 7W soc. Document reference: 645548 and 646929 BUG=b:245440443 BRANCH=None TEST=Build FW and test on nivviks board and there is no error message "unknown SA ID: 0x4617, skipped power limits configuration." Signed-off-by: Simon Yang <simon1.yang@intel.com> Change-Id: Iefe17f5b574cc319fe9aad3850401a8aa8e31270 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-09-06src/soc/intel: remove force-included header compiler.h from fileMartin Roth
The header file `compiler.h` is automatically included in the build by the top level makefile using the command: `-include $(src)/commonlib/bsd/include/commonlib/bsd/compiler.h`. Similar to `config.h`, 'kconfig.h`, and 'rules.h`, this file does not need to be included manually, so remove it. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I5d3eb3f5e5f940910b2d45e0a2ae508e5ce91609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-06src: remove force-included header rules.h from individual filesMartin Roth
The header file `rules.h` is automatically included in the build by the top level makefile using the command: `-include src/soc/intel/common/block/scs/early_mmc.c`. Similar to `config.h` and 'kconfig.h`, this file does not need to be included manually, so remove it. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I23a1876b4b671d8565cf9b391d3babf800c074db Reviewed-on: https://review.coreboot.org/c/coreboot/+/67348 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-05soc/intel/alderlake: Remove dependency of FSP-S CpuMpPei ModuleSubrata Banik
This patch fixes a hidden issue present inside FSP-S while coreboot decides to skip performing MP initialization by overriding FSP-S UPDs as below: 1. CpuMpPpi ------> Passing `NULL` as coreboot assume FSP don't need to use coreboot wrapper for performing any operation over APs. 2. SkipMpInit -----> Set `1` to let FSP know that coreboot decided to skip FSP running CPU feature programming. Unfortunately, the assumption of coreboot is not aligned with FSP when it comes to the behaviour of `CpuMpPpi` UPD. FSP assumes ownership of the APs (Application Processors) upon passing `NULL` pointer to the `CpuMpPpi` FSP-S UPD. FSP-S creates its own infrastructure code after seeing the CpuMpPpi UPD is set to `NULL`. FSP requires the CpuMpPei module, file name `UefiCpuPkg/CpuMpPei/CpuMpPei.c`, function name `InitializeCpuMpWorker` to perform those additional initialization which is not relevant for the coreboot upon selecting the SkipMpInit UPD to 1 (a.k.a avoid running CPU feature programming on APs). Additionally, FSP-S binary size has increased by ~30KB (irrespective of being compressed) with the inclusion of the CpuMpPei module, which is eventually not meaningful for coreboot. Hence, this patch selects `MP_SERVICES_PPI_V2_NOOP` config unconditionally to ensure pass a valid pointer to the `CpuMpPpi` UPD and avoid APs getting hijacked by FSP while coreboot decides to set SkipMpInit UPD. Ideally, FSP should have avoided all AP related operations when coreboot requested FSP to skip MP init by overriding required UPDs. TEST=Able to drop CpuMpPei Module from FSP and boot to Chrome OS on Google/Redrix, Kano, Taeko devices with SkipMpInit=1. Without this patch: Here is the CPU AP logs coming from the EDK2 (open-source) [UefiCpuPkg/CpuMpPei/CpuMpPei.c] when coreboot sets `NULL` to the CpuMpPpi UPD. [SPEW ] Loading PEIM EDADEB9D-DDBA-48BD-9D22-C1C169C8C5C6 [SPEW ] Loading PEIM at 0x00076F9A000 EntryPoint=0x00076FA24E2 CpuMpPei.efi PROGRESS CODE: V03020002 I0 [SPEW ] Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE [SPEW ] Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 76FA0239 AP Loop Mode is 2 GetMicrocodePatchInfoFromHob: Microcode patch cache HOB is not found. CPU[0000]: Microcode revision = 00000000, expected = 00000000 [SPEW ] Register PPI Notify: 8F9D4825-797D-48FC-8471-845025792EF6 Does not find any stored CPU BIST information from PPI! APICID - 0x00000000, BIST - 0x00000000 [SPEW ] Install PPI: 9E9F374B-8F16-4230-9824-5846EE766A97 [SPEW ] Install PPI: 5CB9CB3D-31A4-480C-9498-29D269BACFBA [SPEW ] Install PPI: EE16160A-E8BE-47A6-820A-C6900DB0250A PROGRESS CODE: V03020003 I0 With this patch: No instance of `CpuMpPei` has been found in the AP UART log with FSP debug enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8ebe0bcfda513e79e791df7ab54b357aa23d295c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66706 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-03soc/intel: Add SI_DESC region to GSCVD rangesJulius Werner
Intel platforms have soft straps stored in the SI_DESC FMAP section which can alter boot behavior and may open up a security risk if they can be modified by an attacker. This patch adds the SI_DESC region to the list of ranges covered by GSC verification (CONFIG_VBOOT_GSCVD). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I0f1b297e207d3c6152bf99ec5a5b0983f01b2d0b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66346 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-02cbfs/vboot: Adapt to new vb2_digest APIJulius Werner
CL:3825558 changes all vb2_digest and vb2_hash functions to take a new hwcrypto_allowed argument, to potentially let them try to call the vb2ex_hwcrypto API for hash calculation. This change will open hardware crypto acceleration up to all hash calculations in coreboot (most notably CBFS verification). As part of this change, the vb2_digest_buffer() function has been removed, so replace existing instances in coreboot with the newer vb2_hash_calculate() API. Due to the circular dependency of these changes with vboot, this patch also needs to update the vboot submodule: Updating from commit id 18cb85b5: 2load_kernel.c: Expose load kernel as vb2_api to commit id b827ddb9: tests: Ensure auxfw sync runs after EC sync This brings in 15 new commits. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-09-02soc/intel/cmn/graphics: Use pci_dev_request_bus_master for BM enablingSubrata Banik
Enabling Bus Master isn't required by the hardware, so we shouldn't need to enable it at all. However, some payloads do not set this bit before attempting DMA transfers, which results in functionality failure. For example: in this case, unable to see the developer screen in Depthcharge. In the prior IA SoC platform, FSP/GFX PEIM does the BM enabling for the IGD BAR resources but starting with the MTL platform, it fails to do so resulting into inability to see the Pre-OS display. BUG=b:243919230 ([Rex] Unable to see Pre-OS display although GFX PEIM Display Init is successful during AP boot) TEST=Able to see the developer screen with eDP/HDMI while booting the Google/Rex. Also, this change doesn't impact the previous platforms (ADL, TGL, CML etc.) where the BM is default enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9ad9eee8379b7ea1e50224e3fabb347e5f14c25b Reviewed-on: https://review.coreboot.org/c/coreboot/+/67273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-01vendorcode/intel/fsp2/glk: Add the FSP headers for version 2.2.3.1Sean Rhodes
Add the headers for 2.2.3.1, which includes the following changes over 2.2.0.0: • [Implemented]GLK: XHCLKGTEN Register setting causes S0ix entry failure in less than 5 cycles when a USB2 Ethernet Dongle is connected. Refer GLK BIOS Spec Volume1 CDI# 571118 under chapter 7.20.6 for new Register settings. • [Implemented] [GLK/GLK-R] DDR4 16Gb SDP Memory support for Gemini Lake/Gemini Lake – R • [Update] MRC new version update to 1.38. • [Fixed][GLK-R][WLAN] Removed the DSW function - Wake on LAN from S4 issue with latest Wifi driver. [Update] MRC new version update to 1.39. Included fix for MinRefRate2xEnable and support for Rowhammer mitigation. • [Fixed] Disable Dynamic DiffAmp and set CTLE from 7 to 5. This change specific to DDR4 memory configuration. • GLK Klocwork Fix • [Update] MRC new version update to 1.40. Added in a separate directory as the default. The 2.2.0.0 headers were left and will be used for Google boards, as some offsets have moved. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I09498368b116c2add816eeada2fa4d0dba6e5765 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-08-31soc/intel/alderlake: Add new pcie5 alias for raptorlakeBora Guvendik
Pcie5_1 is added for DID 0xA72Dh and BDF 0/1/1. References: RaptorLake External Design Specification Volume 1 (640555) BUG=b:229134437 BRANCH=firmware-brya-14505.B TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Id7440bf202d5560ff92807877d48b94054cb1de9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-30soc/intel/cmn/block/acpi: Add new GPIO ASL MethodTim Wawrzynczak
Ths new Method, GSCI, allows control over whether or not IRQs are routed as SCI#s for the given GPIO. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic61caaf77d2c6e295e67a1501544e8b8fc6f3b6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66813 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-30soc/intel/cmn/block/acpi: Modify GPIO Methods to use bitfieldsTim Wawrzynczak
IMHO, using bitfields directly in the Field declaration makes the ASL code more readable then directly manipulating the entire 32-bit dword. TEST=ACPI code using several of these Methods still works (google/agah dGPU ACPI code) Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I9909700022d8b55db3f5208010bdff11ddaf4e7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66812 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-29soc/intel/alderlake: Rename pcie5 aliasBora Guvendik
Rename pcie5 alias as pcie5_0 since raptorlake is adding a new pcie5 RC. BRANCH=firmware-brya-14505.B TEST=none Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Iee669e68e3607b7ffec9f0800e9f0a916defd498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-26soc/intel/meteorlake: Update MTL_USE_COREBOOT_MP_INIT descriptionSridhar Siricilla
The patch update MTL_USE_COREBOOT_MP_INIT Kconfig description. TEST=Build code for MTL Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I38609cb03714084dd9092f41dd6e5b418a7f120a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-26soc/intel/mtl: Activate TME on all CPUsTarun Tuli
This patch runs `set_tme_core_activate()` on all CPUs (BSP+APs) as per MTL processor EDS. TEST= Able to build and boot RVP. Confirmed TME supported mode detected via temporary debug prints and MSR 0x9ff indicates activated. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Id368925504d81025239e94698d2cb0e2266a5a96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66949 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSSJohn Zhao
This change provides access to IOE through P2SB Sideband interface for Meteor Lake TCSS functions of pad configuration and Thunderbolt authentication. There is a policy of locking the P2SB access at the end of platform initialization. The tbt_authentication is read from IOM register through IOE P2SB at early silicon initialization phase and its usage is deferred to usb4 driver. BUG=b:213574324 TEST=Built coreboot and validated booting to OS successfully on MTLRVP board. No boot hung was observed. Signed-off-by: John Zhao <john.zhao@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8dcee90080c6e70dadc011cc1dbef3659fdbc8f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66951 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26soc/intel/p2sb: Refactor `p2sb_execute_sideband_access` functionSubrata Banik
This patch refactors p2sb_execute_sideband_access() to be able to handle SBI operations in both SMM and non-SMM scenarios. Prior to FSP-S operation being done, the IOE P2SB device will be visible on the PCI bus hence, performing the SBI operation using IOE P2SB doesn't involve unhide/hide operation. Post FSP-S, the IOE P2SB device is hidden. Additionally, SBI operations can't be performed as is. The only possible way to send SBI is inside SMM mode and to do that, coreboot needs to unhide the P2SB device prior to sending the SBI and hide it post sending SBI. As a result, the p2sb_execute_sideband_access() function has been refactored to manage these cases seamlessly without users of the p2sb_execute_sideband_access() actually being bothered about the calling mode. BUG=b:239806774 TEST=Able to perform p2sb_execute_sideband_access() function call in both SMM and non-SMM mode without any hang/die. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iafebd5190deb50fd95382f17bf0248fcbfb23cb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-25soc/intel/mtl: Hook up Lp5CccConfig FSP UPDKapil Porwal
Hook up Lp5CccConfig FSP UPD for Intel MeteorLake. BUG=b:243734885 TEST=Built and booted on Google Rex. Verified the UPD value in MRC log. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3d7ff8e08546f06cf7807ee825cfef84c14a6c5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/67052 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-25soc/intel/mtl: Hook up ECT FSP UPDKapil Porwal
Hook up ECT FSP UPD for Intel MeteorLake. BUG=b:243734885 TEST=Built and booted on Google Rex. Verified the UPD value in MRC log. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Idc23717c3ce52e3635e2da41733058f912545e5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/67051 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-25soc/intel/mtl: Program MCHBASE prior enabling extended bios rangeSubrata Banik
This patch resolves the SoC programming dependency order where enabling extended bios support requires MCHBASE to be enabled. BUG=b:243693375 TEST=Able to boot from RW-A slot which is mapped to extended BIOS range. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8bd9c3d3fb5e82e34f2d6af8548452c744d4b3c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67046 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24soc/intel/common/block: Drop empty smm.hAngel Pons
This file has nothing useful. Get rid of it. Change-Id: Id2a42005d3b4b5161079c9ff48867cfc6fb0413d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-24soc/intel/adl: Consider INTEL_TME config prior TME MSR programmingSubrata Banik
This patch brings INTEL_TME config check prior programming TME Set Activation Core MSR on all cores. TEST=Able to boot Google/Taeko to OS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8af7e305da1050f443929ab33be556e713e53e9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66976 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-24soc/intel/alderlake/hsphy: Add support for HSPHY firmware loadingMichał Żygowski
BIOS must send the IP_LOAD HECI command to fetch the firmware for CPU PCIe Gen5 and upload it via CPU REG BAR prior FSP Silicon Init. Implementation based on public Slimbootloader's "Silicon/AlderlakePkg/Library/CpuPcieHsPhyInitLib". TEST=Boot MSI PRO Z690-A and see the HSPHY FW is loaded. PCIe x16 Gen3 GPU card started working in the PCIE 5.0 slot. [DEBUG] HECI: Sending Get IP firmware command [DEBUG] HECI: Get IP firmware success. Response: [DEBUG] Payload size = 0x6944 [DEBUG] Hash type used for signing payload = 0x3 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6c6c11581e3d3d9bab0131fae6ef487cafe98080 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-08-24soc/intel/meteorlake: Enable GPIO 4 bits pad mode configurationJamie Ryu
This enables SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS to support 4 bits GPIO pad mode to configure native function 8 to 15. BUG=b:239690757 TEST=build and verify pad mode configuration with Meteor Lake mtlrvp Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Ibf4b13a3d19095d15bf857c7fe4ec0affb54a4e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66391 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-24soc/intel/common/gpio: Support 4 bits GPIO pad mode configurationJamie Ryu
Intel GPIO pad supports 4 bits pad mode, PAD_CFG_DW0[13:10] for pins that native function 8 to 15 is assigned. This adds native function definitions from NF8 to NF15 and updates PAD_CFG0_MODE_MASK to support 4 bits pad mode configuration. Since PAD_CFG_DW0[16:13] is reserved for pins that NF8 or higher is not assigned, this change would not cause an issue but Kconfig option is added to minimize an impact and support 4 bits pad mode configuration. BUG=b:239690757 TEST=build and verify pad mode configuration with Meteor Lake mtlrvp Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Iefd2daa92a86402f2154de2a013ea30f95d98108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-23{sb,soc}/intel: Do not require hda_verb.cAngel Pons
Just use the conditional inclusion through `device/Makefile.inc`. Change-Id: Id363a97460ae2cfe4b10d491d4ef06394eb530c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-22soc/intel/alderlake: Perform TME core activation on all CPUsSubrata Banik
This patch runs `set_tme_core_activate()` on all CPUs (BSP+APs) as per Alder Lake Processor EDS. TEST= Able to build and boot Google/Redrix. Dumping MSR 0x9FF on all logical processors shows zero value being set. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I130480d4fba413d47d0d0137932ec1fb041a88d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66753 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-22soc/intel/cmn/cpu: API to set TME core activationSubrata Banik
This patch implements API to program TME core activation MSR 0x9FF. Write zero to TME core activate MSR will translate the TME_ACTIVATE[MK_TME_KEYID_BITS] value into PMH mask register. Note: TME_ACTIVATE[MK_TME_KEYID_BITS] = MSR 0x982 Bits[32-35] TEST=Able to build and boot Google/Redrix. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I48cf8e255b294828ac683ab96eb61ad86578e852 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-21soc/intel: Enable TME based on supported CPU SKU and config optionSubrata Banik
This patch removes the static kconfig being used to fill in TME enable FSP UPD. Instead use`is_tme_supported()` and `CONFIG(INTEL_TME)` to check if the CPU has required TME support rather than hardcoding. TEST=FSP debug log shows `TmeEnable` UPD is set appropriately for the TME-supported CPU SKUs. As per FSP-M debug log: Without this CL, Alder Lake-P CPU SKU without TME support: [SPEW ] TmeEnable = 0x1 With this CL, Alder Lake-P CPU SKU without TME support: [SPEW ] TmeEnable = 0x0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8aa2922baaf2a49e6e2762d31eaffa7bdcd43b0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66750 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-21soc/intel/common/block/cpu: API to check if TME is supportedSubrata Banik
As per the Alder Lake FAS coreboot shall detect the existence of TME feature by running the CPUID instruction: CPUID leaf 7/sub-leaf 0 Return Value in ECX [bit 13]=1 If TME is supported then only access to TME MSRs are allowed otherwise accessing those MSRs would result in GP#. TEST=Able to detect the existence of TME feature across different Alder Lake and Meteor Lake CPU SKUs. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibd4fcf15a66d27748ac7fbb52b18d7264b901cd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66749 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-21soc/intel: Unravel `INTEL_TME` Kconfig optionAngel Pons
The `INTEL_TME` Kconfig option has a prompt, which means it is meant to be user-configurable. However, it has been selected from Alder Lake and Meteor Lake Kconfig, so `INTEL_TME` cannot be disabled on them. Replace the `select INTEL_TME` statements with default values in order for this option to be user-configurable on all platforms that support it. Change-Id: Ib37c108fcc1004840b82be18fd23c340a68ca748 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66756 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-21intel/systemagent: Align debug outputNico Huber
Output should be easier to read as a table. Change-Id: I32e3e0aab5afd25c0b004d18f64de76445d9a0ed Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-08-19soc/intel/alderlake: Add support to skip the MBP HOBV Sowmya
This patch adds the support to enable/disable skipping MBP HOB from the devicetree based on mainboard requirement. Only ADL-N FSP has the required support to skip the MBP HOB and enabling it is saving the Boot time. BUG=b:241850107 TEST=Build and boot to verify that the right value has been passed to the FSP. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Iddeb2c652fac9513b14139d6f732d333bbb989d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-18soc/intel/tigerlake/fsp_params.c: Add INT D routing for PEG60Frans Hendriks
Debian 11 reports ´0:6:0 can´t derive routing for PCI INT D´. Use FIXED_INT_PIRQ for INT D to PIRQ routing table. BUG=NA TEST=Boot Debian 11 on Siemens AS_TGL1 and verify no PIRQ error message in ´dmesg´ Change-Id: If38c7b6f664e0f6533e583ce62504281a4092720 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-08-18Revert "soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSS"Subrata Banik
This reverts commit eb80b1efa36c99e485b2604e913c2aa316168eea. Reason for revert: Results into hard hang with serial debug msg inside FSP-S. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8e7cf804828da8939f591eb0770c8daf830c8d94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-17soc/intel/apollolake: Add the remaining CSE Firmware Status RegistersSean Rhodes
Add the Shadow Registers from 2 through 5 and print information from them accordingly. All values were taken from Intel document number 571993. Tested on the StarLite Mk III and the correct values are shown: [DEBUG] CSE: IBB Verification Result: PASS [DEBUG] CSE: IBB Verification Done : YES [DEBUG] CSE: Actual IBB Size : 88 [DEBUG] CSE: Verified Boot Valid : FAIL [DEBUG] CSE: Verified Boot Test : NO [DEBUG] CSE: FPF status : FUSED Please note, the values shown are in an error state. This replaces the Fuse check that is done via Heci, as this will only work whilst the CSE is in a normal state. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8a9e7b329010fae1a2ed9c3fefc9765e617cdfe4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-17soc/intel/apollolake: Enable DPTF & SMBus as it is a required deviceSean Rhodes
coreboot is unable to disable certain devices, whilst many are hidden DPTF and SMBus are not. Set this to enabled chipset so that it is enabled by default. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I85d74179b6fe3c6126566422f82f7b806f80d0c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-17soc/intel/tigerlake: Disable DISPLAY_FSP_VERSION_INFO on IOTFrans Hendriks
Build error for platforms using Intel FSP for TGL_IOT (FSP_TYPE_IOT). File FirmwareVersionInfoHob.h does not exist in Intel FSP TGL IOT package. File FirmwareVersionInfoHob.h is included when DISPLAY_FSP_VERSION_INFO is enabled. Enable this config for non TGL_IOT only. BUG = NA TEST = Verify that DISPLAY_FSP_VERSION_INFO is disabled by default for TGL_IOT configuration (Build Siemens AS_TGL1). Change-Id: Ief5a7222daf6f1658e8dc04f97b4ddc2bcb74905 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66636 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>