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AgeCommit message (Expand)Author
2020-07-25soc/intel/baytrail/elog.c: Align with BraswellAngel Pons
2020-07-25soc/intel/baytrail/cpu.c: Align with BraswellAngel Pons
2020-07-25soc/intel/baytrail/acpi.c: Align with BraswellAngel Pons
2020-07-25soc/intel/baytrail/bootblock/bootblock.c: Move functionsAngel Pons
2020-07-25soc/intel/baytrail: Retype some pointersAngel Pons
2020-07-25soc/intel/tigerlake: Update Pkg C-State latenciesRavi Sarawadi
2020-07-25soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKUSumeet R Pawnikar
2020-07-25soc/intel/tigerlake: Update Tiger Lake SA IDsDerek Huang
2020-07-24soc/intel/common/gpio_defs: Remove unused macro for NFMaxim Polyakov
2020-07-24soc/intel/common/gpio_defs: Undo set TxDRxE in GPI_TRIG_OWN()Maxim Polyakov
2020-07-24soc/intel/common/gpio_defs: Improve some GPI macrosMaxim Polyakov
2020-07-23soc/intel/xeon_sp/cpx: display SystemMemoryMapHob fieldsJonathan Zhang
2020-07-23soc/intel/jasperlake: Add the SkipCpuReplacementCheck configurationV Sowmya
2020-07-22soc/intel/jasperlake: Move tco_configure to bootblockTim Wawrzynczak
2020-07-22soc/intel/cannonlake: Move tco_configure to bootblockTim Wawrzynczak
2020-07-21soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2Subrata Banik
2020-07-21src: Use ACPI macrosElyes HAOUAS
2020-07-21soc/intel/baytrail: Add new CPUID 0x30679Mate Kukri
2020-07-21soc/intel/xeon_sp/cpx: remove unused gpio.hMaxim Polyakov
2020-07-20src: Report word-sized access for PM1a_EVTAngel Pons
2020-07-20src: Make HAVE_CF9_RESET set the FADT reset registerAngel Pons
2020-07-20src: Drop useless cache flush settings in FADTAngel Pons
2020-07-20src: Never overwrite `fadt->flags`Angel Pons
2020-07-20soc/intel/xeon_sp/skx: Clean up FADTAngel Pons
2020-07-20src: Drop useless PM1b settings from FADTAngel Pons
2020-07-20src: Drop useless GPE1 settings from FADTAngel Pons
2020-07-20soc/intel/cannonlake: Add configs for USB 3.1 Gen2 EV settingsJamie Chen
2020-07-19soc/intel/common/gpio_defs: Fix coding styleMaxim Polyakov
2020-07-16soc/intel/common/block/pmc: Select PMC on mainboard basisTim Chu
2020-07-16mb/ocp/deltalake: Config PCH PCIe ports in devicetreeMorgan Jang
2020-07-15soc/intel/tigerlake: Hook up SATA Port Enable DITO UPDsShaunak Saha
2020-07-15PCI IDs: Add PCI ID for JSL DPTF/DTT PCI deviceTim Wawrzynczak
2020-07-14soc/intel/skylake: Move `acpi_fill_fadt` to fadt.cAngel Pons
2020-07-14soc/intel/braswell: Move `acpi_fill_fadt` to fadt.cAngel Pons
2020-07-14soc/intel/baytrail: Move `acpi_fill_fadt` to fadt.cAngel Pons
2020-07-14soc/intel/broadwell: Move `acpi_fill_fadt` to fadt.cAngel Pons
2020-07-14src: Drop unused <cpu/x86/tsc.h> includeElyes HAOUAS
2020-07-14src: Remove unused 'include <cpu/x86/msr.h>'Elyes HAOUAS
2020-07-14soc/intel/baytrail/northcluster.c: Add missing includeElyes HAOUAS
2020-07-14soc/intel/baytrail/romstage/pmc.c: Add missing includeElyes HAOUAS
2020-07-14soc/intel/baytrail/romstage/raminit.c: Add missing includeElyes HAOUAS
2020-07-14soc/intel/braswell/romstage/romstage.c: Add missing includeElyes HAOUAS
2020-07-14src: Remove unused 'include <stdint.h>Elyes HAOUAS
2020-07-14src: Remove unused 'include <types.h>'Elyes HAOUAS
2020-07-12soc/intel/baytrail: Add dedicated devices for MMC and MMC 4.5 controllerMate Kukri
2020-07-12soc/intel/gpio: Convert PAD_CFG0_ROUTE_* to PAD_IRQ_ROUTE()Maxim Polyakov
2020-07-12soc/intel/gpio: Convert PAD_CFG0_RX_POL_* to PAD_RX_POL()Maxim Polyakov
2020-07-12intel/gpio: Convert PAD_CFG0_TRIG_* to PAD_TRIG()Maxim Polyakov
2020-07-12soc/intel/common/block/pcie: Select ASPM on mainboard basisChristian Walter
2020-07-12soc/intel/xeon_sp/cpx: use HOB_TYPE_GUID_EXTENSION to interpret platform HOBsJonathan Zhang
2020-07-12soc/intel/xeon_sp: Add RTC failure checkingJingle Hsu
2020-07-12vendocode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww28 release and adapt socJonathan Zhang
2020-07-12soc/intel/tigerlake: Move tco_configure to bootblockTim Wawrzynczak
2020-07-12soc/intel/tigerlake: Configure Type-C Input Output Manager(IOM) deviceJohn Zhao
2020-07-12soc/intel/tigerlake: Add Type-C IOM base address and size macroJohn Zhao
2020-07-12soc/intel/tigerlake: Add new IGD deviceRavi Sarawadi
2020-07-09soc/intel/broadwell/pcie.c: Drop dead codeAngel Pons
2020-07-09soc/intel/baytrail/pmutil.c: Constify string arraysAngel Pons
2020-07-09soc/intel/baytrail/pmutil.c: Do not hardcode num_bitsAngel Pons
2020-07-09soc/intel/baytrail: Align whitespace and commentsAngel Pons
2020-07-09soc/intel/baytrail: Rename "pmc.h" to "pm.h"Angel Pons
2020-07-09mainboard/intel/tglrvp: Remove unused PrmrrSize chip configSubrata Banik
2020-07-09soc/intel/braswell: Drop some BIOS_SPEW printk'sAngel Pons
2020-07-09soc/intel/braswell/lpss.c: Use 16-bit ops on PCI COMMANDAngel Pons
2020-07-07soc/intel/common/block: Add new block DTTTim Wawrzynczak
2020-07-07soc/intel/tigerlake: Disable Thunderbolt PCIe root ports bus masterJohn Zhao
2020-07-07soc/intel/{tiger,jasper}lake: Add IPU to soc_acpi_nameTim Wawrzynczak
2020-07-07soc/intel/common: Add a minimal PCI driver for IPUTim Wawrzynczak
2020-07-07lp4x: Add new memory parts and generate SPDsDavid Wu
2020-07-06src/**/acpi/smbus.asl: Drop dead codeAngel Pons
2020-07-06soc/intel: Drop unused `#include <reg_script.h>`Angel Pons
2020-07-06soc/intel/jasperlake: set SerialIoUartDebugMode to skip Uart InitMaulik V Vaghela
2020-07-04soc/intel/xeon_sp/cpx: update HOB display codeJonathan Zhang
2020-07-04soc/intel/xeon_sp: Add read CPU PPIN MSR functionJohnny Lin
2020-07-04soc/intel/tigerlake: Remove unused EHL DID from TGL SoCSubrata Banik
2020-07-03soc/intel/tigerlake: Disable hybrid storage mode in CSE Lite RO bootJamie Ryu
2020-07-03drivers/intel/pmx_mux: Remove redundant declarationKyösti Mälkki
2020-07-03soc/intel/common: Only touch Time Window Tau bits in supported SoCsTim Wawrzynczak
2020-07-01soc/intel/tigerlake: Switch to CSE Lite RW at BS_DEV_INIT_CHIPS entryJamie Ryu
2020-07-01soc/intel/cannonlake: make satahotplug user configurable via devicetreeJonas Loeffelholz
2020-07-01soc/intel/common/cpu: Don't set any TCC settings if offset is 0Tim Wawrzynczak
2020-07-01soc/intel/skylake: Update ASL syntax in xhci.aslEdward O'Callaghan
2020-07-01soc/intel/tigerlake: Add platform wide _OSC capabilities for USB4John Zhao
2020-07-01ACPI GNVS: Replace uses of smm_get_gnvs()Kyösti Mälkki
2020-06-30soc/intel/cannonlake: Add UWES ASL into xhci.aslEdward O'Callaghan
2020-06-30jasperlake: enable tcc_offset functionalitySumeet R Pawnikar
2020-06-30tigerlake: enable tcc_offset functionalitySumeet R Pawnikar
2020-06-30ACPI: Drop typedef global_nvs_tKyösti Mälkki
2020-06-30soc/intel/tigerlake: Add CpuReplacementCheck to chip optionsJamie Ryu
2020-06-30soc/intel/tigerlake: Avoid NULL pointer dereferenceJohn Zhao
2020-06-30src: Remove whitespaces before tabsElyes HAOUAS
2020-06-29soc/intel/tigerlake: Run pmc_set_acpi_mode() during .init in pmc_opsWilliam Wei
2020-06-28vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww24 release and adapt socJonathan Zhang
2020-06-28soc/intel/common: add TCC activation functionalitySumeet R Pawnikar
2020-06-28soc/xeon_sp/cpx: Define MSR PPIN related registersJohnny Lin
2020-06-27soc/intel/broadwell: Use common early SPI codeAngel Pons
2020-06-25soc/intel/cannonlake: Add PchPmPwrCycDur to chip optionsSridhar Siricilla
2020-06-25drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1Jonathan Zhang
2020-06-25soc/intel/xeon_sp: use edk2-stable202005 headersJonathan Zhang
2020-06-25soc/intel/xeon_sp/cpx: display UPDs and CPX-SP specific HOBsJonathan Zhang