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Change-Id: I311269967949533264e44fd3bb29ad3a06056653
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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coreboot have an option to use legacy UART or LPSS UART. FSP will use the
UART initialized by coreboot and we can choose an option to skip Uart
initialization by FSP.
For this, we need to pass correct debug interface flag to FSP through
which FSP will know which UART port to use. If we don't pass correct
interface information, FSP may try to dump logs on that port and it may
slow down the system.
BUG=none
BRANCH=none
TEST=Compile and boot with coreboot. Check FSP and coreboot logs are
coming on serial port.
Change-Id: I1ebb20c93e2c15ec085538509099de72bc9dd62c
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update the Kconfig option for disabling ESPI SMI source
to disable it entirely, not just when ACPI mode is disabled.
For the situations where this is needed (just the sarien
board) it is better to completely stop the EC from sending
any SMI events as no actions are taken.
Change-Id: Id94481bb2f0cfc948f350be45d360bfe40ddf018
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch adds required FSP UPD changes for CometLake SoC.
Also this patch tries to create common parse logic for CometLake as
well as cannonlake SOC.
We parse device tree parameters for PCI devices and fill values in FSP
UPDs. We fill UPDs based on pci device config as well as SerialIoDev
config of devicetree.
For PCI devices, if PCI device is disabled from devicetree, we'll assign
disable value to FSP UPD.
In case devicetree doesn't fill this parameter or value is invalid in
SerialIoDev config, default mode will be set to PCI.
In case of valid value, we'll fill the same value into FSP UPD.
BUG=none
BRANCH=none
TEST=check if CML board boots and proper UPD values are filled.
Change-Id: Ib92b660409ab01d70358042b2ed29b8bf9cab26d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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Change-Id: Ie7afe77053a21bcf6a1bf314570f897d1791a620
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I9b4d72116a66d5a256659fa82682497ef3481e77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Move ChipsetFspReturnPoint() to drivers/intel/fsp1_0.
Allows to have a common entry after FSP-M.
Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
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CNL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A
and so this change updates the check for these bits to use GEN_PMCON_A
instead of GEN_PMCON_B.
BUG=b:128482282
TEST=Verified that prev_sleep_state is reported correctly when booting
from S5.
Change-Id: I75780a004ded8f282ffb3feb0cdc76233ebfd4f2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31908
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to support mainboards that do not store DRAM part number in
the traditional way i.e. within the CBFS SPD for soldered memory, this
change provides a runtime callback to allow mainboards to provide DRAM
part number from a custom location e.g. external EEPROM on hatch.
For other boards it should be a NOP since the weak implementation of
mainboard_get_dram_part_num does nothing.
BUG=b:127609572
Change-Id: I9b2d4c33fc378b9a24b111971ec2bfdb5f8d57d0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31850
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use <arch/acpi.h> when appropriate.
Change-Id: I05a28d2c15565c21407101e611ee1984c5411ff0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Some Apollo Lake mainboards use SeaBIOS as payload. SeaBIOS requires the
initialization of the programmable interrupt controller (PIC) for
faultless operation. The PIC mode is need for USB support (e.g.
keyboard, memory stick) and for some Option ROMs (e.g. PXE ROM).
Therefore add setup_lapic() to configure the APIC.
Change-Id: I00b339ce1850729023db74da7f8845927a95dcc6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31802
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This patch adds support for logging wake source information in gsmi
callbacks. With this change, all the elog logging infrastructure can
be used for S0ix as well as S3 on cannonlake.
BUG=b:124131938
BRANCH=none
TEST=Verified that the wake events are logged during the S0ix resume:
6 | 2019-03-04 17:03:13 | S0ix Enter
7 | 2019-03-04 17:03:17 | S0ix Exit
8 | 2019-03-04 17:03:17 | Wake Source | RTC Alarm | 0
9 | 2019-03-04 17:03:55 | S0ix Enter
10 | 2019-03-04 17:03:56 | S0ix Exit
11 | 2019-03-04 17:03:56 | Wake Source | GPE # | 21
12 | 2019-03-04 17:04:36 | S0ix Enter
13 | 2019-03-04 17:04:45 | S0ix Exit
14 | 2019-03-04 17:04:45 | Wake Source | GPE # | 112
15 | 2019-03-04 17:05:01 | S0ix Enter
16 | 2019-03-04 17:05:09 | S0ix Exit
17 | 2019-03-04 17:05:09 | Wake Source | Power Button | 0
Change-Id: Id627843e22c2524dfa94395b780cf2134f386137
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change moves soc_fill_power_state and soc_prev_sleep_state to
pmutil.c. It allows the functions to be used across romstage and smm.
BUG=b:124131938
BRANCH=none
TEST=none
Change-Id: If24c3feeb77f4fb692ef0bf38d537b2b54de3c36
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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CPU PM TIMER EMULATION logic will help UEFI payload to execute rather
wait for time tick in absence of TCO and ACPI PM timer after FSP-S.
BUG=N/A
TEST=Able to build and boot with tianocore payload.
Change-Id: I7fd11e728b7a14f41f08bc39bcd92a42a8aa6cff
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I7e181111cd1b837382929071a350b94c3afc1aaa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This patch adds support H110 chipset (Sunrise Point) for Skylake and
Kaby Lake processor families by adding the corresponding IDs. It has
been tested on ASRock H110M-DVS motherboard (Skylake i5-6600 CPU).
Change-Id: I85ba65ac860687b0f9fd781938e5cac21a1b668d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31602
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds support
1) Intel(R) Xeon(R) E3 - 1200/1500 v5/6th Gen Intel(R) Core(TM) Host
Bridge/DRAM Registers - 191F;
2) HD Graphics 530 Skylake GT2 - Intel integrated graphics processor
https://en.wikichip.org/wiki/intel/hd_graphics/530.
This is required to run coreboot on the Intel Core i5-6600 (Skylake)
desktop processor. It has been tested on ASRock H110M-DVS motherboard.
Change-Id: If47e9ac32813a9f73d3a23f44536f60d1003971d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31601
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add SPI_OPTYPE_XXX values for the SPI controller.
BUG=N/A
TEST=flashrom on Facebook FBG-1701
Change-Id: Id183d68b3a80b2e7ab1a0685580d79ca327db03a
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Intel Braswell P-UNIT is missing in pci_devs.h
Add PUNIT device, function and device ID
BUG=N/A
TEST=Facebook FBG-1701 booting Embedded Linux
Change-Id: I80c87c8964b3ba830571e0c03c424b67729a0c1a
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31711
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I1f44ffeb54955ed660162a791c6281f292b1116a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The other DEFAULT_ entries are just immediate
constants.
Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Call the simple PCI config accessors directly.
Change-Id: I2c6712d836924b01c33a8435292be1ac2e530472
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This IS_ENABLED(XXX) line should've clearly been IS_ENABLED(CONFIG_XXX).
This patch can fix that. However, I don't have (and don't plan to
acquire) an affected system to test, so approve at your own risk (or
let me know if I should just remove that check instead).
Change-Id: I79a0fca65853798ee45c3779b437864ba3cf2b1e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Intel Braswell SoC contains SMBus controller but no support
is available for this controller.
This controller is compatible with the Intel SMBus support in the
southbridge common directory.
To be able using smbus support from the Intel common directory
the smbus.c is moved outside SOUTHBRIDGE_INTEL_COMMON
dependency block.
Use SOUTHBRIDGE_INTEL_COMMON_SMBUS to include support.
BUG=N/A
TEST= Facebook FBG-1710 LCD panel
Change-Id: Ie3d4f657558a1aed21b083ef5cad08ea96e629c3
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I91158452680586ac676ea11c8589062880a31f91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31692
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fixes indirect includes that would break with followup work.
Change-Id: I37ca01b904a0b422a4d09475377e755e167a6ab3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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These resolved to <device/oprom/include/io.h> which
included <arch/io.h> that we really wanted.
Change-Id: I9aa0bdf34cd1d53e20b4494c7986f0878f4fd840
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31693
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move common definitions for PCH H and LP to a common header.
Change-Id: If47692ecb05134db1ee6c0fb10125d6a1b67f127
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31621
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the ISH ACPI device so we can hang fields off of a _DSD table.
Since this is also a PCI device that has run time probing, we can always
emit the ACPI device and let the device tree turn the device on or off.
BRANCH=none
BUG=b:122722008
TEST=verify that _DSD table gets publish under ISH device in kernel ACPI
tables. Also verified that device is still turned off if device tree for
ISH is off.
Change-Id: Ic0231f1ac637fea0e251eb3ac84f0fd8d64c12b2
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31681
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The following remarks show up during cannonlake based platform coreboot
build:
dsdt.asl 55: Offset (0x00),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 136: Offset (0xa8),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Address those two remarks in coreboot.
BUG=N/A
TEST=Build coreboot and check build log to see no more remark.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Iad660347b32d90ac1176654820375e30a21b5ffe
Reviewed-on: https://review.coreboot.org/c/31666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Local APIC was not configured.
Add setup_lapic() to configure the APIC.
BUG=N/A
TEST= Ubuntu 4.15.0 reports correct local APIC information
on Intel CherryHill CRB
Change-Id: Ic1da5b1bf235f34b957142e86c70a9dbfa3ded1d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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HDA support did not configure the codecs correclty.
Use Intel common block support to configure the codecs.
To use common Intel HDA support file hda.c file has been
removed and Braswell HDA device ID is added to list of
supported PCI devices in intel/common/block/hda/hda.c.
CONFIG_SOC_INTEL_COMMON_BLOCK and
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA are enabled
to include hda.c in build.
When codec table is available at board level
SOC_INTEL_COMMON_BLOCK_HDA_VERB must be enabled
and a codec table must be supplied.
BUG=N/A
TEST=Facebook FBG-1701 ALC298 configuration
Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Since ACPI v2.c, this field is access_size.
Currently, coreboot is using ACPI v3,so we can drop '.resv' field.
Change-Id: I7b3b930861669bb05cdc8e81f6502476a0568fe0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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We had two ways to configure the serial IRQ mode. One time in the
devicetree for FSP and one time through Kconfig for coreboot. We'll
use `enum serirq_mode` from soc/intel/common/ as a devicetree option
instead. As the default is `quiet mode` here and that is the most
common mode, this saves us a lot of lines.
In four cases kblrvp8, 11 and librem 13v2, 15v3, we had conflicting
settings in devicetree and Kconfig. We'll maintain the `continuous`
selection, although it might be that coreboot overrode this earlier
on the kblrvps.
Note: A lot of Google boards have serial IRQ enabled, while the pin
seems to be unconnected?
Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0.
The value for this field is zero but 1 is allowed to maintain
compatibility with ACPI 1.0.
So set this value to zero as we are using greater version than ACPI 1.0.
Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29986
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Calculation of memory reserved by FSP is incorrect.
Use CBMEM_ID_FSP_RESERVED_MEMORY to determine the memory area
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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This patch adds SOC_INTEL_COMETLAKE Kconfig option.
Change-Id: I2b0c269ade84d72cffaf59a0b53e0d6e3a84b835
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31282
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ISA dma controller is not configured.
Add call isa_dma_init().
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ib7af3f4ef6d6a29628bb2c27d32071be63ff6af2
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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The level/edge mode of PIRQ is not configured and i8259 PIC not initialized.
Add calls to:
- i8259_configure_irq_trigger()
- setup_i8259()
- write_pci_config_irqs()
to correct the configuration of interrupts.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I128cb35dd0e348a9cd9fb162651e0aa2b7e4a3ef
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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IRQ10 and 11 are not available as _PRS in all LNKx ResourceTemplates.
These interrupt numbers are added to all LNKx.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ie7a263d7d50f7f85e6195777c1429dcc27a15604
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29287
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change ac8c60e (soc/intel/cannonlake: Disable ACPI mode as part of
pmc_soc_init) moved disabling of ACPI mode to pmc_soc_init to keep it
more aligned with the behavior on other Intel SoCs. However, as the
PMC device is hidden, it never gets enumerated and so init function
does not get called for it. This change moves the call to disable ACPI
mode to exit of BS_DEV_INIT instead.
BUG=b:126016602
TEST=Verified that:
1. pmc_set_acpi_mode is actually getting called.
2. EC panic event gets logged to eventlog correctly.
Change-Id: Ie7025e322fa0abc21367a520184a4c7741eba1e6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31633
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: If7190ac105b2a65a9576709955c3cc840b95dcdf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Fix cases of using ENV_SMM where __SIMPLE_DEVICE__
should be used instead.
Change-Id: I385c82767a87ff7a47466a200488fae9fc8b863d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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TEST=Verify PM_STS1 value is is not 0xFF.
Change-Id: I932585f6e7525830bd57ecfc372bf3120e7cca66
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/31434
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds CML-U 2+2 SA DID into systemagent.c and report
platform.
Change-Id: I2e882a560dd0a1e96d6e1405735c6f7389c0db5a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31638
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes duplicate pm timer emulation macros from soc
directory and makes use from common code msr.h
Change-Id: I6ec347e7464f785862e855817ec8308e3d207bb1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31610
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For fast CBMEM console use minimum BIOS_DEBUG level.
For other consoles, Kconfig and/or nvram settings
apply.
Change-Id: Iff56a0a3182f258200cac80e013957d598cc2130
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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SD controller in CNL-PCH provides a ability to configure the behavior of
SD_VDD1_PWR_EN# as an active high or low signal. FSP provides an UPD
"SdCardPowerEnableActiveHigh" to control the same.
However, for platforms using SD_VDD1_PWR_EN# as active high, the SDXC
card connector is always powered and may impact system power. This is because
SD_VDD1_PWR_EN# does not de-assert during SDXC D3 or when SD card is not
inserted.
Workaround is to change the pad ownership of SD_VDD1_PWR_EN to GPIO and
force the TX buffer to low in _PS3. And restore the pad mode to native
function in _PS0.
Hence add a Kconfig option to update the UPD, which the board can select
based on how the SD_VDD1_PWR_EN is implemented on it. And, the workaround
gets applied based on this config.
BUG=b:123350329
Change-Id: Iee262d7ecdf8c31362aec3d95dd9b3e8359e0c25
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31445
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a function in gpio ASL library to enable/disable pad Rx/Tx Buffers.
BUG=b:123350329
Change-Id: I6c40d79debb61b0c4e96e485b410d446b77d9cf6
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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PMC initialization on Cannon Lake happens earlier in the boot sequence
than other SoCs because FSP-Silicon init hides PMC from PCI bus. As
ACPI disabling was done as part of PMC init, it was being called
earlier than what other SoCs do. This resulted in a different order of
events for some drivers e.g. ChromeOS EC. In case of ChromeOS EC, it
ended up clearing EC events (which happens as part of ACPI disabling
in SMM) before logging any events of interest that happen during
mainboard initialization.
This change moves the call to disable ACPI to pmc_soc_init just like
other SoCs to keep the order of events more aligned.
BUG=b:126016602
TEST=Verified that EC panic event gets logged to eventlog correctly.
Change-Id: Ib73883424a8dfd315893ca712ca86c7c08cee551
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Denote appropriate reserved groups as virtual GPIOs in Cannonlake LP/H SoC.
Change-Id: I4da161b91f83749b0ae29b387b5c99c1c3f706d8
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add cometlake specific PCH IDs
Change-Id: I18dda48cee29213aa66c0ccddf3da31f0f489d2f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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* Introduce a measured boot mode into vboot.
* Add hook for stage measurements in prog_loader and cbfs.
* Implement and hook-up CRTM in vboot and check for suspend.
Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add cometlake specific SA IDs
Change-Id: I1fbbab8a7797b36a9eacbd1c6a0644466f2fe6b1
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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Add cometlake specific CPU IDs
Change-Id: I75d5b82524c9df1402abf6659d62dbc716c28c30
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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CB:31547 fixes few whitespace error. Here is few more whitespace clean up.
Change-Id: I69c12a5da4feb48b2bc23874332ab341a559f6e6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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devicetree
Tested on system76 galp3-c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I3aa8990a335e413628c016007ebabf7142aef80d
Reviewed-on: https://review.coreboot.org/c/31535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add a function in gpio ASL library to set pad mode.
BUG=b:123350329
Change-Id: I6c683f27ddffc3132001706d1694c71bb5664577
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I33a50e9fc90162c7cb2aa7fbc3887efe9c6ebcde
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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For CFL and WHL, Microcode is being loaded from FIT. Both
supports the PRMRR/SGX feature. If This is supported the FIT
microcode load will set the msr (0x08b) with the Patch id one
less than the id in the microcode binary. This results in
Microcode getting reloaded again in bootblock and ramstage.
Avoid the microcode reload by checking for PRMRR support.
CFL and WHL CPU die are based on KBL CPU so we need to have
this check, where CNL CPU die is not based on KBL CPU so
skip this check for CNL.
BUG=b:124126405
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: I3311a7413d27044f9c819179e5b0cb9a67b46955
Reviewed-on: https://review.coreboot.org/c/31492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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Change-Id: I91b54b43c8bb5cb17ff86a6d9afa95f265ee49df
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Variants of Hatch need to accommodate single channel DDR. Also,
removing const modifier as we'll need to set these fields
incrementally now. For the single channel configuration, we set
MemorySpdPtr10 to 0. For the dual channel configuration, we set
MemorySpdPtr10 to MemorySpdPtr00.
BUG=b:123062346, b:122959294
BRANCH=None
TEST=Boot into current boards and ensure that we have 2 channels as expected
Change-Id: Ice22b103664187834e255d1359bfd9b51993b5b6
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31262
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch feeds PsysPmax setting to FSP through UPD and adds a
psys_pmax member in chip information so that we can set PsysPmax
through DT. The PsysPmax needs to be set correctly mapping to maximum
system power. Otherwise, system performance would be limited due to
the default PsysPmax setting in FSP is only 21W.
BUG=None
BRANCH=None
TEST=Set psys_pmax to an example value eg 101 in DT && put debug code
in FSP to print the PsysPmax value before sending to Pcode, ensure
the setting is correctly programmed.
Change-Id: Ia88ea17bc661a388c5b9bc3e59abc27c9f262977
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/31505
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds the _DSM method 5 and 6 for entering and exiting S0ix.
The _DSM method gets injected into DSDT table and called from kernel.
LPIT table is hardcoded in this patch but the proper way to implement
is to use inject_dsdt to make the _DSM methods available for soc's to
implement.
Calling the LPIT table from mainboard here so that with the current
implementation the platforms which do not have lpit support throw
compilation error.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db
Reviewed-on: https://review.coreboot.org/c/31101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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New whiskeylake v-0 stepping have changed the graphics device id from
0x3EA0 to 0x3EA1 for celeron, so declare that in common code. Also the
CPUID was changed from 806EB to 806EC, include that as well.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6
Reviewed-on: https://review.coreboot.org/c/31433
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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"mosys memory spd print all" returns incorrect memory ranks info.
This patch and 2 upcomming ones (one in FSP) will address the issue.
BUG=b:122329046
TEST=Boot to OS on Bobba variant of Octopus
BRANCH=octopus
Change-Id: I212215040e4786c258a9c604cc5c2bb62867c842
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Reviewed-on: https://review.coreboot.org/c/31235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Use the common VMX implementation, and set IA32_FEATURE_CONTROL
lock bit per Kconfig *after* SGX is configured (as SGX also sets
bits on the IA32_FEATURE_CONTROL register).
As it is now correctly based on a Kconfig, the `VmxEnable` devicetree
setting vanishes.
Test: build/boot google/[chell,fizz], observe Virtualization enabled
under Windows 10 when VMX enabled and lock bit set.
Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29682
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace all instances, where 0 is used by the macro/define
`ACPI_FADT_LEGACY_FREE`.
Change-Id: I226b334620e0cdafc7639c7a76ea3a523ae53a74
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/31289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1
should be clear to prevent unexpected I2C behaviors.
BUG=b:124269499
TEST=boot on nami and check bit 25 TOL_1V8 is clear
Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/31368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Define VR settings configuration as per board design.
BUG=N/A
TEST=Build and boot up into sarien platform.
Change-Id: Ic9927943b1f8fab687659fd1d6da0e3988a3aba2
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/31405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Set SerialIoDebugUartNumber to CONFIG_UART_FOR_CONSOLE
SerialIoDebugUartNumber UPD use to select UART Number for Debug Purpose
The default value of SerialIoDebugUartNumber is 2 by default it selects UART 2
so it needs to be initialized as per board config
BUG=b:123702398
Change-Id: I91df4bb756e8ea86db112f1cc28687f48b2c0525
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31375
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: Ia210af6ef1a97da67d00036070faa1ceb3ce250b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: I731bc1c9dec6cb5bbb228b7949a73848cb73eee3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30511
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: Idca207b4f05d1844ce6612dbecaad6faeb68725a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: I72effa93e36156ad35b3e45db449d8d0d0cabf06
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Some similar calls to postcar_frame_add_mtrr() were added in the
meantime or were under review while postcar_frame_add_romcache()
was introduced.
Change-Id: Ia8771dc007c02328bd4784e6b50cada94abba198
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I45f2ca809a6acfcb80a742d29c045d04888e4d7f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This board is EOL and has FSP2.0 support, so drop the older
version.
Change-Id: If5297e87c7a7422e1a129a2d8687fc86a5015a77
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The CAR setup is almost identical to the cpu/intel/non-evict
CAR setup, with the only difference that L2 cache needs to be
separately enabled. Currently this assumes that it is possible
to use a static Kconfig option to cover all CPU's requiring this.
Change-Id: Iae9b584bc0d32a56be2e6e2b2e893897eb448aa5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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It is not mentioned in the FSP spec and doesn't seem to be implemented
for any other FSP than the Broadwell-DE one.
Change-Id: I87c758204f1aabf13f47de19fd87c6e1ed67258e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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FSP-S is currently configuring GPIOs that it should not. This results
in issues where mainboard devices don't behave as expected e.g. host
unable to receive TPM interrupts as the pad for the interrupt is
re-configured as something else.
Until FSP-S is fixed, this change adds a workaround by reconfiguring
GPIOs after FSP-S is run.
All mainboards need to call cnl_configure_pads instead of
gpio_configure_pads so that SoC code can maintain a reference to the
GPIO table and use that to re-configure GPIOs after FSP-S is run.
BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.
Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This patch performs below tasks
1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig.
2. Allow required SoC to select this kconfig to extend CANNONLAKE
SoC support and add incremental changes.
3. Select correct SoC support for hatch, sarien, cflrvps
and whlrvp.
* Hatch is WHL SoC based board
* Sarien is WHL SoC based board
* CFLRVP U/8/11 are CFL SoC based board
* WHLRVP is based on WHL SoC
4. Add correct FSP blobs path for WHL SoC based designs.
Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The allocation is not required before romstage,
so it can be just another CAR_GLOBAL instead of
polluting the linker script.
Change-Id: I0738a655f6cc924fbed92ea630f85406e3f58c0b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31191
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The default state of the HOSTSW_OWN register in the PCH is zero, which
configures GPIO pins for ACPI ownership. The board variabt GPIO tables
can request specific pins to be configured for GPIO driver ownership.
This change sets the HOSTSW_OWN ownership bit when requested and
explicitly clears the ownership bit if not requested.
BUG=b:120884290
BRANCH=none
TEST=Build coreboot on sarien. Verified UEFI to coreboot transition
boots successfully.
Change-Id: Ia82539dbbbc7cf5dfb9223902d563cafec1a73e5
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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By APL BIOS Spec, we must not do this on warm boots.
The TODO comment seems stale and copied over. So the actual
requirements for SGX are unknown and we add a guard for that
case.
Change-Id: I09b4a2fe22267d7318951aac20a3ea566403492e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31200
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Idfe93e454cc0ce0d8e06e23beaddee2f11f5eedd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31199
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The FSP has a parameter to enable or disable the VTD feature
(Intel's Virtualization Technology for Directed I/O). In current header
files for FSP-S (Apollo Lake and Gemini Lake) this parameter is set to
disabled per default. Therefore, if the FSP was not modified via BCT,
this feature is most likely disabled on all mainboards.
Add a chip parameter so that VTD can be enabled on mainboard level in
devicetree and therefore this feature can be activated if needed.
Change-Id: Ic0bfcf1719e1ccc678a932bf3d38c6dbce3556bc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31194
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GLK has a dedicated USB2 port that is used specifically for CNVi
BT. This requires that the ACPI tables define an additional USB 2 port
which results in _ADR for USB 3 ports being different for GLK than
APL.
This change splits the ports in xhci.asl into APL and GLK specific
ports.asl and selects the appropriate file based on
CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK
if ACPI name is requested for that port.
BUG=b:123670712
BRANCH=octopus
TEST=Verified that generated DSDT for octopus (GLK) includes HS09 and
for reef (APL) does not include HS09 definition.
Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31172
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes duplicate selects of same SOC_INTEL_CANNONLAKE_MEMCFG_INIT
from various CFL/WHL SoC based boards to include cnl_memcfg_init.c file
and include the cnl_memcfg_init.c file by default in CNL SoC Makefile.inc.
Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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TEST=Dump SSDT entries to verify _CST between S0ix enable and disable.
>> iasl -d SSDT # to generate SSDT.dsl
Change-Id: I82d8bf9d143263a80a544f6e11186a3bc9c41052
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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TEST=Dump SSDT entries to verify _CST between S0ix enable and disable.
Change-Id: I25e8f8c13bb91c2645e8e9fdfdf9ba4d7022f1b1
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/31154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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XHCI is currently named as XHC1. This leads to namespace lookup error in
the kernel when children USB ACPI devices are added under the scope of
XHCI device.
BUG=b:123296264
BRANCH=octopus
TEST=Boot to ChromeOS; Ensure that the below error is resolved in the
kernel dmesg
[ 0.001000] ACPI Error: [\_SB_.PCI0.XHCI.RHUB.HS03] Namespace lookup
failure, AE_NOT_FOUND (20170728/dswload-210)
Change-Id: Ia4921547fee6fb51333319b9e881501a7e75ebce
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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FSP 2.0.9 provides UPD interface to adjust integrated filter
value, usb3 LDO and pmic vdd2 voltage. Change coreboot upd
structure to sync with fsp 2.0.9 release.
BUG=b:123398358
CQ-DEPEND=CL:*817128
TEST=Verified yorp boots to kernel.
Change-Id: I3d17dfbe58bdc5222378459723da8e9ac0573510
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/31131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Now we have usb2eye configuration register in FSPUPD, so we need
to add an interface to override usb2eye setting.
BRANCH=octopus
BUG=NONE
TEST=Verified usb2eye custom setting works
Change-Id: I5c500964658072eaaf59364242aa928df25d99d1
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/31060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch removes stale ASL entries added in past due to chromeos
requirement.
BUG=115755982
TEST=Build and boot ICL platform without any problem.
Change-Id: I18b57822ce3198fb96aae977f0b552ff2d4a14ee
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31117
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The SoC has an Image Processing Unit which is located on PCI 00:03.0.
There is a corresponding parameter for FSP which handles
enabling/disabling of this functionality (IpuEn). Add this device to
the disable_dev() function of the chip so that if this device is
disabled in devicetree the matching FSP parameter will be disabled as
well. As this parameter is only valid for Apollo Lake, use the config
switch CONFIG_SOC_INTEL_GLK to disable this code if compiled not for
Apollo Lake. As this issue is regarding a missing structure member,
this check needs to be done on preprocessor level and not at runtime.
Test=Verified this function on mc_apl2.
Change-Id: I75444bf483de32ba641f76ca50e9744fdce2e726
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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If the VTd feature is enabled, there will be up to two fixed resources
which are set up by the FSP. Add these resources to the list of system
resources so that the PCI enumerator will know them.
Change-Id: If96fc1c93746e3c7f510e5b3095ea3090e1b8807
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30991
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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