coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2017-03-15	intel/skylake: Support for setting AC/DC loadline	Duncan Laurie
	Add options to set the AC and DC loadline values for each supported VR type so these can be tuned on a per-board basis in devicetree.cb. BUG=b:36228330 BRANCH=none TEST=Build and boot on Eve and check debug FSP output to ensure that it is applying the provided loadline values Change-Id: I2a5533d2c9fd86351c86584e3738e80ac4c1f915 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18819 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-15	intel/skylake: Fix bug in VR configuration with FSP 2.0	Duncan Laurie
	With the move to FSP 2.0 the number of VR types supported was reduced to 4, and the VR_RING type is no longer present. This means all existing boards using FSP 2.0 are incorrectly passing VR configuration into FSP as the values corresponding to "GT Sliced" and "GT Unsliced" have changed. Fix this by updating the skylake SOC VR handling to account for changes in the FSP configuration and no longer provide VR_RING type when using FSP 2.0. BUG=b:36228330 BRANCH=none TEST=manual: build and boot on Eve Change-Id: I59eea9fba006a4c235d7b42d07fdc6e4f44f7351 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-03-15	intel/skylake: nhlt: Add support for rt5514 NHLT blob	Duncan Laurie
	Add support for describing the NHLT blob for the rt5514 DSP. Currently this only supports 4 channel capture. BUG=b:35585307 BRANCH=none TEST=build and boot on Eve P1 Change-Id: Ib59b56222f9aa65370fdcf9ddf25145c571b1b2e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18816 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-15	soc/intel/quark: Read the rmu.bin file from read-only region	Lee Leahy
	Always read the rmu.bin file from the read-only section of the SPI flash. Without this change vboot attempts to read this file from the A or B section of the flash. TEST=Build and run on Galileo Gen2 Change-Id: Ied8eaa2cd37645bf401aa957936943946bfd6182 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18803 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-15	soc/intel/common: Wrap lines at 80 columns	Lee Leahy
	Fix the following error detected by checkpatch.pl: ERROR: code indent should use tabs where possible TEST=Build and run on Galileo Gen2 Change-Id: Ief4b96073b3df30e45bf5d802ca3b190e7f431a7 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18753 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-15	soc/intel/apollolake: Cache FPF status value in flash	Andrey Petrov
	Since asking CSE to read FPF status turned out to be slow in some cases, cache and save returned value on first boot only. Value is read from flash on consequent boots. BUG=b:35586975 BRANCH=reef TEST=boot twice, make sure cached FPF status is loaded from flash the second time. Change-Id: I6e56a35407c9097616ccb05a557fded7b639c88a Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18774 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14	soc/intel/quark: Pass S3 wake status to fsp_silicon_init	Lee Leahy
	Fix build error with FSP 1.1. Pass the S3 wake status to fsp_silicon_init. TEST=Build and run on Galileo Gen2 Change-Id: I78150f737321db5b1b4d63b411fa6432ac30d080 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18805 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14	soc/intel/quark: Add ESRAM display to FSP 1.1	Lee Leahy
	Add ESRAM display to FSP 1.1 TEST=Build and run on Galileo Gen2 Change-Id: Ia47b0bdba65606a7f0695332d298fc1e910b0e2f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18804 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14	soc/intel/quark: Return NULL for top_of_memory	Lee Leahy
	Return NULL for top_of_memory when the register has not been set. TEST=Build and run on Galileo Gen2 Change-Id: If79cac68c2a64aa9bf3be72d3cfc4c73fceef12b Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18802 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14	soc/intel/skylake: Extract DIMM Information from FSP MEM INFO HOB	Barnali Sarkar
	Extract SMBIOS memory information from FSP SMBIOS_MEM_INFO_HOB and save it in CBMEM. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in SMBIOS Table from Kernel command "dmidecode". Change-Id: I593d4ccb0d4866e99913a73c49b2f000b51827d1 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18275 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-13	soc/intel/quark: Add the verstage files	Lee Leahy
	Add the files to support verstage for vboot. TEST=Build and run on Galileo Gen2 Change-Id: Icf87075012c08cf581c17d579e0763888c707265 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18040 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13	soc/intel/apollolake: Wrap lines at 80 columns	Lee Leahy
	Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build for reef Change-Id: I4fbe95037ca4b52e64ba37e5c739af4a03f64feb Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18728 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13	soc/intel/apollolake: Fix issues detected by checkpatch	Lee Leahy
	Fix the following errors and warnings detected by checkpatch.pl: ERROR: switch and case should be at the same indent ERROR: do not use assignment in if condition WARNING: Statements terminations use 1 semicolon WARNING: unnecessary whitespace before a quoted newline WARNING: else is not generally useful after a break or return TEST=Build for reef Change-Id: I5486936dbf19b066c76179d929660affa1da5f16 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18727 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13	soc/intel/apollolake: Fix position of storage class	Lee Leahy
	Fix the following error and warning detected by checkpatch.pl: ERROR: inline keyword should sit between storage class and type WARNING: storage class should be at the beginning of the declaration TEST=Build for reef Change-Id: I2ed418cc3b4a989eb1101013944169429bf147c2 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18726 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13	soc/intel/apollolake: Fix parenthesis issues	Lee Leahy
	Fix the following errors and warning detected by checkpatch.pl: ERROR: space required before the open parenthesis '(' ERROR: space prohibited before that close parenthesis ')' ERROR: return is not a function, parentheses are not required WARNING: space prohibited between function name and open parenthesis '(' TEST=Build for reef Change-Id: I31f854adf3269ba6f77c4044fb3748bb1957841c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18725 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13	soc/intel/apollolake: Fix unsigned warnings	Lee Leahy
	Fix the following warning detected by checkpatch.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build for reef Change-Id: Ifc45ce90d466d087cd20af72ddfc8486d2f1492c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18724 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13	soc/intel/apollolake: Remove unnecessary braces	Lee Leahy
	Fix the following warnings detected by checkpatch.pl: WARNING: braces {} are not necessary for any arm of this statement WARNING: braces {} are not necessary for single statement blocks TEST=Build for reef Change-Id: Ifab09c023faa7da215945f1aedd391f4b2a1a04c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18723 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13	soc/intel/apollolake: Indent code using tabs	Lee Leahy
	Fix the following error and warnings detected by checkpatch.pl: ERROR: code indent should use tabs where possible WARNING: please, no spaces at the start of a line WARNING: please, no space before tabs TEST=Build for reef Change-Id: Id7a758463b95274c5e8bbdd67da0955f1ae78aac Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18721 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13	soc/intel/apollolake: Fix spacing around operators and commas	Lee Leahy
	Fix the following errors detected by checkpatch.pl: ERROR: spaces required around that '==' (ctx:VxO) ERROR: space required before that '-' (ctx:OxV) ERROR: spaces required around that '=' (ctx:VxW) ERROR: spaces required around that '=' (ctx:WxV) ERROR: spaces required around that '=' (ctx:VxV) ERROR: need consistent spacing around '+' (ctx:VxW) ERROR: space prohibited before that '++' (ctx:WxB) ERROR: space prohibited before that ',' (ctx:WxW) ERROR: space required after that ',' (ctx:VxV) TEST=Build for reef Change-Id: I37265a69fcb14fbf7c182ef29d823f70a5748ad8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18720 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13	soc/intel/apollolake: Fix space between type, * and variable name	Lee Leahy
	Fix the following errors detected by checkpatch.pl: ERROR: "foo * bar" should be "foo bar" ERROR: "(foo)" should be "(foo *)" TEST=Build for reef Change-Id: I4a762d8fa762057a06e601dfed10538adc5d8bc8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18719 Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13	soc/intel/apollolake: Move brace to beginning of line	Lee Leahy
	Fix the following error detected by checkpatch.pl: ERROR: open brace '{' following function declarations go on the next line TEST=Build for reef Change-Id: Icb92dc49c6e7b8dfea60bc0395f3db7316c4e34c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18722 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-13	soc/intel/common: Remove parenthesis	Lee Leahy
	Fix the following error detected by checkpatch.pl: ERROR: return is not a function, parentheses are not required TEST=Build and run on Galileo Gen2 Change-Id: Idf7723d4fd48124a26bbb626afc310820f859f66 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18757 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-13	soc/intel/common: Fix unsigned warnings	Lee Leahy
	Fix the following warning detected by checkpatach.pl: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' TEST=Build and run on Galileo Gen2 Change-Id: Ic266c077eb115e0c7d934c15bcc4cc9b9e530a39 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18756 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-13	soc/intel/common: Fix spacing issues	Lee Leahy
	Fix the following errors detected by checkpatch.pl: ERROR: spaces required around that '=' (ctx:VxV) ERROR: spaces required around that ':' (ctx:VxW) ERROR: space required after that ',' (ctx:VxV) ERROR: space required before the open parenthesis '(' ERROR: switch and case should be at the same indent ERROR: "foo bar" should be "foo bar" TEST=Build and run on Galileo Gen2 Change-Id: I52ba2a3c1e0fffad7145eecd878aba8dc450ac0b Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18755 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-13	soc/intel/common: Indent code with tabs	Lee Leahy
	Fix the following error detected by checkpatch.pl: ERROR: code indent should use tabs where possible TEST=Build and run on Galileo Gen2 Change-Id: I61c4f01216cb6c788cf6da988c414bbb9648d502 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18754 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-10	soc/intel/common: Pass the minimum possible string length for strncpy	Barnali Sarkar
	In strncpy() function of dimm_info_fill(), the minimum possible size of Module Part Number of DIMM is passed as argument. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in SMBIOS Table from Kernel command "dmidecode". Change-Id: Icc7667149eae9705b91e271628af1b443eb8556e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18617 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10	soc/intel/broadwell: Rework IGD's CDClk selection	Nico Huber
	CDClk selection was wrong in some corner cases (e.g. ULX SKUs) and, for Broadwell, never took the devicetree config into account. Rewrite the selection with the following in mind: o cpu_is_ult() might return `true` for ULX SKUs, too, o ULX and Broadwell-ULT SKUs can be `overclocked` with additional cooling, so leave that as devicetree option. For Haswell, the following frequency selections are valid: o ULX: 337.5MHz by default, 450MHz optional o ULT: 450MHz only (maybe 337.5MHz too, documentation varies, it wasn't selectable before either) o others: 540MHz by default, 450MHz optional For Broadwell: o ULX: 450MHz by default, 337.5MHz / 540MHz optional o ULT: 540MHz by default, 337.5MHz / 450MHz / 675MHz optional o others: 667MHz by default, 337.5MHz / 450MHz / 540MHz optional Side effects: A too high setting in the devicetree results in the highest possible frequency now, Haswell non-ULT/ULX defaults to 540MHz instead of 450MHz. Change-Id: Iec12752f2a47bf4a5ae6077c75790eae9378c1b2 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17768 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-10	soc/intel/skylake:Add _DSM method to reduce D3 cold delay for eMMC controller	sowmyav
	eMMC Controller is taking over 100ms to resume during runtime which results in I/O latency issues on the Skylake systems like Cave and Caroline. This patch adds _DSM method for eMMC comtroller for specifying the device readiness durations. Function index 9 returns package of five integers to set D3 cold delay to zero and ACPI constant Ones for the elements where overriding the default values is not desired. BUG=b:35774937 BRANCH=none TEST=update caroline coreboot and test i/o latency is under 100ms Change-Id: Iacc8aa8560897da8770fe559ca8cd17aaf6ebeba Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/18532 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-03-10	soc/intel/apollolake: Add PM methods to power gate SD card	Venkateswarlu Vinjamuri
	This implements dynamic generation of sdcard GpioInt in SSDT. GpioInt in SSDT generation is based on the card detect GPIO if it is provided by the mainboard in devicetree. This implements GNVS variable to store the address of sdcard cd pin. GNVS used to store rxstate of the sdcard cd pin to get card presence. Add _PS0/_PS3 methods to power gate the sd card controller in S0ix and runtime PM. CQ-DEPEND=448173 BUG=chrome-os-partner:63070 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should enter S0ix and resume with no issue. Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18496 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2017-03-09	soc/intel/skylake: Add GPIO macros for IOxAPIC and SCI	Li Cheng Sooi
	Add two GPIO macros: 1. PAD_CFG_GPI_APIC_EDGE allows a pin to be route to the APIC with input assuming the events are edge triggered. 2. PAD_CFG_GPI_ACPI_SCI_LEVEL to route the general purpose input to SCI assuming the events are level triggered. Change-Id: I944a9abac66b7780b2336148ae8c7fa3a8410f3f Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com> Reviewed-on: https://review.coreboot.org/18533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-09	soc/intel/skylake: Add SKL SOC PCH H GPIO support	Li Cheng Sooi
	Add SKL/KBL PCH-H GPIO settings referring from SKL PCH-H specifications to support sklrvp11. Split the gpio_defs.h into headers gpio_pch_h_defs.h and gpio_soc_defs.h for PCH-H specific and SOC specific GPIO defs respectively. Change-Id: I5eaf8d809a1244a56038cbfc29502910eb90f9f2 Signed-off-by: Li Cheng Sooi <li.cheng.sooi@intel.com> Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com> Reviewed-on: https://review.coreboot.org/18027 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-09	soc/intel/apollolake: Add check if FPFs are blown	Andrey Petrov
	Apollolake platform comes with FPF (field-programmable-fuses). FPF can be blown only once, typically at the end of the manufacturing process. This patch adds code that sends a request to CSE to figure out if FPFs have already been blown. Change-Id: I9e768a8b95a3cb48adf66e1f17803c720908802d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18604 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-09	soc/intel/apollolake: Start using common CSE driver	Andrey Petrov
	Change-Id: If866453f06220e0edcaa77af5f54b397ead3ac14 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18603 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-09	soc/intel/common/block: Add HECI driver	Andrey Petrov
	Add common driver that can send/receive HECI messages. This driver is inspired by Linux kernel mei driver and somewhat based on Skylake's. Currently it has been only tested on Apollolake. BUG=b:35586975 BRANCH=reef TEST=tested on Apollolake to send single messages and receive both fragmented and non-fragmented versions. Change-Id: Ie3772700270f4f333292b80d59f79555851780f7 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18547 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-09	soc/intel/apollolake: Prepare to use common HECI driver	Andrey Petrov
	Change-Id: Ib284493d886b223e8c85607de5fdb56b698fe5fa Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-08	intel/skylake: Filter suspend well power failure event for Deep Sx	Duncan Laurie
	If Deep Sx is enabled the event log will get entries added on every power sequence transition indicating that the suspend well has failed. When a board is using Deep Sx by design this is intended behavior and just fills the logs with extraneous events. To make this work the device init state has to be executed first so it actually enables the Deep Sx policies in the SOC since this code does not have any hooks back into the devicetree to read the intended setting from there. BUG=b:36042662 BRANCH=none TEST=Perform suspend/resume on Eve device with Deep S3 enabled, and then check the event log to be sure that it does not contain the "SUS Power Fail" event. Change-Id: I3c8242baa63685232025e1dfef5595ec0ec6d14a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18664 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-08	intel/skylake: Add function to read state of Deep S5	Duncan Laurie
	Add a function to read the current state of Deep S5 configuration and indicate if it is enabled (for AC and/or DC) or disabled. This is similar to the existing function that checks Deep S3 enable state. BUG=b:36042662 BRANCH=none TEST=tested with subsequent commits to check Deep S5 state at boot and filter event log messages if it is enabled. Change-Id: I4b60fb99a99952cb3ca6be29f257bb5894ff5a52 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18663 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-08	intel/skylake: Add devicetree settings for acoustic noise mitigation	Duncan Laurie
	Add options to the skylake chip config that will allow tuning the various settings that can affect acoustics with the CPU and its VRs. These settings are applied inside FSP, and they can adjust the slew slew rate when changing voltages or disable fast C-state ramping on the various CPU VR rails. BUG=b:35581264 BRANCH=none TEST=these are currently unused, but I verified that enabling the options can affect the acoustics of a system at runtime. Change-Id: I6a8ec0b8d3bd38b330cb4836bfa5bbbfc87dc3fb Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18662 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-07	soc/intel/quark: Fix errors detected by checkpatch	Lee Leahy
	Fix the errors detected by checkpatch and update the copyright dates. TEST=Build and run on Galileo Gen2 Change-Id: Idad062eaeca20519394c2cd24d803c546d8e0ae0 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18591 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07	soc/intel/quark: Fix I2C driver	Lee Leahy
	Fix the following issues: * A raw read is described by a single read segment, don't assert. * Support reads longer than the FIFO size. * Support writes longer than the FIFO size. * Use the 400 KHz clock by default. * Remove the error displays since vboot device polling generates errors. TEST=Build and run on Galileo Gen2 Change-Id: I421ebb23989aa283b5182dcae4f8099c9ec16eee Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18029 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-06	soc/intel/skylake: Clean up CPU code	Subrata Banik
	Use header (soc/intel/common/block/include/intelblocks/msr.h) for MSR macros Change-Id: I401b92cda54b6140f2fe23a6447dad89879a5ef0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18554 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06	soc/intel/skylake: Use intel/common/xhci driver	Subrata Banik
	Change-Id: I7bd83d293fcc1848f6f64526d8f38d010c1f69a3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18223 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06	intelblocks/msr: Move intel x86 MSR definition into common location	Subrata Banik
	Move all common MSRs as per IA SDM into a common location to avoid duplication. Change-Id: I06d609e722f4285c39ae4fd4ca6e1c562dd6f901 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18509 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06	soc/intel/common/block: Add Intel XHCI driver support	Subrata Banik
	Create sample model for common Intel XHCI driver. Change-Id: I81f57bc713900c96d998bae924fc4d38a9024fe3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18221 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06	soc/intel/common: Make infrastructure ready for Intel common code	Subrata Banik
	Select all Kconfig belongs into Intel SoC Family block/ips common code model and include required header.h file. Change-Id: Idbce59a57533dbeb9ccfadca966c3d7560537fa0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18377 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06	soc/intel/skylake: Clean up XHCI code	Subrata Banik
	Don't need "skylake/include/soc/xhci.h", hence removed. Change-Id: I35df2003f311b557b622ce1d7a1c2e832693c2fc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18508 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06	soc/intel/apollolake: Move XDCI in its own file	Andrey Petrov
	Split out dual-port switching functionality into dedicated xdci.c. Change-Id: Ia58fc3fb6d017dd0c19cc450d1caba307fc89a7b Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18226 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-04	soc/intel/skylake: indicate voltage margining enabled/disabled	Rizwan Qureshi
	Support for voltage margining is dependent on the platform. Enabling voltage margining puts additional constraints for the SLP_S0# to be asserted and hence moving to S0ix state. If the platform PMIC/VR supports PCH voltage reduction, voltage marigining can be enabled. Use the UPD provided by FSP to enable/disable voltage margining. Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18469 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-02	intel/broadwell: Use the correct SATA port config for setting IOBP register	Youness Alaoui
	Fix a typo that was introduce in commit 696ebc2d (Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3.) [1]. Setting one of the SATA port 3 IOBP setting was using the value from the port 2 register. On the purism/librem13 (on which SATA port 3 is tested), this change doesn't seem to affect anything, as that typo wasn't exhibiting any visible problems anyways. [1] https://review.coreboot.org/18408 Change-Id: I3948def5c0588791009c4b24cbc061552d9d1d48 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/18514 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-01	soc/intel/common: Save Memory DIMM Information in SMBIOS table	Barnali Sarkar
	Save SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM. Add function dimm_info_fill() which populates SMBIOS memory information from FSP MEM_INFO_DATA_HOB data. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in SMBIOS table from Kernel command "dmidecode". Change-Id: I0fd7c9887076d3fdd320fcbdcc873cb1965b950c Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18418 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-23	soc/intel/skylake: Enable Systemagent IMGU	Rizwan Qureshi
	Camera and Imaging device should be enabled for camera usecase, FSP provides a UPD to enable/disable the SA IMGU (Imaging Unit) expose the same as a config option in devicetree.cb Also remove a redundant assignment for PchCio2Enable. BUG=None BRANCH=None TEST=lspci should list 00:05:00 Change-Id: I4cf7daf41bfaf4dcba414921cac2e7e12bf89f37 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18365 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-22	Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3.	Youness Alaoui
	The Broadwell SATA controller supports IOBP registers on ports 0 and 1 but Browell supports up to 4 ports, so we need to support setting IOBP for ports 2 and 3 as well. The magic numbers (IOBP SECRT88 and DTLE) for ports 2 and 3 were only guessed by looking at ports 0 and 1 and extrapolating from there. Port 3 has been tested (DTLE setting on Librem 13) and confirmed to work so we can assume that port 2 and 3 magic numbers are valid, but having someone confirm them (through non-public documents?) would be great. Change-Id: I59911cfa677749ceea9a544a99b444722392e72d Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/18408 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-22	acpi: Add ACPI_ prefix to IRQ enum and struct names	Furquan Shaikh
	This is done to avoid any conflicts with same IRQ enums defined by other drivers. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18444 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-22	soc/intel/skylake: Fix broken suspend-resume	Furquan Shaikh
	With recent change (a4b11e5c90: soc/intel/skylake: Perform CPU MP Init before FSP-S Init) to perform CPU MP init before FSP-S init, suspend resume is currently broken for all skylake/kabylake boards. All the skylake/kabylake boards store external stage cache in TSEG, which is relocated post MP-init. Thus, if FSP loading and initialization is done after MP-init, then ramstage is not able to: 1. Save FSP component in external stage cache during normal boot, and 2. Load FSP component from external stage cache during resume In order to fix this, ensure that FSP loading happens separately from FSP initialization. Add fsp_load callback for pre_mp_init which ensures that the required FSP component is loaded/saved from/to external stage cache. BUG=chrome-os-partner:63114 BRANCH=None TEST=Verified that 100 cycles of suspend/resume worked fine on poppy. Change-Id: I5b4deaf936a05b9bccf2f30b949674e2ba993488 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18414 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-20	soc/intel/skylake: Expand USB OC pins definition to support PCH-H	Teo Boon Tiong
	Currently the USB OC pins definition only being defined up to OC3. For PCH-H, OC4 and OC5 are needed, so add both into OC pin enum. Changes is being verified and booted to Yocto with Saddle Brook. Change-Id: Idaed6fa7dcddb9c688966e8bc59f656aec2b26eb Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/18364 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-20	lynxpoint/broadwell: fix PCH power optimizer	Matt DeVillier
	Setting both bits 27 and 7 of PCH register PMSYNC_CFG (PMSYNC Configuration; offset 0x33c8) causes pre-OS display init to fail on HSW-U/Lynxpoint and BDW-U ChromeOS devices when the VBIOS/GOP driver is run after the register is set. A re-examination of Intel's reference code reveals that bit 7 should be set for the LP PCH, and bit 27 for non-LP, but not both simultaneously. The previous workaround was to disable the entire power optimizer section via a Kconfig option, which isn't ideal. Test: unset bit 27 of PMSYNC_CFG and boot google/lulu, observe functional pre-OS video output Change-Id: I446e169d23dd446710a1648f0a9b9599568b80aa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18385 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20	Revert "intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano"	Matt DeVillier
	We've been able to narrow down the problem to a single register/ single bit, so revert this commit and address the problem in a follow-on commit. This reverts commit 0f2025da0fd4dce6b951b4c4b97c9370ca7d66db. Change-Id: I780f9ea2976dd223aaa3e060aef6e1af8012c346 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18384 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-19	soc/intel/skylake: Disable s0ix if not enabled in devicetree	Duncan Laurie
	There is an enable_s0ix config option in the devicetree that should be used to disable it when not set: - do not export C8/C9/C10 C-states in _CST - do not enable SLP_S0 in FSP BUG=chrome-os-partner:58666 TEST=test on eve board to ensure that OS only sees 3 ACPI C-states instead of 6 and that it no longer attempts to enter C10 Change-Id: I90e4dc776d1d17d0b700cda63c8476786cd2e4ff Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18394 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-18	soc/intel/skylake: add PrmrrSize to chip config	Robbie Zhang
	Prmrr configuration is supported by Kabylake FSP-M with UPD provided. It is required as one of the SGX initialization steps in BIOS. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Tested on Eve, verified uncore PRMRR MSRs get programmed to set size and boot. Change-Id: I2b3dc7c92487505165ee429bd1a37bd60ceac8f3 Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/18361 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-17	soc/intel/skylake: Add Maxim 98927 and Realtek 5663 NHLT blob support	Rizwan Qureshi
	Add APIs and required parameters for creating Maxim 98927 and Realtek 5336 SSP endpoints in NHLT table. BUG=chrome-os-partner:62051 BRANCH=None TEST=check that NHLT table created is created properly Change-Id: Ica302aab05c5364faf4923dc5327be8e8eaae8b4 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: M Naveen <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/18213 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-17	soc/intel/skylake: Add config option for Kabylake	Rizwan Qureshi
	Currently there is no distinction between mainboards using Skylake or Kabylake SoC, Add a config option for Kabylake SoC to allow mainboards to explicitly select if they are using it. Change-Id: Ie7960bd81f88a223894afe3115ddc0bc637e4be4 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18312 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-17	intel/skylake: add function is_secondary_thread()	Robbie Zhang
	There are MSRs that are programmable per-core not per-thread, so add a function to check whether current executing CPU is a primary core or a "hyperthreaded"/secondary core. For instance when trying to program Core PRMRR MSRs(per-core) with mp_init, cpu exception is thrown from the secondary thread. This function was used to avoid that. Potentially this function can be put to common code or arch/x86 or cpu/x86. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Tested on Eve, verified core PRMRR MSRs get programmed only on primary thread avoiding exeception. Change-Id: Ic9648351fadf912164a39206788859baf3e5c173 Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/18366 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-16	soc/intel/skylake: Add support for SPI device	Furquan Shaikh
	Add a new PCI driver for SPI devices with supported PCI ids. Also, provide a translation table to convert struct device structure into SPI bus number. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: If860eb819f2ce5ae5443f808b356af57f86c52be Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18341 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-16	soc/intel/skylake: Add GSPI controller get_config support	Furquan Shaikh
	Provide implementation of get_config routine for GSPI controller on skylake platforms. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully. Change-Id: I5170076c15d72a7f29acd0989acef5b9149e2ba0 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18338 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-16	soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL ↵	Sooi, Li Cheng
	HALO SOC Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC Change-Id: I6a44d55d1588d2620bd1179ea7dc327922f49fd7 Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com> Reviewed-on: https://review.coreboot.org/18028 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-14	soc/intel/skylake: Perform CPU MP Init before FSP-S Init	Subrata Banik
	As per BWG, CPU MP Init (loading ucode) should be done prior to BIOS_RESET_CPL. Hence, pull MP Init to BS_DEV_INIT_CHIPS Entry (before FSP-S call). BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Boot to OS with all threads enabled. Change-Id: Ia6f83d466fb27e1290da84abe7832dc814b5273a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18287 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-14	Revert: soc/intel/skylake: Set FSP-S UPD PchHdaIDispCodecDisconnect to 1	Duncan Laurie
	This reverts commit 32997fb0bcb9f4183789331a91fd83138776b96f. This change is breaking I2S audio on Kabylake platforms so revert the change to fix audio. BUG=chrome-os-partner:61548,chrome-os-partner:61009 TEST=manual testing on Eve P1 system Change-Id: I3212c8be83078ed57e38501386605e67b87d5bd0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18360 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-14	google/rambi: add explicit pull-down for ram-id	Matt DeVillier
	Some variants need the internal pull resistor on GPIO_SSUS_40 set explicitly to pull down rather than disabling the pull, in order for the ram-id to be read correctly via GPIO. Correct this by adding a function to enable and set the internal pull and define its use as needed in the board's variant.h. Chromium source: branch: firmware-gnawty-5216.239.B /src/soc/intel/baytrail/baytrail/gpio.h#418 /src/mainboard/google/gnawty/romstage.c#60 Test: boot 4GB Candy board and observe correct RAM id, amount detected Change-Id: I8823c27385f4422184b5afa57f6048f7ff2a25ab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18309 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-14	intel/skylake: Disable FADT.8042 if NO_FADT_8042 is set	Jenny TC
	Kernel relies on FADT 8042 flag to enable/disable 8042 interface. If FADT reports 8042 capability and 8042 (/PS2) capability is actually disabled by coreboot, kernel would assume the presence of 8042 based on the FADT flag. This results in undesired system power off when kernel tries to access the 8042 memory region. To address this, CONFIG_NO_FADT_8042 was added to selectively disable 8042 on FADT. BUG=chrome-os-partner:61858 TEST=Boot OS and verify FADT 8042 flag Change-Id: Ic80b3835cb5cccdde1203e24a58e28746b0196fc Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/18307 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-08	soc/intel/apollolake: dump CSE status	Aaron Durbin
	Dump the CSE status registers for potential debugging purposes. Explicitly call out manufacturing mode of the part since it's important shipping devices ensure manufacturing mode is locked down. Intel is planning on writing a common driver so a complete status -> string dumps was not done because (surprise surprise) not all the fields are equal with previous implementations. BUG=chrome-os-partner:62177 BRANCH=reef TEST=Booted and noted dump of CSE status registers. Change-Id: I71d15722bb193877f1569c1d3e7f441302f5bd14 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18303 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-01-22	soc/intel/skylake: Include I2C code in romstage	Duncan Laurie
	The lpss_i2c driver is enabled in romstage, so the SOC needs to export the pre-ram compatible I2C controller info, which for skylake is in the bootblock/i2c.c file. This was not causing a compiler error in normal use, but when adding I2C debug code in romstage it failed to compile. With this added, I can now do I2C transactions in romstage. Change-Id: I0778b0497d0b6936df47c29b2ce942c8d90cf39b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18198 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-21	soc/intel/apollolake: correct GPIO 13 IRQ number	Aaron Durbin
	The define for GPIO_13_IRQ had the wrong IRQ number. It should be 0x70 instead of 0x6f. BUG=chrome-os-partner:62085 BRANCH=reef TEST=touch controller doesn't indicate continuous interrupts Change-Id: I3a0726db59fc1eb7736d348aecbf1082719f15b2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18190 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-20	soc/intel/skylake: Set FSP-S UPD PchHdaIDispCodecDisconnect to 1	Barnali Sarkar
	As per Audio PCH team recommendation the iDisplay Audio/SDIN2 should be disabled to bypass InitializeDisplayAudio() function call. Display Audio Codec is HDA-Link Codec, which is not supported in I2S mode BUG=chrome-os-partner:61548 BRANCH=none TEST=Tested to verify that InitializeDisplayAudio() does not get called. Change-Id: Ie0771a8653821e737d10e876313917b4b7c64499 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/18091 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-01-19	driver/intel/fsp1_1: Fix boot failure for non-verstage case	Teo Boon Tiong
	Currently car_stage_entry is defined only in romstage_after_verstage and as a result when SEPARATE_VERSTAGE is not selected, there is no entry point into romstage and romstage will not be started at all. The solution is move out romstage_after_verstage.S from fsp1.1 driver to skylake/romstage. And add CONFIG_PLATFORM_USES_FSP1_1 to fix the build and boot issue with this change. Besides that, rename the romstage_after_verstage to romstage_c_entry in more appropriate naming convention after this fix. Tested on SkyLake Saddle Brook (FSP 1.1) and KabyLake Rvp11 (FSP 2.0), romstage can be started successfully. Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/17976 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-19	soc/intel/skylake: Add SATA interrupt for APIC mode	Sooi, Li Cheng
	Add SATA interrupt for APIC mode Change-Id: I9e0682e235715399da2c585174925c89b9116ab3 Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com> Reviewed-on: https://review.coreboot.org/18130 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-16	intel: Fix copy/paste error in license text	Marshall Dawson
	Change all instances of "wacbmem_entryanty" to "warranty". Change-Id: I113333a85d40a820bd8745efe917181ded2b98bf Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18136 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-14	soc/intel/apollolake: Allow USB2 eye pattern configuration in devicetree	Kane Chen
	This code allows people to override the usb2 eye pattern UPD settings for boards. BUG=chrome-os-partner:61031 BRANCH=None TEST=Usb2 function ok and make sure fsp upd is overridden Change-Id: I5fab620a29aba196edf1f24ffe6a1695de1e523e Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/18060 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13	fsp_baytrail: Enable graphic init per default	Werner Zeh
	Baytrail SoC has a bug where in some cases the DisplayPort can hang leading to a non-working display (it just stays black). To avoid this hang, a patch was introduced in 02/2016 (1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort) but per default not switched on so that each mainboard can decide if it wants to use this patch or not. Recently a new case of this bug was reported by Benoit Sansoni (benoit.sansoni@kontron.com) and he requested to enable this fix per default as it costs him a lot of time to find the cause and even the already available fix in coreboot. To avoid this effort for someone else in the future we can enable this fix per default as no negative side effects are known and it is now tested at Siemens and at Kontron on different mainboards with success. As the goal is to enable this code permanently the config switch is not longer needed and is removed. Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/18109 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-13	soc/intel/skylake: Rename car_stage.S for fsp2_0	Teo Boon Tiong
	Cosmetic changes to rename car_stage.S to car_stage_fsp20.S, so that it is associated with FSP driver version that is being used. Tested on Kabylake Rvp11. Change-Id: I869df6eb746e3982e5912c272255eab6cb008838 Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com> Reviewed-on: https://review.coreboot.org/18083 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-12	fsp 1.0 systems: Check for NULL when saving HobListPtr	Martin Roth
	Die if cbmem_add can't allocate memory for the hob pointer. This shouldn't ever happen, but it's a reasonable check. - fsp_broadwell_de already had a check, but it returned to someplace inside the FSP. Just die instead. Change-Id: Ieef8d6ab81aab0ec3d52b729e34566bb34ee0623 Found-by: Coverity Scan #1291162 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18092 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-01-11	skylake: Do not pass VBT to FSP if display init not required	Duncan Laurie
	The FSP 2.0 change broke the logic for determining whether or not to execute the GOP binary. Modify the FSP 2.0 code to do the right thing and check for display_init_required() before passing VBT into FSP and the GOP binary. BUG=chrome-os-partner:61726 TEST=disable developer mode and ensure FSP does not run GOP Change-Id: I7fc8055b6664e0cf231a8de34367406eb049dfe1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18084 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-06	nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>	Arthur Heymans
	Nothing from that header is used or even declared since CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not selected on Intel hardware. Change-Id: I9101eb6ffa6664a2ab45bc0b247279c916266537 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18044 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2017-01-04	soc/intel/quark: Add monotonic timer support	Lee Leahy
	Add the Kconfig value HAVE_MONOTONIC_TIMER and the routine to read the TSC for the monotonic timer. Simplify the routine to get the TSC frequency. TEST=Build and run on Galileo Gen2 Change-Id: I806fb864b01e39277bf2d6276254b0543930c2f6 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18002 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03	soc/intel/quark: Add early debugging code	Lee Leahy
	Add Kconfig values and early debugging code to better segment and debug the early code in bootblock by using the SD LED as an indicator. Update the help text for the debug Kconfig values to point to the various failure locations. TEST=Build and run on Galileo Gen2 Change-Id: I1cd62eba3e9547cb1dd7f547aaec5d4827e14633 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/17985 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03	soc/intel/quark: Fix serial port configuration	Lee Leahy
	Fix serial port configuration broken by how PCI configuration space was referenced introduced by change 3d15e10a (MMCONF_SUPPORT: Flip default to enabled). TEST=Build and run on Galileo Gen2 Change-Id: I2ab52cf598795e94f1f16977f8d12b7fdd95e146 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/17984 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-27	cpu/intel/common: Add/Use common function to set virtualization	Matt DeVillier
	Migrate duplicated enable_vmx() method from multiple CPUs to common folder. Add common virtualization option for CPUs which support it. Note that this changes the default to enable virtualization on CPUs that support it. Change-Id: Ib110bed6c9f5508e3f867dcdc6f341fc50e501d1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17874 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-12-26	soc/intel/skylake: set TCC activation by BSP only	Sumeet Pawnikar
	TCC activation functionality has package scope. It was set for all CPU in the system which is unnecessary. In this patch TCC activation is being set by the BSP only. BUG=chrome-os-partner:59397 BRANCH=None. TEST=Built for skylake platform and verified the TCC activation value before and after S3. Change-Id: Iacf64cbc40871bbec3bede65f196bf292e0149a6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17889 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-23	spi: Get rid of SPI_ATOMIC_SEQUENCING	Furquan Shaikh
	SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with the ability to perform tx and rx of flash command and response at the same time. Instead of introducing this notion at SPI flash driver layer, clean up the interface to SPI used by flash. Flash uses a command-response kind of communication. Thus, even though SPI is duplex, flash command needs to be sent out on SPI bus and then flash response should be received on the bus. Some specialized x86 flash controllers are capable of handling command and response in a single transaction. In order to support all the varied cases: 1. Add spi_xfer_vector that takes as input a vector of SPI operations and calls back into SPI controller driver to process these operations. 2. In order to accomodate flash command-response model, use two vectors while calling into spi_xfer_vector -- one with dout set to non-NULL(command) and other with din set to non-NULL(response). 3. For specialized SPI flash controllers combine two successive vectors if the transactions look like a command-response pair. 4. Provide helper functions for common cases like supporting only 2 vectors at a time, supporting n vectors at a time, default vector operation to cycle through all SPI op vectors one by one. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17681 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-23	soc/intel/skylake: Use the new SPI driver interface	Furquan Shaikh
	1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCh=None TEST=Compiles successfully for chell and eve. Change-Id: I2fe0ef937297297339d4ea19dc37d3061caaa80c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-21	soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init	Brenton Dong
	FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize & tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to ApolloLake SoC when CONFIG_FSP_CAR is enabled. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/17063 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-15	soc/intel/common: provide option to invalide MRC cache on recovery	Aaron Durbin
	Allow a board/platform to invalidate the normal MRC cache when hardware retraining is requested in recovery mode. A small 4 byte payload is used to update the latest data written. It will of course fail on MRC cache retreival on next usage. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: Ic88cd66802664813562d003f50d54e4a4ea375ef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17870 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-15	soc/intel/apollolake: don't probe flash manually	Aaron Durbin
	Rely on boot_device_spi_flash() to provide the spi_flash object. There's no need to duplicate the probing logic. BUG=chrome-os-partner:56151 BRANCH=reef Change-Id: I91900a3dfad7ba92cbd3b0ace77b08db04cff0b6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17867 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-15	soc/intel/common: remove mrc cache assumptions	Aaron Durbin
	Update the mrc cache implementation to use region_file. Instead of relying on memory-mapped access and pointer arithmetic use the region_devices and region_file to obtain the latest data associated with the region. This removes the need for the nvm wrapper as the region_devices can be used directly. Thus, the library is more generic and can be extended to work on different boot mediums. BUG=chrome-os-partner:56151 Change-Id: Ic14e2d2f7339e50256b4a3a297fc33991861ca44 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17717 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-14	soc/intel/broadwell/lpc.c: don't zeroize existing gnvs table	Matt DeVillier
	The gnvs table only needs to be zeroized after init; zeroizing an existing/populated table renders all I2C devices completely non-functional. TEST: boot Linux and observe all I2C devices functional Change-Id: Id149ad645dfe5ed999a65d10e786e17585abc477 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17828 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-13	intel MMA: Enable MMA with FSP2.0	Pratik Prajapati
	- Separate mma code for fsp1.1 and fsp2.0 and restructuring the code - common code is placed in mma.c and mma.h - mma_fsp<ver>.h and fsp<ver>/mma_core.c contains fsp version specific code. - whole MMA feature is guarded by CONFIG_MMA flag. Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/17496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-11	x86 SMM: Fix use with RELOCATABLE_RAMSTAGE	Kyösti Mälkki
	The value for _size was not evaluated correctly if ramstage is relocated, make the calculation runtime. While touching it, move symbol declarations to header file. Change-Id: I4402315945771acf1c86a81cac6d43f1fe99a2a2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17784 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08	soc/intel/apollolake: Move privilege drop to later stage	Andrey Petrov
	Previously privilege drop was happening "too early" and that caused some PMC IPC programming (performed in FSP) to fail because sideband was already locked out. This change set moves privilege drop to later stage, after last FSP notify call. BRANCH=reef BUG=chrome-os-partner:60657 TEST=iotools rdmsr X 0x121, make sure they can't be read. Also dmesg\|grep -i IPC to make sure there are no errors related Change-Id: Ia3a774aee5fbf92805a5c69093bfbd3d7682c3a7 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17769 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-08	soc/intel/apollolake: Set PL2 in RAPL register	Sumeet Pawnikar
	This patch sets the package power limit (PL2) value in RAPL register. BUG=chrome-os-partner:60535 TEST=Built, booted on reef and verified PL2 value. Change-Id: I83fe854cf3e9fc92ab87f84b86e64ebb6085065f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17699 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07	soc/broadwell: set EM4/EM5 registers based on cdclk	Matt DeVillier
	The EM4/EM5 registers in the mini-HD audio device must be set based on the GPU cdclk value in order for HDMI audio to function properly. Add variables to save the correct values when initializing the GPU, and accessor functions to retrieve them in order to set the registers when initializing the mini-HD audio device. Change-Id: Icce7d5981f0b2ccb09d3861b28b843a260c8aeba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17718 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-12-07	soc/intel/apollolake: Use the new SPI driver interface	Furquan Shaikh
	1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully for reef. Change-Id: If07db9d27bbf4f4eb6024175cb7753c6cf4fb793 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17562 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)