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2016-01-19intel/skylake: Disable SaGv in recovery modeharidhar
This patch disables the SaGv feature in recovery mode. Since the memory training happens at both low and high frequency points when SaGv is enabled, recovery mode boot time increases by 5 seconds. To reduce this 5 second increase, the SaGv feature is disabled in recovery mode. The value "0" here means SaGv disable. Following is the table for same. 0=Disabled (SaGv disabled) 1=FixedLow (Fixed to low frequency) 2=FixedHigh (Fixed to High frequency) 3=Enabled (SaGv Enabled. Dynamically changes) BRANCH=None BUG=chrome-os-partner:48534 TEST=Built for kunimitsu. Results show recovery mode boot time is not affected (not increased). Change-Id: I77412a73a183a5dbecf5564a22acc6e63865123e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: dc586079052acf9af573b68dff910386cd43484d Original-Change-Id: Ice3e1a630e119d40d3df52e3a53ca984e999ab0b Original-Signed-off-by: haridhar <haridhar.kalvala@intel.com> Original-Signed-off-by: Somayaji, Vishwanath <vishwanath.somayaji@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315759 Original-Commit-Ready: Haridhar Kalvala <haridhar.kalvala@intel.com> Original-Tested-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Reviewed-on: https://review.coreboot.org/12998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-19soc/braswell: Remove the unneccessary functions from pcie.cShaunak Saha
Functions in file pcie.c is not needed. TEST=Boot and test wifi and video playback Original-Reviewed-on: https://chromium-review.googlesource.com/298965 Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I70337c0fc61c221330836ef17f6cefea8c5f0f11 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/12737 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-19intel/skylake: Add support for IV feedback loop capture blobSathya Prakash M R
SSM4567 smart speaker needs Current and Voltage sensing to be captured and reported to the algorithm. This needs 4 CH capture blob. BUG=chrome-os-partner:48625 BRANCH=none TEST=Built and booted. Verified CBFS locates the blob. CQ-DEPEND=CL:*242635 Change-Id: Ie13622da9a9a8ce5930d32e52ddaf2e0d4862895 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 06f1a501dcb3fa6102eccdb3e24f9011b7869ab0 Original-Change-Id: I7b65b7582b619be53544ebbe4b3ea65398d32a34 Original-Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319020 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12995 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: Change in UPD name from SkipMpInit to FspSkipMpInitBarnali Sarkar
Changing the UPD param name from "SkipMpInit" to "FspSkipMpInit" BRANCH=none BUG=none TEST=Build and booted in kunimitsu with FspSkipMpInit token enabled from Coreboot. Change-Id: I5ebe7a1338ac77a62d5aa2e48e083b4fb906bf28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cdaa95a82bc7e90637c6b90e33d88d040e085f58 Original-Change-Id: Ibdaa3d202f8f6f6f0ca6c6d4c6428f1616572f1d Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319353 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12993 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-18intel/skylake: Remove unused devicetree configuration variablesDuncan Laurie
The GPU panel configuration variables are unused on skylake and are no longer needed in chip.h. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-chell coreboot Change-Id: Ie6bfb676b5a32b4d4d39dda91b90fc7e973d38e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f261d7ca9ec93aae1362975efde11ac9657b7ca6 Original-Change-Id: If64594455754e4dea1f53511861b74ddd880c5b5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/318923 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12986 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: provide default VR configurationAaron Durbin
FSP 1.8.0 will do nothing with the VR settings if VrConfigEnable is non-zero. That behavior is not desired because it's not clear what the behavior will be for various processor SKUs. Instead provide default values for the VR config. Note that PSI3 and PSI4 are not enabled for those defaults. BUG=chrome-os-partner:48466 BRANCH=None TEST=Built and booted glados. Change-Id: I02cb5fbdd4549cc827a0b0e4006bc21da4593b55 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a68c53e0fdf15584270dfafc679a22319f497d17 Original-Change-Id: I82b1d1da2cfa3c83ccc6a981e30ffac6fb6c8c4b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/318263 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12983 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: Add devicetree setting for DDR frequency limit UPDDuncan Laurie
There is a UPD setting exposed by FSP that allows the DDR frequency to be limited. Expose this for devicetree. BUG=chrome-os-partner:47346 BRANCH=none TEST=tested by limiting DDR frequency to 1600 on chell EVT Change-Id: I1f17b221d9fa4c2dd1e8c5f403deb0f2bc0493a7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 91f760ad19823225f7e5bd2dc690164ed253e220 Original-Change-Id: Ibcd4a65a9cfd7d32fbf2ba8843ab25da8e9cf28a Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317243 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12981 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: Add elog event for THERMTRIPDuncan Laurie
The THERMTRIP status bit is in GBLRST_CAUSE instead of GEN_PMCON like the EDSv1 indicates. Read this status bit and add an elog event if THERMTRIP has fired. BUG=chrome-os-partner:48438 BRANCH=none TEST=tested on chell EVT after thermtrip fired Change-Id: Icd52b753c7f3ab0d48095279f1255dd2dd08fd59 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b090c7897a8f99a685f523990235d83fafa063b2 Original-Change-Id: I5a287d7fdae2ba8ae8585cb9a4d4dd873393e1e6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317242 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12980 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17intel/skylake: disable heci1 if psf is unlockedArchana Patni
This patch adds support for disabling the heci1 device at the end of boot sequence. Prior to this, FSP would have sent the end of post message to ME and initiated the d0i3 bit. This uses the Psf unlock policy and the p2sb device to disable the heci1 device, then lock the configuration and hide the device. BRANCH=none BUG=chrome-os-partner:45618 TEST=build for kunimitsu or glados board. set the hecienabled policy to 0 and check for heci 1 device status in kernel lspci. CQ-DEPEND=CL:*238451 Change-Id: I26b145231f8ed0c140af42d378b222e857d9aff6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fe184b8baf1bea9bcd0af1841785a4d763af9358 Original-Change-Id: I3b435491aeea0f2ca36b7877e942dc940560e4dd Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311912 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12976 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-17intel/skylake: During RO mode after FSP reset CB lose original stateSubrata Banik
CB used to clear recovery status towards romstage end after FSP memory init. Later inside FSP silicon init due to HSIO CRC mismatch it will request for an additional reset.On next boot system resume in dev mode rather than recovery because lost its original state due to FSP silicon init reset. Hence an additional 1 reset require to identify original state. With this patch, we will get future platform reset info during romstage and restore back recovery request flag so, in next boot CB can maintain its original status and avoid 1 extra reboot. BUG=chrome-os-partner:43517 BRANCH=none TEST= build and booted Kunimitsu and tested RO mode Change-Id: Ibf86ff2b140cd9ad259eb39987d78177535cd975 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 40ddc21a97b318510116b7d5c4314380778a40f7 Original-Change-Id: Ia52835f87ef580317e91931aee5dd0119dea8111 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/302257 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12975 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16intel/skylake: Fix uninitialized variable warningMartin Roth
I don't think the warning is valid, because we already verify that num_channels is 2 or 4 as soon as we enter the function. Adding the default case makes the compiler happy. Fixes warning: src/soc/intel/skylake/nhlt/dmic.c: In function 'nhlt_soc_add_dmic_array': src/soc/intel/skylake/nhlt/dmic.c:100:2: error: 'formats' may be used uninitialized in this function [-Werror=maybe-uninitialized] return nhlt_endpoint_add_formats(endp, formats, num_formats); ^ Change-Id: Idc22c8478ff666af8915d780d7553909c3163690 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/13021 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-16intel/skylake: Add kconfig option to skip Native SD ControllerSubrata Banik
Skylake Core boot should have configurable option to skip PCH based SD 3.0 Controller from customer/reference design. Addition to that no unused or unnecessary should list under device view. BUG=chrome-os-partner:48190 BRANCH=None TEST=Build & boot Kunimitsu and LARs. Change-Id: Ie17fd6db01e0cabcdf605017509d809b54509a0d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 99ac17b723125822368539d0562aa35119e520fb Original-Change-Id: I98a48f45ef442246227fd54ea021b53f824954c5 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/315420 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12946 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-16intel/skylake: Add VrConfig UPD parameters from corebootRizwan Qureshi
Adding VrConfig UPDs and assign values to those from devicetree BRANCH=none BUG=chrome-os-partner:45387 TEST=Build and booted in kunimitsu CQ-DEPEND=CL:310192 Change-Id: Ifce9dfacabc742b55266c48459c56c69b1f22236 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b34a3cc77afc8795abb64972f8169986c30c2acd Original-Change-Id: Ifa960e718ed77db729f1fc4e2c00c9b305093e04 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311317 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12944 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-16intel/skylake: Enable SkipMpInit tokenRizwan Qureshi
This patch helps to enable SkipMpInit token of FSP SiliconInit UPD BRANCH=none BUG=chrome-os-partner:44805 TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB. CQ-DEPEND=CL:310869 Change-Id: I43377e4b8adadf42091a9387883363fdfbab4c1b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b7962273fd1a591cfe9a658f49ebc7d23bcad577 Original-Change-Id: I977d2d39c283d74f1aa9033c8aa60dc652735019 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310192 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12943 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/skylake: Init variable so GCC knows it's setMartin Roth
Even though the data32 variable was getting written by pch_pcr_read(), GCC still flagged it as being used while uninitialized and failed the build. Note that pch_pcr_read() may only set 1 or 2 bytes of data32 in the successful path, depending on the size of the read. Change-Id: Icd6e80d06b9bf4af506d62d55ffe4c5e98634b2b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12860 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2016-01-15intel/skylake: More UPD params are added for PCH policy in FSPRizwan Qureshi
Some more PCH Policy UPD Parameters are added in FSP. Lockdown config moved from FSP to coreboot. Removing settings in devicetree.cb which are zero. BRANCH=none BUG=none TEST=Build and booted on kunimitsu, verified that CB is doing the Lockdowns which were previously done by FSP. CQ-DEPEND=CL:*237842, CL:310191 Change-Id: I3dcf3a5340f3c5ef2fece2de5390cde48db4d327 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e8bdb35897b640d271adcaed266030367f060553 Original-Change-Id: Ia201672565c07b2e03d972b2718512cd4fcbb95c Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310869 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12941 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-01-15intel/skylake: Update UPD parameters as per FSP 1.8.0Barnali Sarkar
Some MemoryInit UPD parameters have been moved to SiliconInit in FSP 1.8.0. This patch has the respective changes in coreboot for this. BRANCH=none BUG=none TEST=Build and booted in kunimitsu CQ-DEPEND=CL:*237423, CL:*237424 Change-Id: Ic008d22f96fb5f14965e5b5db15e05fb39dd52d3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 573c1d8325cd504213528030ecf99559402b5118 Original-Change-Id: I71b893aa7788519ed2ef15f3247945ffcbbbcf4d Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/310191 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12940 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/skylake: Add GPIO ACPI Apis.Subrata Banik
GPIO ASL APIs to get GPIO Value. Need such APIs to read GPIO config settings. Example: Kunimitsu need to read AUDIO_DB GPIO to identify codec select. BUG=chrome-os-partner:44481 BRANCH=none TEST=build and boot on Kunimitsu. Change-Id: If56bb7b3eae08e1949d372850a6426dfde5aadd0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4983ba835a8da2baf578b035ae482755983c1ecb Original-Change-Id: Ia40d86c8d4b14857fa8822677b3f7d393a35b677 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/316352 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12956 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-15intel/skylake: add nhlt supportAaron Durbin
The use of a NHLT table is required to make audio work on the skylake SoCs employing the internal DSP. The table describes the audo endpoints (render vs capture) along with their supported formats. These formats are not only dependent on the audio peripheral but also hardware interfaces. As such each format has an associated blob of DSP settings to make the peripheral work. Lastly, each of these settings are provided by Intel and need to be generated for each device's hardware connection plus mode/format it supports. This patch does not include the dsp setting blobs. The current supported connections: - digital mic array 2 channel - digital mic array 4 channel - Maxim 98357 amplifier - ADI ssm4567 - NAU88L25 headset codec BUG=chrome-os-partner:44481 BRANCH=None TEST=Built glados. Speakers, headphones, and mic on camera decently worked. CQ-DEPEND=CL:*239598 Change-Id: If1a9be97573b9b160893944661790cac7df26fca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1f5514e27811c500732de97e1cc7edeced2607e7 Original-Change-Id: Ib42e895f00e7605cb30ce24d9b8dd00bf68a7477 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313998 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12938 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14soc/braswell: Add CPUID for D0 steppingDivya Sasidharan
Original-Reviewed-on: https://chromium-review.googlesource.com/309122 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Change-Id: Ia24dbeb6b23ccbbb380843a4684def578cde168a Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://review.coreboot.org/12727 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14soc/braswell: Fix P-state tableSubrata Banik
Incorrect bus-core-ratio been used to generate P-state table Original-Reviewed-on: https://chromium-review.googlesource.com/290681 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I4a34ec80ff3f2ed46dc074c9f8fe06756db8b357 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/12731 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-14intel/skylake/pcr.c: error out on invalid size in pcr read/writeMartin Roth
The read and write routines take a number of bytes to write, which should be 1,2, or 4. We now return an error if an invalid size is specified. Change-Id: I93344bc0837c3715fc7660503f405c8878eb711c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12936 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-13tree: drop last paragraph of GPL copyright header from new filesMartin Roth
This continues what was done in commit a73b93157f2 (tree: drop last paragraph of GPL copyright header) Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12914 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-12intel/skylake: Remove check for Microcode loaded by MEMartin Roth
This method of reporting has been removed from the current Skylake ME binaries so is no longer needed. Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12854 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-08fsp_baytrail: Add additional PCI space above 4GBMartin Roth
This just tells the OS that it can use the 16GB of address space at the 48GB mark for PCI. This is the upper 16GB of Bay Trail's 36 bit physical address space. This could be hardcoded into the UMEM definition, but doing it this way makes it more plain what it's doing, and allows for modification to put it just above the top of upper memory, similar to what is done with the standard PCI region above the top of low memory. Change-Id: Id6208c3712e5d94d62a83c4ac69e8ffd0e19f4ad Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12791 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: York Yang <york.yang@intel.com>
2016-01-07intel/braswell: Disable IFD & ME by default so abuild can buildMartin Roth
The Braswell IFD & ME blobs aren't published in the 3rdparty repo, so disable them by default for now. Change-Id: If68ff1f37fbf7afb2f9eb1e5d9942afcf40ab1e3 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-07Correct some common spelling mistakesMartin Roth
- occured -> occurred - accomodate -> accommodate - existant -> existent - asssertion -> assertion - manangement -> management - cotroller -> controller Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-06intel/braswell: Build in both C0 and 'other' vbiosMartin Roth
The Braswell CPU seems to have two different Video BIOS roms, one for the C0 revision, and one for other revisions. Build them both into the coreboot image, and let coreboot sort out which one should be used at runtime. This should allow one rom to be used for all revisions. The initial reason for this patch was that the Kconfig symbol C0_DISP_SUPPORT didn't exist, and was causing issues. This seems like the best way to eliminate the need for that symbol. Change-Id: I5b9f225c0daf4e02fda75daf9cd07bb160bf0e0f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12826 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-27soc/intel/broadwell: Add back support for EHCI debug setupDuncan Laurie
The EHCI debug device setup code was removed from broadwell in commit 49ee5ef: http://review.coreboot.org/11874 However the generic device setup code is in the southbridge/common/intel directory while broadwell is in the soc directory so this is not used. Add it back to the broadwell soc to fix undefined reference compile errors with 'pci_ehci_dbg_dev' and 'pci_ehci_dbg_enable'. This was tested to compile and produce romstage and ramstage output on a google/samus board. Change-Id: Ia93825a1e21a770f6c82d0989cb97980a5c700d6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/12794 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-27broadwell: Fix SATA Gen3 DTLE configuration registersDuncan Laurie
The port0 and port1 registers were swapped, which meant it did not work to apply the DTLE settings to the correct SATA port. This was tested on an unreleased mainboard but is verified with the documentation to be the correct register addresses now. Change-Id: Ifb8890a563a741129ec8ddf72e73ab021c7d33da Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/12793 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-27broadwell: Fix CONFIG_SPI_CONSOLE usageDuncan Laurie
Locking down the SPI controller with a specific opcode menu kills the SPI console. Skip this when the SPI console config option is enabled. This was tested using an em100 and google/samus board to ensure the console output does not stop at the finalize step. Change-Id: Ie460f583214b47544e92d4afa8ef862563a11e36 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/12792 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-12-26ACPI: Add hack to avoid IASL warning when reading back registersMartin Roth
Upcoming versions of IASL give a warning about unused methods. This adds an operation after the read to use the local variable and avoid the warning. The warning can be completely disabled on the command line, but as it can find real issues, my preference is to not do that. Fixes warnings: dsdt.aml 640: Store (CTMP, Local0) Warning 3144 - Method Local is set but never used ^ (Local0) Change-Id: If55bb8e03abb8861e1f2f08a8bcb1be8c9783afe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12704 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-22soc/intel/fsp_baytrail: Make sure i2c bus is < 7Martin Roth
Baytrail has I2c Busses 0 to 6, so is supposed to error out if the I2c driver is called with 7 or greater. Due to an off-by-one error it could be called with bus 7. Fixes coverity warning: CID 1287074 (#1 of 1): Out-of-bounds read (OVERRUN) 3. overrun-local: Overrunning array base_adr of 7 4-byte elements at element index 7 (byte offset 28) using index bus (which evaluates to 7). Change-Id: I7caec60298cf27bd669796e0e05e4a896f92befd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12781 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-12-20soc/intel/broadwell: Init var before use, only use when neededMartin Roth
root_port_init_config() pcie.c wasn't initializing a variable before passing its pointer to pch_iobp_exec(). pch_iobp_exec() wrote the uninitialized value into a register. In theory, the register would only be used if data was being written, and pch_iobp_exec() was being used to read the data, not write it, so this change shouldn't have any practical effect. Fixes coverity error: CID 1293134 (#1 of 1): Uninitialized scalar variable (UNINIT) Change-Id: I5d17863d904c6b1ceb30d72b94cd7a40c8fbb437 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12778 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-12-17soc/intel/fsp_baytrail: Adjust root port INT routingMartin Roth
Adjust the root port INT routing based on Bay Trail spec: Document Number: 538136, Rev. 3.9 Table 241. Interrupt Generated for INT[A-D] Interrupts INTA INTB INTC INTD Root Port 1 INTA# INTB# INTC# INTD# Root Port 2 INTD# INTA# INTB# INTC# Root Port 3 INTC# INTD# INTA# INTB# Root Port 4 INTB# INTC# INTD# INTA# Change-Id: I22a8c0bc6ad731dfb79385d6e165f1ec0a07507d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12684 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2015-12-16intel/fsp_baytrail: change indent to use tabsBen Gardner
Change-Id: If0d0a15442738bab0e34f1b05513e7f8e8fa9afc Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12698 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-16intel/fsp_baytrail: rename include folder baytrail to include/socBen Gardner
This is to match the layout of the non-fsp baytrail to make comparisons easier and possibly remove duplicate files. Change-Id: I9a94842d724ab3826de711d398227e7bdc1045ff Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12686 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-16intel/fsp_baytrail: Fix PCI_DEV_PIRQ_ROUTE macro endingBen Gardner
The macro PCI_DEV_PIRQ_ROUTE ends with a comma and escaped newline. Ending a macro with an escaped newline is always wrong. The final comma is not necessary, as all uses of PCI_DEV_PIRQ_ROUTE() properly separate calls with a comma. I haven't investigated whether this is causing a real issue, but it should be leaving gaps in struct baytrail_irq_route.pcidev. The non-FSP baytrail does not have this issue. Change-Id: If6782176068b07cb3bc819c00d1cdb1b618bcea8 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12696 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-12-16intel/skylake: Work around ROMCC optimization bugStefan Reinauer
On Skylake systems, the bootblock fails to compile with the following error message: bootblock_simple.c:6.1: 0x13930e0 copy Internal compiler error: non dominated rhs use point 0x13a3f70? Aborted (core dumped) The option -fno-simplify-phi works around the issue, but will cause the code to use more registers, hence we also need to enable -mcpu=p4 (see intel/truxton mainboard for another example of where this has been done in the past) Change-Id: Iea1a1ba18d76c7323bb626c5f4b0032e4ee04a86 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12719 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-15x86 acpi: remove ALIGN_CURRENT macroAaron Durbin
The ALIGN_CURRENT macro relied on a local variable name as well as being defined in numerous compilation units. Replace those instances with an acpi_align_current() inline function. Change-Id: Iab453f2eda1addefad8a1c37d265f917bd803202 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12707 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-11mrc_cache: add version fieldAaron Durbin
In order to allow for updateable memory init code on intel x86 platforms one needs to ensure the saved mrc data matches the code consuming the data. To that end add a version field to the saved data structure. BUG=chrome-os-partner:46050 BRANCH=None TEST=Built and booted on glados. Suspended and resumed. Also verified version mismatch path. Change-Id: Ie86db1750af5d9bff6446999b0d04b60612f8d29 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12700 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-10ACPI: Fix IASL Warning about unused method for GBUF checkMartin Roth
According to the ACPI Spec for CondRefOf, the result argument is optional. In all of these locations, it was getting set but not used, creating a warning in new versions of IASL. Since it's an optional argument, just remove it. dsdt.aml 640: If (CondRefOf (^GBUF, Local0)) { Warning 3144 - Method Local is set but never used ^ (Local0) Change-Id: Ie2f46808e92c309a63ba7661bcbd77402a08366a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12694 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-10intel/fsp_baytrail: Remove code for nonexistant BBARBen Gardner
The BBAR register (BIOS Base Address Configuration Register) defined in the ICH9 datasheet does not exist in the Bay Trail E3800 datasheet. Accessing it seems harmless, but should likely be avoided. Change-Id: I5d9a6a1ccead84c8996796f516a2bdc5f248cfef Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12671 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-10lib: remove assets infrastructureAaron Durbin
Now that only CBFS access is supported for finding resources within the boot media the assets infrastructure can be removed. Remove it. BUG=chromium:445938 BRANCH=None TEST=Built and ran on glados. Change-Id: I383fd6579280cf9cfe5a18c2851baf74cad004e9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12690 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-08soc/intel/common: Remove USE_FMAP - symbol doesn't existMartin Roth
The USE_FMAP Kconfig symbol doesn't exist, so remove things that are depending on it not being enabled. Change-Id: I1946f5d13a762ab07744a1d9a6cb754433e6701d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12663 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-08soc/intel/skylake: Remove obsolete Kconfig symbolsMartin Roth
CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit 66e0c4c8 (cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS) Both CPU_MICROCODE_IN_CBFS and SUPPORT_CPU_UCODE_IN_CBFS were present, so just remove CPU_MICROCODE_IN_CBFS. SMM_MODULES was removed in commit 44cbe10f (smm: Merge configs SMM_MODULES and SMM_TSEG) Change-Id: Icdd4fcc5a3a97aee443742aaab3df92b53ff4589 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12662 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-12-06fsp_baytrail: Add missing newline to eMMC Mode logBen Gardner
Change-Id: Icd697053c2ea1a2ac42bdd045134d223d93d5403 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/12623 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-06Remove #ifdef checks on Kconfig symbolsMartin Roth
In coreboot, bool, hex, and int type symbols are ALWAYS defined. Change-Id: I58a36b37075988bb5ff67ac692c7d93c145b0dbc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12560 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-04braswell/skylake: Add FspUpdVpd.h to fix compilationStefan Reinauer
Imported from cros repo 18ae19c Change-Id: Ib88ac9b37d2f86d323b9a04cb17a5a490c61ff5b Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/12467 Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins)
2015-12-03intel/skylake: Add ACPI device for audio controllerDuncan Laurie
Add the audio controller device to ACPI and define the _DSM handler to return the address of the NHLT table, if it has been set in NVS. BUG=chrome-os-partner:47346 BRANCH=none TEST=build and boot on glados and chell Change-Id: I8dc186a8bb79407b69ef32fb224a7c0f85c05bc4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6b73fba375f83f175d0b73e5e70a058a6c259e0d Original-Change-Id: Ia9bedbae198e53fe415adc086a44b8b29b7f611d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313824 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12597 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03intel/skylake: Remove unused code to add SSDT2Duncan Laurie
This code is doing nothing and is not needed. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados Change-Id: I910d443f09a94de1ee0de03cda0577b8847b2de8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ac09fdd7673e5fceb8bfaf1076a8a91e54fc31af Original-Change-Id: Id989c82853d5a5d5b750def073d34c39816a48d5 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/313823 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12596 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-30fsp_baytrail: Remove use of BAYTRAIL_SMM Kconfig symbolMartin Roth
The symbol BAYTRAIL_SMM was never valid (there's no config statment initializing the symbol), but it was being selected and used in the code. Now that SMM is supported in fsp_baytrail, the code it was trying to switch can be removed, and just set up for SMM. Change-Id: I0fd4865a951734e728500e7baf593ff7eb556f73 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12553 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
2015-11-28baytrail: fix missing brackets around ir_base to fix IRQ routingAlexander Couzens
The missing brackets caused other registers, including the IO APIC enable bit (EAN in OIC) to be overwritten. Bug introduced by bde6d309 (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer) Change-Id: I1d5aa2af6d74405a1a125af6221ac0e635a6b693 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/12525 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-27soc/intel/common: Fix whitespace in KconfigMartin Roth
Change leading spaces to tabs. Change-Id: Ief138f5f68198578ba9dddb8fbdabbd9a0185a21 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-24intel/soc/baytrail: Move MCRS ResourceTemplate out of _CRS methodMartin Roth
Fixes these remarks: Object is not referenced (Name is within method [_CRS]) The ACPI compiler is trying to be helpful in letting us know that we're not using various fields in the MCRS ResourceTemplate when we define it inside of the _CRS method. Since we're not intending to use those objects in the method, it shouldn't be an issue, but the warning is annoying and can mask real issues. Moving the creation of the MCRS object to outside of the CRS method and referencing it from there solves this problem. Change-Id: I54ab3ad9ed148fdd24e8615d83bc8ae668d1dbff Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/12514 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-24soc/intel/braswell: Drop gfx_read_resources()Nico Huber
Drop the last remnant of vanished CONFIG_MARK_GRAPHICS_MEM_WRCOMB. Could not build test google/cyan and intel/strago due to lack of UEFI headers, OMG. Change-Id: I0b9eac5c040d24bab2b85e9b63042b6aaa9879d9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: http://review.coreboot.org/12338 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-21baytrail: add C0 and D0 stepping decodeBen Gardner
The E3800 with ordering code FH8065301487717 is stepping D0, value 0x11. Add that so the debug log shows 'D0' instead of '??'. Also, add the C0 stepping decode to fsp_baytrail. Change-Id: Ibec764fcf5d3f448e38831786a071f5ab6066d67 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: http://review.coreboot.org/12488 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-11-20intel/skylake: Fix flash_controller.c compilationStefan Reinauer
Since this code is not currently being built by coreboot, it failed compilation. Change-Id: Ib8a0e1ebc76b7dca3dd785b09398b73abad46366 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/12466 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-20intel: Add MMA feature in corebootPratik Prajapati
This patch implements Memory Margin Analysis feature in coreboot. Few things to note (1) the feature is enabled by setting CONFIG_MMA=y in the config file (2) coreboot reads mma_test_metadata.bin from cbfs during romstage and gets the name of MMA test name and test config name. Then coreboot finds these files in CBFS. If found, coreboot passes location and size of these files to FSP via UPD params. Sets MrcFastBoot to 0 so that MRC happens and then MMA test would be executed during memory init. (3) FSP passes MMA results data in HOB and coreboot saves it in cbmem (4) when system boots to OS after test is executed cbmem tool is used to grab the MMA results data. BRANCH=none BUG=chrome-os-partner:43731 TEST=Build and Boot kunimitsu (FAB3) and executed MMA tests Not tested on Glados CQ-DEPEND=CL:299476,CL:299475,CL:299474,CL:299473,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479 Change-Id: I0b4524abcf57db4d2440a06a79b5a0f4b60fa0ea Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4aba9b728c263b9d5da5746ede3807927c9cc2a7 Original-Change-Id: Ie2728154b49eac8695f707127334b12e345398dc Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/299476 Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: http://review.coreboot.org/12481 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-20fsp1_0: Remove hardcoded microcode locationsMartin Roth
These are no longer needed. Test: Booted minnowmax. Change-Id: Ie77040f3506464c614760bd4d30280c8113373bd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12468 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-11-17fsp_baytrail: use external microcode .h filesMartin Roth
The microcode for Bay Trail that's in the blobs repo is for the M and D chip variants only. The fsp_baytrail directory is for Bay Trail I chip variants, and will not boot if the M/D microcode is used. The microcode for the I variant is supplied as part of the Bay Trail FSP package. Change-Id: I5493deb1626dc3cf037053e13e092f5a1143a13a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12334 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-16intel/fsp_baytrail: Load APs microcode in baytrail_init_cpusYork Yang
Load microcode to APs when performing baytrail_init_cpus. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. Change-Id: I7b7c0f43da0d149048ae5a8fd547828f42de04fd Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/12095 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-16intel/fsp_baytrail: Load BSP microcode in bootblockYork Yang
Load microcode to BSP in bootblock so later on the FSP TempRamInit call can be success. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. If BSP is not loaded a microcode before calling TempRamInit API, the call will fail with the error No Valid Microcode Was Found. Change-Id: I1fbe68e14e5a24d8f2da70603cd2f03675b9ca81 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/11896 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2015-11-13intel/skylake: ensure the RTC time is setAaron Durbin
In 2014 or so the RTC code was changed to assume the ALTCENTRY register (0x32) as always being utilized for creating an rtc_time. However, one needs to ensure it's set at least once otherwise the year field in rtc_time is not sane. In practice this doesn't matter unless somone wants to use the full year value. cmos_init() should do the same thing in the rtc fail case, but the machine I had never had that set correctly. BUG=chrome-os-partner:47388 BRANCH=None TEST=Booted glados w/ 0xff ALTCENTRY value. New value is 0x20. Change-Id: I028f801c5d717a0018ed00df82c25b466d64670c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7d5be5bc697bef60a264ddc7f67755aa96088d36 Original-Change-Id: I6e12a30c9e08d8c1002e4cef0f143f0f88009e92 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311264 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12411 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-11fsp_baytrail: Add macros for legacy GPIO output set upWerner Zeh
Up to now the GPIO set up macros for input sets up GPIOs to be mapped to memory space while macros for outputs sets up GPIOs to be mapped to legacy io space. This patch adds two additional macros for legacy output definition and changes the old macros to memory space mapping. In addition, the intel/minnowmax mainboard is modified to use the legacy macros for outputs to ensure this mainboard stays unchanged in terms of functionality. TEST=Booted siemens/mc_tcu3 and ensured GPIO set up in linux. Change-Id: I99e98d31e1a59e63c58d536f2c493d6dcbfd1e75 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/12340 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-09fsp_baytrail: Add functions to set a GPIOWerner Zeh
Add two functions to set a memory mapped GPIO to a given value. TEST=Booted siemens/mc_tcu3 board and confirmed GPIO-value after using this functions. Change-Id: Idc14c5d4049487e60040cc294ba0cea363d998a6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/12341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-05Kconfig: Remove obsolete Kconfig symbols from google/intel boardsMartin Roth
- CACHE_ROM is no longer used in the coreboot code. It was removed in commit 4337020b (Remove CACHE_ROM.) - CAR_MIGRATION is also no longer used in coreboot code - it was removed in commit cbf5bdfe (CBMEM: Always select CAR_MIGRATION) - MARK_GRAPHICS_MEM_WRCOMB was removed in commit 30fe6120 (MTRR: Mark all prefetchable resources as WRCOMB) Change-Id: I8b33a08c256f6b022e57e9af60d0629d9a3ffac8 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12327 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-05intel/skylake: Add Fan control supportSumeet Pawnikar
This patch adds the ASL file for Fan as cooling device /participant for thermal active cooling action for DPTF on SKL-U fan based kunimitsu board. With active cooling policy (_ART), we can control the fan on/off and speed. BRANCH=None BUG=chrome-os-partner:46493 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also, checked the FAN type the cooling devices enumerated in the /sys/class/thermal with sysfs interface. Change-Id: Iacfd9152e300ec47895c29deab2c9d4361230849 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d37a089b5196f02cb95f16083c416456e96d54a4 Original-Change-Id: I8293bfe2a2bf213b69fbb4223bbfcf508a9cf0bf Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/307027 Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12322 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05skylake: Set Pkg Power clamping bit in Power Limit MSRRizwan Qureshi
Setting the Package Power clamping bits in Power Limit MSR (MSR_PKG_POWER_LIMIT 0x610) Allows going below the OS requested P or T state for the time window specified for PL1 or PL2. BRANCH=none BUG=chrome-os-partner:47041 TEST=Built and boot on kunimitsu, load the system with Aquarium WebGL, change the power limit value from default (TDP or 15W) to any lower value note that the Pkg power comes down and also the CPU frequency is lowered. Change-Id: I9c0dd90a6660214ae142418aae8b8c5f6a739896 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b0b527991c2d26da5772700a22ff101eaf9993ef Original-Change-Id: Ia59fcfe2a14cd7f8b1e1b8e967073e67eb452f42 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/309556 Original-Tested-by: Charulatha Varadarajan <charuprasanna@gmail.com> Original-Tested-by: Charulatha Varadarajan <charulatha.varadarajan@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12257 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-28intel/skylake: Add USB2 port config for max settingsDuncan Laurie
Add a new USB2_PORT_MAX with the max possible settings (56mV) for the TX and Pre-emphasis bias values. Also fix the settings for the detachable tablet config to match the skylake HSIO tuning guide as it was incorrect before. BUG=chrome-os-partner:45367 BRANCH=none TEST=build and boot on glados Change-Id: Id9ccc683fe92c962095347e0d1a0afeb082c821f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e5d56831e75f98a3c75ed333e4b79b1a37f14792 Original-Change-Id: Ia2e3e93236f1463201f83a1cae28349de2836110 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/308729 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12203 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-27intel/skylake: Clean up USB configuration in devicetreeDuncan Laurie
Instead of having many different arrays for USB configuration, with each array containing one bit of information, have one array containing all the information for each port. This way we can put the basic tuning parameters into a structure and then define structures for the basic supported configurations. The existing port definitions are taken from the Skylake HSIO tuning guide. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados, verify USB functionality in all ports. Change-Id: I5873dee011ae9e250b6654c73a7bd5c17681095b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 864040412b2d2923d3acbfca8055724887c58506 Original-Change-Id: Id518b1086abbe4a8c25d77fd4efc2d0de856bd5f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/306734 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12163 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27FSP1_1: Always use common codeLee Leahy
Always use the common FSP code. Remove the FSP_RAM_INIT, FSP_ROMSTAGE, FSP_STACK and FSP_STAGE_CACHE Kconfig values. BRANCH=none BUG=None TEST=Build and run on Kunimitsu Change-Id: Ib3d015cb2dc257e46c2340cc7bc09cf0ffb0492c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5197b1354d138759dfaa428c665de6cbfb8e8911 Original-Change-Id: I3e3c1c9e6f73009a099c1ec3688dbd8c326fc766 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/306142 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12158 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-10-27FSP 1.1: Replace soc_ prefix with fsp_Lee Leahy
Rename soc_display_upd_value to fsp_display_upd_value since the routine was moved from src/soc/intel/common into src/drivers/intel/fsp1_1. BRANCH=none BUG=None TEST=Build and run on Kunimitsu Change-Id: Ifadf9dcdf8c81f8de961e074226c349fb9634792 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 95238782702999a178989467694ac1f15c079615 Original-Change-Id: Ibd26ea41bd5c7a54ecd3c237f7fb7bad6dbf7d8a Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/306351 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12157 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-10-27FSP 1.1: Move common FSP codeLee Leahy
Move the FSP common code from the src/soc/intel/common directory into the src/drivers/intel/fsp1_1 directory. Rename the Kconfig values associated with this common code. BRANCH=none BUG=None TEST=Build and run on kunimitsu Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440 Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/306350 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12156 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-10-27intel/kunimitsu FAB3: Configure LPC to Quiet Mode.pchandri
This patch configures the LPC to quiet mode and sets enables CLKRUN so that LPC can be power gated. BUG=chrome-os-partner:44993 BRANCH=none TEST=Builds and Boots on fab3 kunimitsu. Change-Id: I46ff21f75b70f54da3f12dcc56d61f84b436cd7d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: edd37df385bc013b62f26435267291acc0a9b9a4 Original-Change-Id: Ide0f9e91127aebb8ac027ee0a598608b50aa4278 Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/305396 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com> Reviewed-on: http://review.coreboot.org/12153 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27intel/skylake: IRQ programming through UPDSubrata Banik
Implemented Device IRQ porgramming, PxRC to IRQ mapping, GPIO IRQ routing, SCI IRQ select through UPD BUG=NONE BRANCH=NONE CQ-DEPEND=CL:*232948 TEST= build and booted sklrvp,kunimitsu with this changes. Change-Id: Ic98074491fe5251a48ed55b6fb7ef31809c3abf3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 534bd65e5df8654d745c8efe491a332336c9cdc3 Original-Change-Id: I4ea6f3cdb15d371c6023bfd046f3475290f5aa26 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291403 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12146 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27intel/skylake: FSP 1.7.0 MemoryInit/SiliconInit params updateRizwan Qureshi
In FSP 1.7.0 SataMode and SataEnable have been moved from MemoryInit to SiliconInit. Also, GpioTablePtr has been removed. USB phy settings added to SiliconInit, Enable the configs for USB equalization settings in coreboot. Addition of serialIO UPD to indicate FSP not to reinitialise UART2 controller during MemoryInit. BRANCH=none BUG=chrome-os-partner:45684, chrome-os-partner:42284, chrome-os-partner:41374 TEST=build for Kunimitsu, boot on FAB3, Also checked for Boot from USB, Boot from eMMC, USB Audio, Onboard Audio, Touch, Wifi, S3 entry/resume CQ-DEPEND=CL:*232947, CL:*232946, CL:*232948, CL:*232949 Change-Id: I2e8e6e32fc7074774ddcf1fb4c270bb56372b7df Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 623c5a52f3afedaf2c0bfe7361cfd627d093cb73 Original-Change-Id: I8b3be2c49893c564fe2197aa32bde6323bf425e9 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303661 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12144 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27intel/kunimitsu Fab3: Strengthening Rcomp target CTRL valuepchandri
This patch strengthens the Rcomp Target CTRL by 10% for 8GB memory part K4E6E304EE-EGCF as with the current values the MRC training is failing due to more load on CS# BRANCH=None BUG=chrome-os-partner:44647 TEST=BUilds and boots on Kunimitsu. Change-Id: I478002bbebabaac418356d4b5b4755bb56009268 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b208659e690d8cb5b8dcaf30eed53c01b9f77f6d Original-Change-Id: Ia0a0c1358649af77a3a0d301cb791f26f1e039bf Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/304103 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com> Reviewed-on: http://review.coreboot.org/12143 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27intel/skylake: Add support for Gfx PEIM (AKA GOP)robbie zhang
This patch implements the igd_opregion using the write_acpi_tables mechanism to support GOP usage. BRANCH=none BUG=chrome-os-partner:44559 TEST=W/o GOP_SUPPORT in config, Built and boot on kunimitsu/glados. W/ GOP_SUPPORT enabled, build and boot on kunimitsu/glados, but on glados Dev screen can not be seen (OS display is fine). CQ-DEPEND=CL:303539 Change-Id: I4cd63dfe0d3f456c5f084e38db976425143f79e7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4db57463a69c6114b1e2ed4035d378ee3a82783f Original-Change-Id: I6f3c29c1b608eeaad8f2bf79d17394d49f8e412c Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303387 Original-Commit-Ready: Robbie Zhang <robbie.zhang@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12142 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27fsp/intel common: Add support for Gfx PEIM (AKA GOP)robbie zhang
This patch provides the lb_framebuffer() for coreboot table with fsp gop usage, add Igd Opregion register defines, and update the UPD naming following fsp. BRANCH=none BUG=chrome-os-partner:44559 TEST=Built and boot on kunimitsu/glados. Change-Id: I9cf9d991eb09d698e7a78323cd855c4c99b55eca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cd6834057cca60716bc0e24cfc2cd60fed02be7a Original-Change-Id: I64987e393c39a7cc1084edf59e7ca51b8c5ea743 Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303539 Original-Commit-Ready: Robbie Zhang <robbie.zhang@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12141 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-23Intel: Move MCRS ResourceTemplate outside of _CRS methodMartin Roth
On Broadwell, this reduces the number of 'remarks' in the IASL build from 222 to 3. Fixes these remarks: Object is not referenced (Name is within method [_CRS]) The ACPI compiler is trying to be helpful in letting us know that we're not using various fields in the MCRS ResourceTemplate when we define it inside of the _CRS method. Since we're not intending to use those objects in the method, it shouldn't be an issue, but the warning is annoying and can mask real issues. Moving the creation of the MCRS object to outside of the CRS method and referencing it from there solves this problem. This change was made for fsp_baytrail in commit 2eaa0d49 fsp_baytrail: Fix ACPI 'Object is not referenced' warnings Change-Id: I67a1faf963d1868f4133c7747a43a511cd28a44b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11268 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23intel/fsp_baytrail: Fix logging of ISPEnable optionDavid Imhoff
Before this fix the value of PcdEnableSdio was printed as the MIPI/ISP configuration option. TEST=Built and booted on Minnowboard Max Change-Id: Ia9b02d520f4e615f90b45935456b9d97c5d00f11 Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl> Reviewed-on: http://review.coreboot.org/10126 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-10-15soc/intel/broadwell: fix USBDEBUG copy-pastaGeorg Wicherski
The broadwell soc code was upstreamed based off an old coreboot branch and apparently never tested with USBDEBUG. This changeset fixes USBDEBUG on the not yet upstreamed Auron-Paine board, as verified with a FT232H setup. The fix is simply removing outdated code that since branching off had been deduplicated in upstream coreboot, anyway. Change-Id: I53c924aa2a5357ed8313d0c9eaa2f9f9e132345e Signed-off-by: Georg Wicherski <gwicherski@gmail.com> Reviewed-on: http://review.coreboot.org/11874 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-15cpu/mtrr.h: Fix macro names for MTRR registersAlexandru Gagniuc
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR, we also remove the _MSR suffix, as they are, by definition, MSRs. Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11761 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-14skylake: ACPI: Fix compiler warnings with iasl-20150717Duncan Laurie
Updating to a new IASL introduces a lot of warnings that are not serious issues but can be fixed with some reworks. - Method local variables that are set but never used now warn, when needing to read back a register the ordering is now changed to set the value in Local0 first so the compiler does not complain. - Methods that create an object must be serialized - A ResourceTemplate declared inside a _CRS with a named variable does not seem to be able to compile without a warning. To fix this move the ResourceTemplate outside the _CRS method. - The DPTF CPU code was still using the old legacy \_PR.CPUx instead of the new \_PR.CPxx definitions. BUG=chrome-os-partner:44622 BRANCH=none TEST=build glados with iasl-20150717 and see no warnings Original-Change-Id: I4a66c7eb6495aac4ae1aa42100c846725c1a04d2 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302168 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia3af802ca2faab4f1c59e73f2ce31a65c7e862e0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11812 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com>
2015-10-11skylake: add support for verstageAaron Durbin
The right files just need to be added to the verstage build. Do that so a stand alone verstage builds and links. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I2d0c98760494e2f4657ee35b6f155690939d2d18 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11827 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11soc/intel/common: use prog_locate() for finding fsp.binAaron Durbin
The current method was only taking the cbfs path. Because of this fsp.bin was never being utilized from the RW slots. Using prog_locate() now provides both the cbfs and vboot locate methods for free. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: I2b3e088326d5a965ad90806a7950b9f401ed57de Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11831 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-11skylake: Leave SPI controller enabledLee Leahy
Leave the SPI controller enabled upon boot block exit. BRANCH=none BUG=chrome-os-partner:44827 TEST=Build and run on kunimitsu Change-Id: I5b10d7cc8d5d350282206abe6a945bab66f97ada Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: http://review.coreboot.org/11825 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11skylake: SPI code cleanupLee Leahy
Move base address into iomap.h. Use PCI symbols instead of SPI specific symbols. Fix comments. BRANCH=none BUG=chrome-os-partner:44827 TEST=Build and run on kunimitsu Change-Id: Id5d21603150b52fd1b71dd448105938bd6aff1a9 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: http://review.coreboot.org/11826 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11intel fsp1_1: prepare for romstage vboot verification splitAaron Durbin
In order to introduce a verstage which performs vboot verification the cache-as-ram environment needs to be generalized and split into pieces that can be utilized in romstage and/or verstage. Therefore, the romstage pieces were removed from the cache-as-ram specific pieces that are generic: - Add fsp/car.h to house the declarations for functions in the cache-as-ram environment - Only have cache_as_ram_params which are isolated form the cache-as-ram environment aside from FSP_INFO_HEADER. - Hardware requirements for console initialization is done in the cache-as-ram specific files. - Provide after_raminit.S which can be included from a romstage separated from cache-as-ram as well as one that is tightly coupled to the cache-as-ram environment. - Update the fallout from the API changes in soc/intel/{braswell,common,skylake}. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302481 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11816 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11soc/intel/common: remove chipset specific callsAaron Durbin
The report_platform_info() and set_max_freq() are not being used similarly on skylake and braswell. With the addition of other SoCs I suspect a similar pattern will emerge. Instead of having weak functions to ensure things link with the hardcoded policy push these calls into their respective SoC homes. For parity, both skylake and braswell were updated to be consistent with the same calls prior to this patch. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Built braswell. Original-Change-Id: I3371d09aff0629503254296955fef28d35754a38 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/303334 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I2de33632ed127cac52d7075cbad95cd6387a1b46 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11815 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11intel SOC common: Remove unused parametersLee Leahy
Eliminate unused parameters from the console initialization. BRANCH=none BUG=chrome-os-partner:44827 TEST=Build and run on kunimitsu Original-Change-Id: Iacacea292d43615e9d2f8e5d3ec67e77f3f08906 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/301204 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Change-Id: I3a0ea948ce106b07cb6aa872375ce588317dc437 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11814 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11Braswell: Modify CB to accomodate new FSPv83Subrata Banik
Latest FSPv83 made some change related to UPD/VPD need this patch to align those BUG=None TEST=Build and Boot Cyan System BRANCH=strago-7287.B CQ-DEPEND=CL:*226897 Original-Change-Id: I6395f3a1f4eecaef14fc4720b00252f9e6143fa3 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291394 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Hannah Williams <hannah.williams@intel.com> Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303137 Original-Commit-Ready: John Zhao <john.zhao@intel.com> Original-Tested-by: John Zhao <john.zhao@intel.com> Change-Id: I9920eea84b802699454850bfde489668201ffeb6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11813 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11Skylake: remove the out-dated VR config and un-needed 24mhz calibrationrobbie zhang
On Skylake, mailbox interface is used to configure VRs, dropping direct msr writing. With current fsp, svid/vr programming seems to be functional - no errors are given in the svid transactions in boot, and hw engineer verified the VRs on Kunimitsu. Additional tunnings might be needed later with power testing. 24mhz calibration is no longer needed on Skylake due to bclk archtecture change. BRANCH=none BUG=chrome-os-partner:45387 TEST=Built and boot on kunimitsu/glados, reboot, S3/resume verified. Signed-off-by: robbie zhang <robbie.zhang@intel.com> Original-Change-Id: If99b5758fcdba8604139c761a07403d4a5d2eb4c Original-Reviewed-on: https://chromium-review.googlesource.com/301470 Original-Commit-Ready: Robbie Zhang <robbie.zhang@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Original-Tested-by: Wenkai Du <wenkai.du@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I98acf78aac9c705614fb200f8c3313a89296fbf2 Signed-off-by: robbie zhang <robbie.zhang@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11811 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-11skylake: ajdust cache-as-ram region to 64KiBAaron Durbin
FSP is actually providing 64KiB to the bootloader. Expand current footprint to match reality. BUG=chrome-os-partner:44676 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Ibff243036eb4a6b9b9f331665a7e3efa1853bc91 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/300191 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Change-Id: Ibb876f49c3e5d8d1a3b8f6f74ed12a19663e4145 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11810 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-10-11intel: update common and FSP cache-as-ram parametersAaron Durbin
Instead of just passing bits, tsc_low, tsc_high, and an opaque pointer to chipset context those fields are bundled into a cache_as_ram_params struct. Additionally, a new struct fsp_car_context is created to hold the FSP information. These could be combined as the existing romstage code assumes what the chipset_context values are, but I'm leaving the concept of "common" alone for the time being. While working in that area the ABI between assembly and C code has changed to just pass a single pointer to cache_as_ram_params struct. Lastly, validate the bootloader cache-as-ram region with the Kconfig options. BUG=chrome-os-partner:44676 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Ib2a0e38477ef7c15cff1836836cfb55e5dc8a58e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/300190 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Change-Id: Ic5a0daa4e2fe5eda0c4d2a45d86baf14ff7b2c6c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11809 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-07cbfs: add struct cbfsfAaron Durbin
Now that cbfs is adding more metadata in the cbfs file header one needs to access that metadata. Therefore, add struct cbfsf which tracks the metadata and data of the file separately. Note that stage and payload metadata specific to itself is still contained within the 'data' portion of a cbfs file. Update the cbfs API to use struct cbfsf. Additionally, remove struct cbfsd as there's nothing else associated with a cbfs region aside from offset and size which tracked by a region_device (thanks, CBFS_ALIGNMENT!). BUG=None BRANCH=None TEST=Built and booted through end of ramstage on qemu armv7. Built and booted glados using Chrome OS. Change-Id: I05486c6cf6cfcafa5c64b36324833b2374f763c2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11679 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-05Add EM100 'hyper term' spi console support in ramstage & smmMartin Roth
The EM100Pro allows the debug console to be sent over the SPI bus. This is not yet working in romstage due to the use of static variables in the SPI driver code. It is also not working on chipsets that have SPI write buffers of less than 10 characters due to the 9 byte command/header length specified by the EM100 protocol. While this currently works only with the EM100, it seems like it would be useful on any logic analyzer with SPI debug - just filter on command bytes of 0x11. Change-Id: Icd42ccd96cab0a10a4e70f4b02ecf9de8169564b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11743 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-04drivers/uart/Kconfig: Select 8250 mem when 8250 mem32 is enabledAlexandru Gagniuc
Users of DRIVERS_UART_8250MEM_32 would have to also select DRIVERS_UART_8250MEM to avoid missing Kconfig dependencies. Instead, do what the OXPCIE driver dies and select the appropriate options. Change-Id: I40d93df024fcb3a9ad6dc51d6a5966e7b1b6c07f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11786 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-29 06:45:22 +0000