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2014-12-02Replace hlt with halt()Patrick Georgi
There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-12-01Mark non-executable files non-executablePatrick Georgi
No need to mark Makefiles, C files or devicetrees executable. Change-Id: Ide3a0efc5b14f2cbd7e2a65c541b52491575bb78 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7618 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-30Replace hlt() loops with halt()Patrick Georgi
Change-Id: I8486e70615f4c404a342cb86963b5357a934c41d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-28ACPI: Remove CBMEM TOC from GNVSKyösti Mälkki
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM. See commit a0b4a8d. Change-Id: Iae82498ab729df5682d89e66bb9de96457e91619 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7465 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-11-25intel: Remove IRQ1 from possible PIRQ assignemnt.Vladimir Serbinenko
According to spec IRQ1 isn't available for PIRQ assignment. Has gone unnoticed probably because modern OS use MSI or at least APIC and even with noapic don't use IRQ1 with PCI IRQs. Change-Id: Idc7db249007df629b27e8cae41cc80358d5306f6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7478 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-11-24intel/fsp_baytrail: add new CPUID for Baytrail I step D0Herve ELter
Change-Id: I9e29ca10689cbbbaba593185868e54b8697aa9c4 Signed-off-by: Herve Elter <rvnvv74@gmail.com> Reviewed-on: http://review.coreboot.org/7523 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Tested-by: build bot (Jenkins)
2014-11-21intel/fsp_baytrail: add Gold3 FSP supportYork Yang
Baytrail Gold3 FSP adds a couple of parameters in UPD_DATA_REGION making platform more configurable via devicetree.cb Update the UPD_DATA_REGION structure and pass settings to FSP Add Baytrail Gold2 and earlier FSP backward compatible, as Gold3 FSP changes UPD_DATA_REGION struct Change-Id: Ia2d2d0595328ac771762a84da40697a3b7e900c6 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/7334 Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins)
2014-11-20Replace includes of build.h with version.hKyösti Mälkki
As build.h is an auto-generated file it was necessary to add it as an explicit prerequisite in the Makefiles. When this was forgotten abuild would sometimes fail with following error: fatal error: build.h: No such file or directory Fix this error by compiling version.c into all stages. Change-Id: I342f341077cc7496aed279b00baaa957aa2af0db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7510 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-19broadwell: move to per-device ACPI.Vladimir Serbinenko
Change-Id: Icc4691f260521e7f3cc9388210c9b7631cf7ce18 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7363 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-19fsp_baytrail: Fix ACPI 'Object is not referenced' warningsMartin Roth
The ACPI compiler is trying to be helpful in letting us know that we're not using various fields in the MCRS 'ResourceTemplate' when we define it inside of the _CRS method. Since we're not intending to use those objects in the method, it shouldn't be an issue, but the warning is annoying. Moving the creation of the MCRS object to outside of the _CRS method and referencing it from there solves this problem. Change-Id: I222642e9a93f3078b46ed74f57b83a5834657abf Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7499 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-19fsp_baytrail: Update chip.h UPD entries to match names in fspvpd.hMartin Roth
The entries in chip.h are used to set the UPD values. These had originally been shortened and did not match the names of the structure entries in vendorcode/intel/fsp/baytrail/include/fspvpd.h This patch aligns the names. - Update names in chip.h. - Update names in devictree registers for bayley bay and minnow max. - Update names in chipset_fsp_util.c Change-Id: I8d7e34195cec2e63802d7e07e5aed71735556936 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/7486 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: FEI WANG <wangfei.jimei@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-18baytrail: fix range checkPatrick Georgi
Change-Id: I59d42cd451997e141e02d99a62b84a7a2201eb31 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7500 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-11-13intel: use crosscompiler readelf, instead of globalPatrick Georgi
readelf(1) may not know about the i386 flavor, or not be present at all under this name. Change-Id: I285df1f2098200b89918a4c4d3610e6427e86e01 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7448 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-09src: Too many terminators ';;' at end of stmts, stop SkynetEdward O'Callaghan
Change-Id: I3e9b7e0e5558a6942067dcea04b83fe3bccbbaf9 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-11-08intel: Use 'FORCEWAKE_ACK_HSW' define over '0x130044'Edward O'Callaghan
Change-Id: I1cf87b3c73d8bf8846e5870b19b089f85c299567 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7241 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-11-04Redundant addr '&' operator on func ptr's in struct initiatorEdward O'Callaghan
Bring code inline to be consistent with the rest of coreboot. See standard - c99std (n1256) 6.3.2.1p4 - to paraphrase, 'expressions that refer to functions get converted to pointers to those functions' Change-Id: I63a7bed5efade37dd7076dbfc9c85d420cf6c92b Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7290 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-11-01{cpu,soc}: Use DEVICE_NOOP macro over dummy symbolEdward O'Callaghan
Change-Id: Iaf2b2873bd1c52d7f936bd9b483e194a0872a626 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/7285 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2014-10-28baytrail: Remove unused devicetree fieldsShawn Nematbakhsh
We're no longer configuring hotplug + backlight settings from devicetree, so remove these entries + fields. BUG=chrome-os-partner:27304 TEST=Compile only. BRANCH=rambi+squawks Change-Id: I7e27fbc070a9ea774e7dcbe551d61b1b1682a47f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193831 (cherry picked from commit 4ab13fd3aa2634673bb099bdfd714a21adc3caa0) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7218 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-10-28baytrail: gfx: Don't configure hotplug + backlight registersShawn Nematbakhsh
- The hotplug register doesn't work in the way we describe. Just leave it at default. - The backlight registers will be configured by the OS driver. BUG=chrome-os-partner:27304 TEST=Manual on Rambi. Boot system in both dev and normal mode, verify that display comes up. Also verify that display functions after warm reboot and suspend / resume. BRANCH=rambi+squawks Change-Id: I5559c131f41c4a14e64e5cec66e18d3a4a46092c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193830 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3f287cc31e41fabef755c37361e2e65ca413c88c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7217 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-28Baytrail/dptf: Always return 0 in TCPU._PPCKein Yuan
According to DPTF team _PPC in TCPU must return 0 always. BUG=chromium:355964 TEST=Pass build. BRANCH=rambi Change-Id: I76f0da27757ba4717f0e392bcd80e890d925061a Original-Change-Id: I8b9e17e5479e8a226cb11cd43ce888a3e4dead73 Signed-off-by: Kein Yuan <kein.yuan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/193069 Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 6dbcc677ceebbaf832e41e6db1e6cf171e2e231f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-28baytrail: handle MRC being an ELF fileAaron Durbin
Provide the option to embed MRC as an ELF file and not just binary blob. This allows for MRC to be relocated. BUG=chrome-os-partner:27654 BRANCH=rambi TEST=Built and booted rambi. Change-Id: I2e177c155a3074e4e1d450b1a73b7299aebd5286 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/192893 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 89c97d5e2023b8c5cc780e1b1d532d0a586512f9) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7214 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-10-28baytrail: Configure MSR for 2-core and 4-core P-state configutationDuncan Laurie
Suggested settings to try for performace regression: 2-core systems: - MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL) - MSR_POWER_MISC clear bit 2,3 - \_PR.CPUx._PSD coordination set to 0xFE (HW_ALL) 4-core systems: - MSR_PMG_CST_CONFIG_CONTROL clear bit 11 (SINGLE_PCTL) - MSR_POWER_MISC clear bit 2,3 - \_PR.CPUx._PSD coordination set to 0xFC (SW_ALL) BUG=chrome-os-partner:26211 BRANCH=baytrail TEST=emerge-rambi chromeos-coreboot-rambi Change-Id: Ib68a86525204ae47a820c269257a7b8df9300a6a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/192573 Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 8c8c0be0000043610eaa56926eff978f352819b8) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7213 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-28baytrail: move cache-as-ram base address to 0xfe000000Aaron Durbin
Moving the cache-as-ram base address to 0xfe000000 will provide more breathing room in the physical address space. It will also allow for larger SPI roms in the future. BUG=chrome-os-partner:27045 BRANCH=baytrail CQ-DEPEND=CL:*157278 TEST=Built and booted. Suspended and resumes. Vboot works, MRC settings are being saved as well. Change-Id: I618c069e504f545e02de5ac54e057566f0b5d6c9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/190700 Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 73c07a319d678f3e9be2fac64599c94f91c9ad9c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7212 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-28baytrail: romstage: Add function to check SW WP status for vbootShawn Nematbakhsh
Implement vboot_get_sw_write_protect, which returns the FW SPI ROM SW WP status. BUG=chrome-os-partner:26777 TEST=Manual on Rambi with all patches in sequence: `crossystem sw_wpsw_boot` prints 0 `flashrom --wp-enable` + reboot `crossystem sw_wpsw_boot` prints 1 BRANCH=Rambi Original-Change-Id: I5da35c1b2d25b8679bf0084af65d08de224387f8 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/190097 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5bba447654417c42952c49542ed047b4867d04d1) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I739cbb8fca5f02462cf78c81f9b364aabfd3fe86 Reviewed-on: http://review.coreboot.org/7211 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-22reg_script: default to n for ARCH_X86Isaac Christensen
The reg_script functionality is only used by specific chipsets so have it selected instead of defaulting to y for ARCH_X86. Change-Id: I8fb9466e148eed7896ca8ed80755c77ba1190583 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7006 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-22cmos: Rename the CMOS related functions.Gabe Black
Most of the code related to the mc146818 is not related to the RTC and is really for managing the CMOS storage. Since we intend to add a generic API for RTC drivers it's inconvenient for those functions to have an rtc_ prefix. This CL renames those functions so they start with cmos_ instead. There are some places where rtc_init was called with a comment that says something about starting the RTC. That wasn't correct before (the RTC is always running), but it looks a little odd now that the function is called cmos_init. This CL also opportunistically cleans up some style problems in this file. Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/197794 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 9a9ad24888b185fb58965457704e326bb508d788) Removed the addition of stdint.h to mc146818rtc.h since types.h is now included. Changed rtc_init to cmos_init for fsp_bd82x6x, fsp_rangeley, fsp_baytrail, ibexpeak, vortex86ex. Change-Id: Id4b9f6bea93e8bd5eaef2cb17f296adb9697114c Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6977 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-22broadwell: Update Haswell and Broadwell E0 microcodeDuncan Laurie
Broadwell D0 updated to 0x10 (debug) Broadwell E0 updated to 0xD Haswell updated to 0x1C Change-Id: Ib3e27b3467fec1106c69d82c0b1522d58025d67e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/208212 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 048a8b68dbc79dd27dc3188dde407a95c4d729fc) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6984 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-10-22broadwell: Update microcodeDuncan Laurie
40651: rev 00000018 306D3: rev FFFF000F 306D4: rev 00000009 Change-Id: I47a6caadc83f0ed96b0a4b0c624ad105d9dee3b6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/204819 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit f8f0703c7042a14c6807cbea74eae6e85ba6854e) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6983 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22broadwell: ACPI, romstage, and other updatesDuncan Laurie
broadwell: Add romstage usbdebug support Reviewed-on: https://chromium-review.googlesource.com/199412 (cherry picked from commit 1050e7d3be6ec1e4fe5aa2df408f4bb6d33a42b5) broadwell: Add romstage code to configure PCH UART for console Reviewed-on: https://chromium-review.googlesource.com/199807 (cherry picked from commit ecebda4eb5d6fe58473d25c2898ba1a2eac0f39a) broadwell: Expand the PCI device convenience macros Reviewed-on: https://chromium-review.googlesource.com/199891 (cherry picked from commit f8c54c70f136cd2cb8f977bc25661974d7e529ad) broadwell: Add ramstage driver for ADSP Reviewed-on: https://chromium-review.googlesource.com/199892 (cherry picked from commit e8e986b0ba52bbfc9923d71009fbd31e749ca43f) broadwell: Update ACPI devices Reviewed-on: https://chromium-review.googlesource.com/201080 (cherry picked from commit 2446b35578eb36e0009415bec340059135751549) broadwell: Reserve DPR region Reviewed-on: https://chromium-review.googlesource.com/201081 (cherry picked from commit 8ecd9d2096db2bded6f27ef6ee9a9b39ce2dfec6) broadwell: Remove old pei_data and add cpu function for romstage Reviewed-on: https://chromium-review.googlesource.com/201690 (cherry picked from commit d206c9cdd69519d502a90bb0595f0e3a7cb50274) broadwell: Fixes for graphics without executing VBIOS Reviewed-on: https://chromium-review.googlesource.com/202356 (cherry picked from commit 0c031df1ce92c875e95ddfd3f026f649c342c7fa) broadwell: Fix compilation failure when loglevel is lowered Reviewed-on: https://chromium-review.googlesource.com/202357 (cherry picked from commit 708ce78b2bfae5664b1238e17b086c88cac55bdc) broadwell: Disable GPIO controller interrupt Reviewed-on: https://chromium-review.googlesource.com/203645 (cherry picked from commit 2d17e98eded5958258ba5c0abf600284d8d03af9) broadwell: Add support for E0 stepping Reviewed-on: https://chromium-review.googlesource.com/205160 (cherry picked from commit 802e9d371418cc7a7fc7af131d7e5dda0ae5b273) broadwell: misc updates for CPU driver Reviewed-on: https://chromium-review.googlesource.com/205161 (cherry picked from commit ea1d403817ee193648f2c119fd45894e32e57e97) broadwell: Read power state earlier and store in romstage params Reviewed-on: https://chromium-review.googlesource.com/208151 (cherry picked from commit b2198d71084ad3c1360a0bfedc46c8dd3825bd0e) broadwell: Add parameters to pei_data structure Reviewed-on: https://chromium-review.googlesource.com/208153 (cherry picked from commit 423fbf67e497a907fbc8e12caf2929d4951858af) broadwell: Move platform report output after power state is read Reviewed-on: https://chromium-review.googlesource.com/208213 (cherry picked from commit acedf4146bf9377133433046dae1fa9c8bc69d78) Squashed 15 commits for broadwell support. Change-Id: I87e320d3d5376b84dd9c146b0b833e5ce53244aa Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6982 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22broadwell: Update D0 microcode to FFFF000EDuncan Laurie
New microcode released this week. Change-Id: I426d0e00d1c03650049cbe033b53a909a7d944c9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198896 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 63ec6438b566d14a2b878474ca068cf70d9aa9d6) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6966 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22broadwell: Update microcode for supported CPUsDuncan Laurie
This broadwell implementation will support Haswell ULT in addition to broadwell CPUs. Add the latest available microcode for the broadwell C0 and D0 parts as well as Haswell ULT. Change-Id: I1beb71e0e28af3508e2260751b6fdfe47d53d90d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198742 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 69d5b7c834a4f52656ab14562ea913477418e588) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6965 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22broadwell: add new intel SOCDuncan Laurie
broadwell: Import files from haswell/lynxpoint into soc/broadwell Reviewed-on: https://chromium-review.googlesource.com/198425 (cherry picked from commit 178400e5709d676dd41e6a75df06faa829e0e3af) broadwell: Unify and clean up license Reviewed-on: https://chromium-review.googlesource.com/198426 (cherry picked from commit 30d3c25a0abc76be68477c39a654b95a5975f55d) broadwell: pch.h: split PM into new header Reviewed-on: https://chromium-review.googlesource.com/198427 (cherry picked from commit 97a8d0b051f476d0edc06301f57326a718df1373) broadwell: pch.h: split RCBA into new header Reviewed-on: https://chromium-review.googlesource.com/198428 (cherry picked from commit fa217361b28fdb8d3a3e85f070dfaf13c0d48135) broadwell: pch.h: split SATA into new header Reviewed-on: https://chromium-review.googlesource.com/198429 (cherry picked from commit bf8795ca92f9f0467e7869c701038abb4529ac71) broadwell: pch.h: split SPI into new header Reviewed-on: https://chromium-review.googlesource.com/198550 (cherry picked from commit 099af14676a2654ca3e24e66d7b9f0b4ab13cd14) broadwell: pch.h: split SerialIO into new header Reviewed-on: https://chromium-review.googlesource.com/198551 (cherry picked from commit 4f3c028686aed78fb07b8792dcf46aebd2268ea6) broadwell: pch.h: split LPC into new header Reviewed-on: https://chromium-review.googlesource.com/198552 (cherry picked from commit 10bad5bbb6739c0277fd5330d26a89d60fd5c102) broadwell: pch.h: split GPIO into new header and clean up Reviewed-on: https://chromium-review.googlesource.com/198553 (cherry picked from commit 9c97532460562215b78e10b011a29e092a07f3e5) broadwell: pch.h: split USB into new headers Reviewed-on: https://chromium-review.googlesource.com/198554 (cherry picked from commit 86ef1a45a2e5f307467b3be48e377569f37b3068) broadwell: Split IOBP into separate files Reviewed-on: https://chromium-review.googlesource.com/198734 (cherry picked from commit f93b8bda71728f1383937ad675d2d5fb5a927600) broadwell: smbus: Extract common code and split header Reviewed-on: https://chromium-review.googlesource.com/198735 (cherry picked from commit 8052030a9d6b22e8a19938fa9b93e90d08f0057d) broadwell: Create iomap.h header with platform base addresses Reviewed-on: https://chromium-review.googlesource.com/198736 (cherry picked from commit b35947d070b28871637dfe2b930a9f2be80958ee) broadwell: Add header for platform PCI devices Reviewed-on: https://chromium-review.googlesource.com/198737 (cherry picked from commit 6ac4e56db6e489bb9eaf91a0c3c543399f691500) broadwell: Split SMM related defines/prototypes to new header Reviewed-on: https://chromium-review.googlesource.com/198738 (cherry picked from commit 2a2595067077cd918bfd48cad79a684b8e1ff0f4) broadwell: cpu.h: Split MSR defines to separate header Reviewed-on: https://chromium-review.googlesource.com/198739 (cherry picked from commit 01148cd2c9edd97cd0c8ef3cfed58bc8c33eb805) broadwell: Create romstage header file Reviewed-on: https://chromium-review.googlesource.com/198740 (cherry picked from commit 31c91e811b9e07e7bcba6b9f8f5720a31322eb21) broadwell: Create ram stage header file Reviewed-on: https://chromium-review.googlesource.com/198741 (cherry picked from commit 93dde85f98d43d4a1886b59004d1bab4924ad621) broadwell: Add reference code data interface Reviewed-on: https://chromium-review.googlesource.com/198743 (cherry picked from commit 9059b8e2308892a48c838c3099404c9cf450df95) broadwell: Clean up ACPI NVS region Reviewed-on: https://chromium-review.googlesource.com/198897 (cherry picked from commit d83cc82c36661556eb1e2e437b7ac51d5b8e4a14) broadwell: Move CTDP ACPI methods to new file Reviewed-on: https://chromium-review.googlesource.com/198898 (cherry picked from commit fc1e711290df304d18c558d697eea8a5e57061b2) broadwell: Split EHCI and XHCI ACPI devices Reviewed-on: https://chromium-review.googlesource.com/198899 (cherry picked from commit 26f437b27e00dbd5c92ea22e76404633a62fb7ca) broadwell: ACPI: Clean up SerialIO ACPI code Reviewed-on: https://chromium-review.googlesource.com/198910 (cherry picked from commit ea3cd39566c1bb2ead463a6253b6204a62545d35) broadwell: ACPI: Remove special handling of LPT-LP chipset Reviewed-on: https://chromium-review.googlesource.com/198911 (cherry picked from commit 2c54df159bf6759c8f866628e83541de6f4e28f6) broadwell: ACPI: Clean up use of base address defines Reviewed-on: https://chromium-review.googlesource.com/198912 (cherry picked from commit 34e4788955bceff01631fd0b4dbf0aa24cf56b75) broadwell: ACPI: Clean up and fix formatting Reviewed-on: https://chromium-review.googlesource.com/198913 (cherry picked from commit bc0f7c6d2f95681eb987bb6ff6baf2d16cc77050) broadwell: Add header for ACPI defines and prototypes Reviewed-on: https://chromium-review.googlesource.com/198914 (cherry picked from commit 9951e7931942d2921f92f6e094b1cc32c190eab9) broadwell: Add reset_system function and header Reviewed-on: https://chromium-review.googlesource.com/198915 (cherry picked from commit 6d1efb94bd39bcd6f7e3e0de2f3299a384b109ef) broadwell: Move PCODE MMIO defines to systemagent.h Reviewed-on: https://chromium-review.googlesource.com/198916 (cherry picked from commit abb5f87e548fbde3a08e14a18714b4e4391c955f) broadwell: Unify chip.h and add chip.c Reviewed-on: https://chromium-review.googlesource.com/198917 (cherry picked from commit a9c2d7ff3afa1e2a10be85ccc72b7db0f2aaafe1) broadwell: Rename HASWELL_BCLK to CPU_BCLK Reviewed-on: https://chromium-review.googlesource.com/198918 (cherry picked from commit 65ac1a07abaf14eb42fec6c5df67d2d3688ad5a1) broadwell: Clean up broadwell/cpu.h Reviewed-on: https://chromium-review.googlesource.com/198919 (cherry picked from commit 17353803babc8ace279e105c012130678226144e) broadwell: Clean up broadwell/systemagent.h Reviewed-on: https://chromium-review.googlesource.com/198920 (cherry picked from commit 49d7a023f3ff04a65d16622aa9b2fa6004b693ae) broadwell: Clean up broadwell/pch.h Reviewed-on: https://chromium-review.googlesource.com/198921 (cherry picked from commit 17da652b4408a91fcfea99dd35fe9f9e1bdcf03b) broadwell: Clean up management engine driver Reviewed-on: https://chromium-review.googlesource.com/198922 (cherry picked from commit 4fce5fbb56dc4f31b77e5ada05463c043ad5be72) broadwell: Add common CPUID and PCI Device ID defines Reviewed-on: https://chromium-review.googlesource.com/198923 (cherry picked from commit c6bf20309f33168ea2cc4634cbda5ec242824ba8) broadwell: Clean up and expand report_platform Reviewed-on: https://chromium-review.googlesource.com/198924 (cherry picked from commit 5082d4824db149e867a2cd8be34c932b03754022) broadwell: Clean up the bootblock code Reviewed-on: https://chromium-review.googlesource.com/198925 (cherry picked from commit ba0206ab76fe0b6834a14dc57f400d139094623c) broadwell: Clean up ramstage device and driver operations Reviewed-on: https://chromium-review.googlesource.com/199180 (cherry picked from commit d8fc9daf129738713a5059286b7ead004f3b7569) broadwell: Clean up XHCI and EHCI ramstage drivers Reviewed-on: https://chromium-review.googlesource.com/199181 (cherry picked from commit d355247333a828a146ce7cf9b92a63da74119c1d) broadwell: Clean up gpio handling code Reviewed-on: https://chromium-review.googlesource.com/199182 (cherry picked from commit d62cef1970fe75f8166315016b3d8415cddcab20) broadwell: Clean up the PCH generic code Reviewed-on: https://chromium-review.googlesource.com/199183 (cherry picked from commit 3b93b3ea79965d5ac831bf9015e49330f157b0ff) broadwell: Move get_top_of_ram() and cbmem_top() to memmap.c Reviewed-on: https://chromium-review.googlesource.com/199184 (cherry picked from commit 68955ba4ff8b49ff466d7badaa934bd143026ba7) broadwell: Clean up pmutil.c Reviewed-on: https://chromium-review.googlesource.com/199185 (cherry picked from commit b6fb672ae879e17422f7449f70c3669055096f84) broadwell: pmutil: Add new acpi_sci_irq() function Reviewed-on: https://chromium-review.googlesource.com/199186 (cherry picked from commit 80ad8bb9bdc75f180e667861fed42a3844226bc5) broadwell: Clean up HDA ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199187 (cherry picked from commit b4962acd706eaa66c1c3ef4d22eba313642fbb2d) broadwell: Clean up cache_as_ram assembly Reviewed-on: https://chromium-review.googlesource.com/199188 (cherry picked from commit 8a457b82610b604ae7f69e2500815ce411c2d02d) broadwell: romstage: Separate stack helper functions Reviewed-on: https://chromium-review.googlesource.com/199189 (cherry picked from commit c220383c90466fc2dbf4b6107679b08ecb4aadad) broadwell: Add function to read WPSR from SPI Reviewed-on: https://chromium-review.googlesource.com/199190 (cherry picked from commit 935404da1157d606b913eff6c2635ae898e9980a) broadwell: Clean up SMBUS code in romstage and ramstage Reviewed-on: https://chromium-review.googlesource.com/199191 (cherry picked from commit 6ae9d93c1a6f14da6429a4e5b01619c9ccaefdaa) broadwell: SPI: Clean up romstage and ramstage code Reviewed-on: https://chromium-review.googlesource.com/199192 (cherry picked from commit 28ffd71a416aee2ab54bc5d782cfeef31d4d30bf) broadwell: Clean up PCIe root port ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199193 (cherry picked from commit 781f3a1b72c72f0bb05f5524edec471ad13ec90e) broadwell: Clean up minihd ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199194 (cherry picked from commit a52d275e41fdcbf9895d07350725609d9be1ff0e) broadwell: Update romstage main to follow baytrail format Reviewed-on: https://chromium-review.googlesource.com/199361 (cherry picked from commit 0678c739af84c871922ffba5594132b25e471ddd) broadwell: Add CPU set_max_freq function for romstage Reviewed-on: https://chromium-review.googlesource.com/199362 (cherry picked from commit 68b0122472af27f38502d42a8a6c80678ddbbba6) broadwell: romstage: Add chipset_power_state implementation Reviewed-on: https://chromium-review.googlesource.com/199363 (cherry picked from commit 761cec3b6bb9bde579c3214f3f1196f65700757c) broadwell: romstage: Convert systemagent init to reg_script Reviewed-on: https://chromium-review.googlesource.com/199364 (cherry picked from commit c2ea2d3a0c7555a353fb9a1d4a63e773ac8961b2) broadwell: romstage: Convert pch init to reg_script Reviewed-on: https://chromium-review.googlesource.com/199365 (cherry picked from commit 4383de5846e97ca5aee6dd210459d8dba0af981c) broadwell: elog: Use chipset_power_state for events Reviewed-on: https://chromium-review.googlesource.com/199366 (cherry picked from commit 0ef5961ebe3a7037d5fbe361fbc70a87ac2edad9) broadwell: Clean up SATA ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199367 (cherry picked from commit ffa5743f74551bd48aa7e5445ce7cd9dc7b07ce8) broadwell: Update ramstage graphics driver to support broadwell Reviewed-on: https://chromium-review.googlesource.com/199368 (cherry picked from commit bb01deb8bbed56f15e1143504e4cf012ecf5a281) broadwell: Update raminit to follow baytrail layout Reviewed-on: https://chromium-review.googlesource.com/199369 (cherry picked from commit 3f25c23dc58f85d2521916cd6edbe9deeeb8d523) broadwell: Update and unify the finalize steps Reviewed-on: https://chromium-review.googlesource.com/199390 (cherry picked from commit ddc4c116b42d38dfdfc45ef4388fbfab32ca48fa) broadwell: Clean up SMM code Reviewed-on: https://chromium-review.googlesource.com/199391 (cherry picked from commit 8295e56c9b643fd4b9267d70b5efd0cf94dd67dd) broadwell: Clean up LPC ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199392 (cherry picked from commit 28326aeaaf304c9262866588d91b79b37d1d9a2e) broadwell: Clean up systemagent ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199393 (cherry picked from commit 749988fff07eab8d2c9ebc731e3ed9e427b3f7b3) broadwell: Move C-state configuration information to acpi.c Reviewed-on: https://chromium-review.googlesource.com/199394 (cherry picked from commit 198a3cd5cbd009be406298cbb53163f075fe9990) broadwell: Clean up CPU ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199395 (cherry picked from commit 8159689bba479bab6fd2e949e3e1c3f817088969) broadwell: Do not reserve SMM relocation region Reviewed-on: https://chromium-review.googlesource.com/199402 (cherry picked from commit e2ab52340e3d3a97a3f8dbdad8fac9f7769d1b4c) broadwell: Add an early ramstage driver Reviewed-on: https://chromium-review.googlesource.com/199403 (cherry picked from commit c7a8c867101b49a7f9f17ec1a8777a8db145f3e3) broadwell: Support for second reference code binary Reviewed-on: https://chromium-review.googlesource.com/199404 (cherry picked from commit abb99b36e97c4f739b23abed6146fea370bbbec2) broadwell: Clean up serialio init code Reviewed-on: https://chromium-review.googlesource.com/199405 (cherry picked from commit e09a1f8520a7b72451a1e2068b200f7c5451f489) broadwell: acpi: Add function to fill out FADT Reviewed-on: https://chromium-review.googlesource.com/199406 (cherry picked from commit 7e58f43e46d4382cf4541057f81fe6be3e4d6e74) broadwell: Update C-state table creation Reviewed-on: https://chromium-review.googlesource.com/199407 (cherry picked from commit 68b1f70e32e1d0c6fc4332dce402ad78334e0063) broadwell: acpi: Clean up acpi table creation code Reviewed-on: https://chromium-review.googlesource.com/199408 (cherry picked from commit 49088b312b159bb17a9330eda6a88d6f324ea146) broadwell: acpi: Add ACPI table create helper functions Reviewed-on: https://chromium-review.googlesource.com/199409 (cherry picked from commit 344c3c511d0341457525ef4d6eb70201404fc62c) broadwell: Add soc/intel/broadwell Makefiles Reviewed-on: https://chromium-review.googlesource.com/199410 (cherry picked from commit ea8f97738eadd3b0b6a642754df7a7d22e547ffc) broadwell: Add Kconfig for broadwell soc Reviewed-on: https://chromium-review.googlesource.com/199411 (cherry picked from commit 8c99038a5c20812497619134c66d45bc4f21c8fe) Squashed 78 commits for broadwell that form a solid code base. Change-Id: I365ca9a45978b5e0cc5237f884e20a44f62a0e63 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6964 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22baytrail: Move HDA verb table to Intel SOC common directoryDuncan Laurie
This is common code for Intel SOC that can be shared. Change-Id: Ic703f36f56a8238d5cc1248b353d8c3a49827a9a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196264 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3a9057b9616c54a8404eee55511743d2492dbc28) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6968 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22baytrail: Move MRC cache code to a common directoryDuncan Laurie
This common code can be shared across Intel SOCs. Change-Id: Id9ec4ccd3fc81cbab19a7d7e13bfa3975d9802d0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196263 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit f9919e2551b02056b83918d2e7b515b25541c583) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6967 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-22baytrail/rambi: S3 support and other updatesKein Yuan
baytrail: Change all GPIO related pull resistors from 10K to 20K Reviewed-on: https://chromium-review.googlesource.com/187570 (cherry picked from commit 762e99861dd1ae61ddcf1ebdec8e698ede54405e) baytrail: workaround kernel using serial console on resume Reviewed-on: https://chromium-review.googlesource.com/188011 (cherry picked from commit b0da3bdb5b6b417ad6cab0084359d4eae1cb4469) baytrail: allow dirty cache line evictions for SMRAM to stick Reviewed-on: https://chromium-review.googlesource.com/188015 (cherry picked from commit 50fb1e6a844e1db05574c92625da23777ad7a0ca) baytrail: Optionally pull up TDO and TMS to avoid power loss in S3. Reviewed-on: https://chromium-review.googlesource.com/188260 (cherry picked from commit e240856609b4eed5ed44ec4e021ed385965768d6) rambi: always load option rom Reviewed-on: https://chromium-review.googlesource.com/188721 (cherry picked from commit d8a1d108548d20755f8683497c215e76d513b7a9) baytrail: use new chromeos ram oops API Reviewed-on: https://chromium-review.googlesource.com/186394 (cherry picked from commit f38e6969df9b5453b10d49be60b5d033d38b4594) rambi: always show dev/rec screens on eDP connected panel Reviewed-on: https://chromium-review.googlesource.com/188731 (cherry picked from commit 7d8570ac52f68492a2250fa536d55f7cbbd9ef95) baytrail: stop e820 reserving default SMM region Reviewed-on: https://chromium-review.googlesource.com/189084 (cherry picked from commit 6fce823512f5db5a09a9c89048334c3524c69a24) baytrai: update MRC wrapper header Reviewed-on: https://chromium-review.googlesource.com/189196 (cherry picked from commit 36b33a25b6603b6a74990b00d981226440b68970) rambi: Put LPE device into ACPI mode Reviewed-on: https://chromium-review.googlesource.com/189371 (cherry picked from commit 5955350cd57fd1b3732b6db62911d824712a5413) baytrail: DPTF: Enable mainboard-specific PPCC Reviewed-on: https://chromium-review.googlesource.com/189576 (cherry picked from commit 27fae3e670244b529b7c0241742fc2b55d52c612) baytrail: Add config option for PCIe wake Reviewed-on: https://chromium-review.googlesource.com/189994 (cherry picked from commit 1cc31a7c021ec84311f1d4e89dd3e57ca8801ab5) rambi: Enable PCIe wake Reviewed-on: https://chromium-review.googlesource.com/189995 (cherry picked from commit c98ae1fee54cfb2b3d3c21a19cdbbf56a0bfa1e6) Squashed 13 commits for baytrail/rambi. Change-Id: I153ef5a43e2bede05cfd624f53e24a0013fd8fb4 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6957 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-19x86 romstage: Move stack just below RAMTOPKyösti Mälkki
Placement of romstage stack in RAM was vulnerable for getting corrupted by decompressed ramstage. Change-Id: Ic032bd3e69f4ab8dab8e5932df39fab70aa3e769 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7096 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-19haswell baytrail: Enable RELOCATABLE_RAMSTAGEKyösti Mälkki
Change-Id: I84ee953196ae9bed3392c2b9bab2e8d9f0d27908 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7095 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-10-14intel/fsp_baytrail: Add padding so device_nvs location matches ACPIScott Radcliffe
The offset of the device_nvs in the gnvs struct is expected to be 0x1000. It is actually 0x100 so padding is needed to move device_nvs to the expected location. ACPI references to device_nvs objects will be correct with the padding. This was tested using a Micro Industries customized Baytrail-I board based on the Intel Bayley Bay CRB. In intel/baytrail/nvs.h, there's a Google customized structure located at 0x0100-0x0FFF that is removed from the fsp_baytrail/nvs.h which explains the mismatch here. Change-Id: I4721a79b53b5b3345ff9b0c053bdd31d2cf9cb61 Signed-off-by: Scott Radcliffe <sradcliffe@microind.com> Reviewed-on: http://review.coreboot.org/7038 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-14baytrail: Add padding to the end of device_nvs to match ACPIScott Radcliffe
ACPI globalnvs.asl expects the gnvs memory area size to be 0x2000. Padding has been added to device_nvs struct to reserve the full 0x2000 bytes for gnvs usage. No known issues are caused by having the GNVS area shorter than what ACPI thinks. Since there's nothing defined in this area, O/S shouldn't try to access it. Only problem might be if O/S notices the SSDT is located within the GNVS defined area. I verified that the next table written to memory (SSDT) is 0x2000 past GNVS start using a custom-designed Baytrail-I motherboard based on the Intel Bayley Bay CRB. Change-Id: I9792954c7a3403eba6f37d7e53ea4a9ed3a2e4ac Signed-off-by: Scott Radcliffe <sradcliffe@microind.com> Reviewed-on: http://review.coreboot.org/7039 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-14intel/fsp_baytrail: Clear the GNVS area prior to fillingScott Radcliffe
Zero out the GNVS area so that uninitialized portions are defined. Tests using Microsoft Windows (XP/7/8) gave a bluescreen bugcheck: A5 (ACPI_BIOS_ERROR) with the first parameter (0x00001000) (ACPI_BIOS_USING_OS_MEMORY). Some ACPI enumerated devices use the GNVS area to define whether they're enabled and their MMIO regions. On my custom baytrail-based board and build, these devices were disabled but GNVS had uninitialized data indicating the devices were enabled with improper MMIO regions. Should investigate further to see where the GNVS device values are set if enabled and make sure they're set to valid values even when the devices are disabled via the mainboard/devicetree.cb. Change-Id: I2b575c65bfaab58ae6206ac6f457c259c27a7d97 Signed-off-by: Scott Radcliffe <sradcliffe@microind.com> Reviewed-on: http://review.coreboot.org/7040 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-10-09intel/fsp_baytrail: Include header for "southcluster_smm_save_gpio_route"Kayalvizhi Dhandapani
Fix the error 'implicit declaration of function "southcluster_smm_save_gpio_route"', when SMM module is added. Change-Id: Ia050ab7e2b036541537b645d3fe4dc747cd1dff8 Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com> Reviewed-on: http://review.coreboot.org/7024 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-10-09intel/fsp_baytrail: fix error "unknown type device_t", when SMM Module addedKayalvizhi Dhandapani
Change-Id: I6d8622c7f343619b915442d8056aa6672dfc4f6e Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com> Reviewed-on: http://review.coreboot.org/7025 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-10-09intel/fsp_baytrail: Fix SMM/SMIKayalvizhi Dhandapani
With SMM enabled the boot stopped while patching up global NVS in DSDT. The cause is that both CPUs are assigned the same SMBASE address. So update the "cpu_smm_do_relocation()" function so that each CPU gets a different SMBASE address Based on rmodule work that wasn't propagated to the FSP version: commit 3eb8eb7eba55cdfd64c8d50181ea066526ff6485 Change-Id: I77cd27d3a4f207411a689b5be572b4406a03f16b Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com> Reviewed-on: http://review.coreboot.org/7026 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-10-01baytrail: update C0 microcodeShawn Nematbakhsh
baytrail: Add 811 microcode for C0 parts Incorporate 811 microcode version for C0 stepping parts. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Old-Change-Id: Ic34c233df28fa2c94db3a886faad8239a05f475d Reviewed-on: https://chromium-review.googlesource.com/191693 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 57c9cbdb9e4bb1cf721849ace8958eb6ec032594) baytrail: Add 813 microcode for C0 parts Incorporate 813 microcode version for C0 stepping parts. Old-Change-Id: I513ce5cc1470fa0154bee088547c5cb8a5902fb5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/195200 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit bf15a48c6bd71c2b0ab91530713afb26e139ad9c) baytrail: Update microcode to version 816 Version 816 of microcode. Old-Change-Id: I868702ec94a265013bb5e378a2345ff1cf0dc364 Original-Change-Id: I9a9cacf2d16bdabdb7ec84607bf6c96e4ac3f3c4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197692 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 16512b09e399c05cf42694854277aa7f1753e49e) Squashed 3 successive updates for baytrail C0 microcode. Change-Id: I76714ae636b119348e6bb9f8a4639c68be32ba3a Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/7000 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-09-29intel/fsp_baytrail: Add S3 suspend/resume SupportMohan D'Costa
This adds S3 Suspend / Resume support to Intel's Bay Trail FSP It is based on the "src/soc/intel/baytrail/romstage/romstage.c" implementation. Change-Id: If0011068eb7290d1b764c5c4b12c17375fb69008 Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp> Reviewed-on: http://review.coreboot.org/6937 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins)
2014-09-24baytrail: add 80c microcode for C0 partsAaron Durbin
Incoprorate 80c microcode version for C0 stepping parts. Change-Id: I2a76b4c92cac0aca5949313060f1d315ebd8e1a9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187842 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 318027a8853060e7223524dbd2ad7c3b6cc9b766) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6950 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-09-19baytrail/rambi: spi, charger, and audio updatesAaron Durbin
baytrail: combine SPI configuration in romstage Reviewed-on: https://chromium-review.googlesource.com/185140 (cherry picked from commit 4e7f0e8ae1138e478ae7106d54719cf05e13b402) baytrail: lock down registers before handoff Reviewed-on: https://chromium-review.googlesource.com/185200 (cherry picked from commit 82cce4d2b46ccc554b71efa179b5d95756e2ad5e) baytrail: invoke SMM finalization on handoff Reviewed-on: https://chromium-review.googlesource.com/185201 (cherry picked from commit 1b50affb1fdda52a5986c9429713930ed517a86a) rambi: don't invoke SMM finalization Reviewed-on: https://chromium-review.googlesource.com/185202 (cherry picked from commit 6eff475dae7f4536eb846ccf6d51fce262b8ffef) rambi: remove handling of APM_CNT_FINALIZE Reviewed-on: https://chromium-review.googlesource.com/185203 (cherry picked from commit 9fc310d7e2730466cc7fcc84999502a2d4d08bab) baytrail: don't increment boot count on S3 resume Reviewed-on: https://chromium-review.googlesource.com/185381 (cherry picked from commit 940a0fa4df1ce335229eb6f80143b93a84ba358c) rambi: enable HDA device Reviewed-on: https://chromium-review.googlesource.com/184574 (cherry picked from commit 334f2a5c7c6540e744b6aaf7e1da0b55e1368196) baytrail: lock down spi controller according to mainboard Reviewed-on: https://chromium-review.googlesource.com/185631 (cherry picked from commit 696ece68cb6d522c248e800f168e675e4b4a7317) rambi: implement mainboard_get_spi_config() to lock dow spi controller Reviewed-on: https://chromium-review.googlesource.com/185632 (cherry picked from commit 1d9ba15858fd421a4fe5a47f7171273128e89524) baytrail: introduce ssus_disable_internal_pull() Reviewed-on: https://chromium-review.googlesource.com/185740 (cherry picked from commit 9d6056dd70b27183dab6a4656f4f9612ae870a4d) rambi: fix write-protect gpio reading at romstage Reviewed-on: https://chromium-review.googlesource.com/185741 (cherry picked from commit c64627689b1afec59be6fdab323d5492046f0bc7) baytrail: DPTF: implement charger current limit Reviewed-on: https://chromium-review.googlesource.com/185759 (cherry picked from commit 287e8936613a7a83281ff692b20383dacf7fcaf6) rambi: Enable charger participant and define states Reviewed-on: https://chromium-review.googlesource.com/185760 (cherry picked from commit 2f62a11927ecf10cb2c76a9f5d368d4050404137) baytrail: increase command wait timeout Reviewed-on: https://chromium-review.googlesource.com/185874 (cherry picked from commit 962a79ef72169b5d52fc746d1889d3b652fd9bcc) baytrail: make caching MRC data more robust Reviewed-on: https://chromium-review.googlesource.com/185875 (cherry picked from commit b5e10ad47b9e4f330caaee4faf69702f24d6bdd8) baytrail: upgrade MRC wrapper header Reviewed-on: https://chromium-review.googlesource.com/186391 (cherry picked from commit 8c1a62f1f4261d4f38aacbbb353c9d6218ec2885) rambi: instruct MRC to use weaker memory ODT settings Reviewed-on: https://chromium-review.googlesource.com/186420 (cherry picked from commit b9329126ca08d20ce1d8c5db0fcabd39140c7292) rambi: Move touch wakeup resource GPIO to separate device Reviewed-on: https://chromium-review.googlesource.com/186932 (cherry picked from commit ba44e2e04f9469c629cb61a911c8cd339f52b0ef) baytrail: Set some MSRs related to turbo power Reviewed-on: https://chromium-review.googlesource.com/186933 (cherry picked from commit 76b25df5a31914ae58d47d17af448216011e425c) baytrail: change power consumption number for ACPI_C3/C6FS. Reviewed-on: https://chromium-review.googlesource.com/186934 (cherry picked from commit 5192e2464fbb88ea6fc117070240c9733e34f065) baytrail: Fix use of ConcatenateResTemplate() in ACPI LPE device Reviewed-on: https://chromium-review.googlesource.com/186928 (cherry picked from commit 8d1ab5de1d43b0790d140f6d0e36a990a5049ece) baytrail: Disable P-state HW coordination on 4-core SKU Reviewed-on: https://chromium-review.googlesource.com/187575 (cherry picked from commit c19c0f1d7cb3cb2635766c186ba9598933424a78) baytrail: DPTF: Enable mainboard-specific _PDL Reviewed-on: https://chromium-review.googlesource.com/187576 (cherry picked from commit 5412ac5c07bee22017a0ee6d1e2433917b98ea87) rambi: Apply DPTF tuning parameters Reviewed-on: https://chromium-review.googlesource.com/187577 (cherry picked from commit 932a5a3803ceaf430ad2934b371ac0886c25efca) rambi : change lpe_codec_clk_freq to 19.2 Reviewed-on: https://chromium-review.googlesource.com/187594 (cherry picked from commit f64cb1ae77076ad5ec994670f4a83dc561ea80c4) Squashed 25 commits for baytrail/rambi. Change-Id: Ibe628ac974d117a09361f7f3131a488911ddd27d Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6933 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2014-09-18rambi/baytrail: ACPI, GPIO, audio, misc updatesShawn Nematbakhsh
rambi: Change RAM_ID GPIOs to GPIO_INPUT Reviewed-on: https://chromium-review.googlesource.com/182934 (cherry picked from commit 8afd981a091a3711ff3b55520fe73f57f7258cc0) baytrail: initialize rtc device Reviewed-on: https://chromium-review.googlesource.com/183051 (cherry picked from commit 1b80d71e4942310bd7e83c5565c6a06c30811821) baytrail: Set SOC power budget values for SdpProfile 2&3 Reviewed-on: https://chromium-review.googlesource.com/183101 (cherry picked from commit 87d49323cac4492c23f910bd7d43b83b3c8a9b55) baytrail: Set PMC PTPS register correctly Reviewed-on: https://chromium-review.googlesource.com/183280 (cherry picked from commit 1b520b577f2bf1b124db301f57421665b637f9ad) baytrail: update to version 809 microcode for c0 Reviewed-on: https://chromium-review.googlesource.com/183256 (cherry picked from commit 8ed0ef4c3bed1196256c691be5b80563b81baa5e) baytrail: Add a shared GNVS init function Reviewed-on: https://chromium-review.googlesource.com/183332 (cherry picked from commit 969dffda1d3d0adaee58d604b6eeea13a41a408c) baytrail: Add basic support for ACPI System Wake Source Reviewed-on: https://chromium-review.googlesource.com/183333 (cherry picked from commit a6b85ad950fb3a51d12cb91c869420b72b433619) baytrail: allow configuration of io hole size Reviewed-on: https://chromium-review.googlesource.com/183269 (cherry picked from commit 95a79aff57ec7bf4bcbf0207a017c9dab10c1919) baytrail: add in C0 stepping idenitification support. Reviewed-on: https://chromium-review.googlesource.com/183594 (cherry picked from commit 8ad02684b25f2870cdea334fbd081f0ef4467cd4) baytrail: add option for enabling PS2 mode Reviewed-on: https://chromium-review.googlesource.com/183595 (cherry picked from commit c92db75de5edc2ff745c1d40155e8b654ad3d49f) rambi: enable PS2 mode for VNN and VCC Reviewed-on: https://chromium-review.googlesource.com/183596 (cherry picked from commit 821ce0e72c93adb60404a4dc4ff8c0f6285cbdf9) baytrail: add config option for disabling slp_x stretching Reviewed-on: https://chromium-review.googlesource.com/183587 (cherry picked from commit f99804c2649bef436644dd300be2a595659ceece) rambi: disable slp_x stretching after sus fail Reviewed-on: https://chromium-review.googlesource.com/183588 (cherry picked from commit 753fadb6b9e90fc8d1c5092d50b20a2826d8d880) baytrail: ACPI_ENABLE_WAKE_SUS_GPIO macro for ACPI Reviewed-on: https://chromium-review.googlesource.com/183597 (cherry picked from commit 78775098a87f46b3bb66ade124753a195a5fa906) rambi: fix trackpad and touchscreen wake sources Reviewed-on: https://chromium-review.googlesource.com/183598 (cherry picked from commit 3022c82b020f4cafeb5be7978eef6045d1408cd5) baytrail: Add support for LPE device in ACPI mode Reviewed-on: https://chromium-review.googlesource.com/184006 (cherry picked from commit 398387ed75a63ce5a6033239ac24b5e1d77c8c9f) rambi: Add LPE GPIOs for Jack/Mic detect Reviewed-on: https://chromium-review.googlesource.com/184007 (cherry picked from commit edde584bb23bae1e703481e0f33a1f036373a578) rambi: Set TSRx passive threshold to 60C Reviewed-on: https://chromium-review.googlesource.com/184008 (cherry picked from commit 1d6aeb85fd1af64d5f7c564c6709a1cf6daad5ee) baytrail: DPTF: Add PPCC object for power limit information Reviewed-on: https://chromium-review.googlesource.com/184158 (cherry picked from commit e9c002c393d8b4904f9d57c5c8e7cf1dfce5049b) baytrail: DPTF: Add _CRT/_PSV objects for the CPU participant Reviewed-on: https://chromium-review.googlesource.com/184442 (cherry picked from commit e04c20962aede1aa9e6899bd3072daa82e8613bd) rambi: Move the CPU passive/critical threshold config to DPTF Reviewed-on: https://chromium-review.googlesource.com/184443 (cherry picked from commit dda468793143a6d288981b6d7e1cd5ef4514c2ac) baytrail: Fix XHCI controller reset on resume Reviewed-on: https://chromium-review.googlesource.com/184500 (cherry picked from commit 0457b5dce1860709fcce1407e42ae83023b463cd) baytrail: update lpe audio firmware location Reviewed-on: https://chromium-review.googlesource.com/184481 (cherry picked from commit 0472e6bd45cb069fbe4939c6de499e03c3707ba6) rambi: Put LPSS devices in ACPI mode Reviewed-on: https://chromium-review.googlesource.com/184530 (cherry picked from commit 52bec109860b95e2d6260d5433f33d0923a05ce1) baytrail: initialize HDA device and HDMI codec Reviewed-on: https://chromium-review.googlesource.com/184710 (cherry picked from commit 393198705034aa9c6935615dda6eba8b6bd5c961) baytrail: provide GPIO_ACPI_WAKE configuration Reviewed-on: https://chromium-review.googlesource.com/184718 (cherry picked from commit 44558c3346f5b96cf7b3dcb25a23b4e99855497b) rambi: configure wake pins as just wake sources Reviewed-on: https://chromium-review.googlesource.com/184719 (cherry picked from commit ee4620a90a131dce49f96b2da7f0a3bb70b13115) baytrail: I2C: Add config data to ACPI Device Reviewed-on: https://chromium-review.googlesource.com/184922 (cherry picked from commit ffb73af007e77faf497fbc3321c8163d18c24ec8) Squashed 28 commits for rambi and baytrail. Change-Id: If6060681bb5dc9432a54e6f3c6af9d8080debad8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6916 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-08-28soc/intel/baytrail/Kconfig: Remove empty line at top filePaul Menzel
Change-Id: I932e4566ec6313a7f2dbd58784bde71bca12abd7 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6671 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-15Move baytrail-specific config to baytrail.Vladimir Serbinenko
Stop polluting first screen of all boards. Change-Id: I1ab88075722f7f0d63550010e7c645281603c9c3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6548 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-11soc/intel/fsp_baytrail: set up for including irqroute.h twiceMartin Roth
irq_helper.h intentionally gets included into irqroute.asl twice - once for pic mode and once for apic mode. Since people are used to seeing guard statements on the .h files, add the guards to irqroute.h and add a comment to irq_helper.h explaining why they aren't there. Add a time. Change-Id: I882cbbff0f73bdb170bd0f1053767893722dc60a Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6572 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-01fsp_baytrail/.../gpio.h: Add GPIO_NC1 for GPIOS on func 1Martin Roth
The GPIO_NC setting sets up the gpio as a no-connect - sets it as an input, and pulls it high. It makes an assumption that the GPIO function is muxing function 0. There are a few GPIOs that are on function 1 instead: * GPIO_S0_SC[092-93] * GPIO_S5[11-21] For these GPIOs, use the GPIO_NC1 setting instead of GPIO_NC. Change-Id: Iac6790b40e87ad4ac9a3b265a8e10662186c1201 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6428 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-23src/.../Kconfig: various small fixes to textsDaniele Forsi
Fixed spelling and added empty lines to separate the help from the text automatically added during make menuconfig. Change-Id: I6eee2c86e30573deb8cf0d42fda8b8329e1156c7 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6313 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-17soc,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I6db4eada5be5f9a4340d9edb942924e2fd18b5ca Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6284 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17soc,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: If70f5ad26d639d7366772f4468a25bca83ac0857 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6295 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-14SPI: Split writes using spi_crop_chunk()Kyösti Mälkki
SPI controllers in Intel and AMD bridges have a slightly different restriction on how long transactions they can handle. Change-Id: I3d149d4b7e7e9633482a153d5e380a86c553d871 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6163 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-08soc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I1829c77f41cc809b590d00ef5522f368bd5fd814 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6208 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-05spi: Change spi_xfer to work in units of bytes instead of bits.Gabe Black
Whenever spi_xfer is called and whenver it's implemented, the natural unit for the amount of data being transfered is bytes. The API expected things to be expressed in bits, however, which led to a lot of multiplying and dividing by eight, and checkes to make sure things were multiples of eight. All of that can now be removed. BUG=None TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI errors in the firmware log. Built for rambi. BRANCH=None Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192049 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6175 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.Gabe Black
The spi_flash_probe and and spi_setup_slave functions each took a max_hz parameter and a spi_mode parameter which were never used. BUG=None TEST=Built for link, falco, rambi, nyan. BRANCH=None Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192046 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6174 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-23baytrail_fsp: Fix the mmconf KconfigMartin Roth
The override value in the mainboard that was removed was correct. Change-Id: Ie820df0d6b7a713488173240f0c0ca4a9e108f71 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6095 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-06-23fsp_baytrail: Minor Kconfig updatesMartin Roth
- remove the Kconfig text when setting the default for the FSP location. The text was showing up twice in the config menu. - Remove an extra 'the' in the help text. Change-Id: I3777833bf32e19bbe5a8493578a9346d6ab062a4 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6090 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-21intel boards: Use acpi_is_wakeup_s3()Kyösti Mälkki
Change-Id: Icab0aeb2d5bf19b4029ca29b8a1e7564ef59a538 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6071 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-18fsp_baytrail: Add the default FSP locationMartin Roth
The default FSP location needs to be in the chipset, not the mainboard. This was removed from the Bayley Bay mainboard in patch 41ea7230f7 reviewed at http://review.coreboot.org/#/c/5982/ Change-Id: Ia26ed34e1401cbd2303166628e7a4e357d79c874 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5985 Reviewed-by: Dave Frodin <dave.frodin@se-eng.com> Tested-by: build bot (Jenkins)
2014-06-18fsp_baytrail: Add Baytrail B0/B1 "Super SKU" microcodeMartin Roth
- Add the Bay Trail B0/B1 microcode. These versions of the SOC were released as a "Super SKU" which had features of all the different SKUS (M/D/T/I), and identified as a Bay Trail T as noted by the number 2 in the third character from the left in the microcode name. - Update the size of the microcode blob. We should be pushing a patch to eliminate the need for this shortly. Change-Id: I57ba51eabe9ea0609ab809f18b95e3bc9d5cb191 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5986 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-06-18ACPI: Remove CBMEM TOC from GNVSKyösti Mälkki
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM. Change-Id: I558a7ae333e5874670206e20a147dd6598a3a5e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6032 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-13fsp_baytrail: remove version from default vbios pathMartin Roth
Intel requested that we remove the version number from the default vbios path. Change-Id: I2590fed0db157e3e430212336fc55eb099d28a72 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5984 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-13fsp_baytrail: Fix CONFIG_ENABLE_FSP_FAST_BOOTMartin Roth
While pushing the fsp_baytrail code, it was requested that we change CONFIG_ENABLE_FAST_BOOT to CONFIG_ENABLE_FSP_FAST_BOOT. These were missed in the change. Change-Id: If8af3f90b0f5cc9154ff1d3a387f442430f42dee Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5972 Tested-by: build bot (Jenkins) Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-30cpu/intel/fsp_model_206ax: change realpath to readlinkMartin Roth
realpath and readlink can be used to do the same thing - in this case we're turning path1/path2/../path3/path4 into path1/path3/path4 so that the makefile's wildcard routine can evaluate it. Debian derivatives don't seem to include realpath. (and even when it's installed, it's not the gnu coreutils version.) Change-Id: I0a80a1d9b563810bdf96aea9d5de79ce1cea457a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/5793 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
2014-05-29fsp_baytrail: Add the FSP version of Intel's Bay Trail-I chipMartin Roth
While similar to the Bay Trail-M/D code based on the MRC, there are many differences as well: - Obviously, uses the FSP instead of the MRC binaries. - FSP does additional hardware setup, so coreboot doesn't need to. - Different microcode & microcode loading method - Uses the cache_as_ram.inc from the FSP Driver - Various other changes in support of the FSP Additional changes that don't have to to with the FSP vs MRC: - Updated IRQ Routing - Different FADT implementation. This was validated with FSP: BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd SHA256: d29eefbb33454bd5314bfaa38fb055d592a757de7b348ed7096cd8c2d65908a5 MD5: 9360cd915f0d3e4116bbc782233d7b91 Change-Id: Iadadf8cd6cf444ba840e0f76d3aed7825cd7aee4 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5791 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-17build: separate CPPFLAGS from CFLAGSPatrick Georgi
There are a couple of places where CPPFLAGS are pasted into CFLAGS, eliminate them. Change-Id: Ic7f568cf87a7d9c5c52e2942032a867161036bd7 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5765 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17build: CPPFLAGS is more common than INCLUDESPatrick Georgi
Rename INCLUDES to CPPFLAGS since the latter is more commonly used for preprocessor options. Change-Id: I522bb01c44856d0eccf221fa43d2d644bdf01d69 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5764 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-15baytrail: Add SOC thermal settingsDuncan Laurie
Apply the SOC thermal settings from DPTF reference code for SdpProfile=4 and adjust graphics PUNIT setting to match. BUG=chrome-os-partner:17279 BRANCH=baytrail TEST=boot on rambi and check for valid GPU power values from DPTF Change-Id: I59fc4b75b52084ebcc4c0556563afca0585ea6b8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182786 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5052 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-15baytrail: Enable PCIe common clock and ASPMDuncan Laurie
Enable the config options to have the device enumeration layer configure common clock and ASPM for endpoints. BUG=chrome-os-partner:23629 BRANCH=baytrail TEST=build and boot on rambi, check PCIe for ASPM and common clock: lspci -vv -s 0:1c.0 | grep LnkCtl: LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ lspci -vv -s 1:00.0 | grep LnkCtl: LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ Change-Id: I2477e3cada0732dc71db0d6692ff5b6159ed269f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182860 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15baytrail: enable graphics turboAaron Durbin
Though the limited documentation indicates the default is 0 for the gfx_turbo_disable bit, in practice that isn't true. Knock down the gfs_turbo_disable bit to enable graphics turbo mode. BUG=chrome-os-partner:25044 BRANCH=baytrail TEST=Built and booted. Added debug code to output SB_BIOS_CONFIG. Noted that bit 7 was set to 0. Change-Id: I11210c6a0b29765cb709a54d6ebd94211538807b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182640 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5050 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15baytrail: use CPU_INTEL_TURBO_NOT_PACKAGE_SCOPEDAaron Durbin
On baytrail, it appears that the turbo disable setting is actually building-block scoped. One can see this on quad core parts where if enable_turbo() is called only on the BSP then only cpus 0 and 1 have turbo enabled. Fix this by calling enable_turbo() on all non-bsp cpus. BUG=chrome-os-partner:25014 BRANCH=baytrail TEST=Built and booted rambi. All cpus have bit 38 set to 0 in msr 0x1a0. Change-Id: Id493e070c4a70bb236cdbd540d2321731a99aec2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182406 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5048 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15baytrail: Add ACPI Device for XHCIDuncan Laurie
This will allow USB devices to wake the system (if 5V is not turned off) and the controller to enter D3 at runtime. (if autosuspend is enabled) BUG=chrome-os-partner:23629 BRANCH=baytrail TEST=build and boot on baytrail 1) with modified EC to leave 5V on in S3 ensure that waking from suspend with USB keyboard works. 2) with laptop-mode-tools usb autosuepend config updated see that device enters D3 at runtime when no external devices attached. Change-Id: Ia396d42494e30105f06eb3bd65b4ba8b1372cf35 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182536 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5046 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15baytrail: nvm: use proper types for checking eraseAaron Durbin
The current byte value was being converted to an int when checking against literal 0xff. As the type of the current pointer was char (signed) it was sign extending the value leading to 0xffffffff != 0xff. Fix this by using an unsigned type and using a constant type for expected erase value. BUG=chrome-os-partner:24916 BRANCH=baytrail TEST=Booted after chromeos-firmwareupdate. Noted that MRC cache doesn't think the erased region isn't erased. Change-Id: If95425fe26da050acb25f52bea060e288ad3633c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182154 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5044 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15baytrail: mrc_cache: check region erased before erasingAaron Durbin
On a firmware update the MRC cache is destroyed. On the subsequent boot the MRC region was attempted to be erased even if it was already erased. This led to spi part taking longer than it should have for an unnecessary erase operation. Therefore, check that the region is erased before issuing the erease command. BUG=chrome-os-partner:24916 BRANCH=baytrail TEST=Booted after chromeos-firmeareupdate. Noted no error messages in this path. Change-Id: I6fadeb6bc5fc178abb0a7e3f0898855e481add2e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182153 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5043 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-13baytrail: add C0 microcode updateAaron Durbin
Include C0 microcode drop. BUG=None BRANCH=rambi,squawks TEST=Built. Booted B3 part. Change-Id: If454658235cd5a7b8640de0b3fa12dccddb0e9f6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182080 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5041 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: reboot with EC in S0 with no MRC cache and EC in RWAaron Durbin
This improves boot time in 2 ways for a firmware upgrade: 1. Normally MRC would detect the S0 state without an MRC cache even though it's told to the S5 path. When it observes this state a cold reset occurs. The cold reset stays in S5 for at least 4 seconds which is time observed by the end user. 2. As the EC was running RW code before the reset after firmware upgrade it will still be running the older RW code. Vboot will then reboot the EC and the whole system to put the EC into RO mode so it can handle the RW update. The issues are mitigated by detecting the system is in S0 with no MRC cache and the EC isn't in RO mode. Therefore we can do the reboot without waiting the 4 secs and the EC is running RO so the 2nd reboot is not necessary. BUG=chrome-os-partner:24133 BRANCH=rambi,squawks TEST=Booted. Updated firmware while in OS. Rebooted. Noted the EC reboot before MRC execution. Change-Id: I1c53d334a5e18c237a74ffbe96f263a7540cd8fe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182061 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5040 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: dptf: Add disable trip point methodsDuncan Laurie
Added a method in each temp sensor to disable the aux trip points and then a wrapper function to call this method for each enabled temperature sensor. The event handler function is changed to not use a switch statement so it does not need to be serialized. This was causing issues with nested locking between the global lock and the EC PATM mutex. Some unused code in temp sensors that was added earlier is removed and instead a critical threshold is specified in _CRT. The top level DPTF device _OSC method is expanded to check for the passive policy UUID and initialize thermal devices. This is done for both enable and disable steps to ensure that the EC thermal thresholds are reset in both cases. Additionally the priority based _TRT is specified with TRTR=1. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi, load esif_lf kernel drivers and start esif_uf application. Observe that temperature thresholds are set properly when running 'appstart Dptf' and that they are disabled after running 'appstop Dptf' Change-Id: Ia15824ca42164dadae2011d4e364b70905e36f85 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182024 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5037 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: Updates for DPTF ACPI frameworkDuncan Laurie
- Remove some unused functions from CPU participant that were confusing the userland component since the CPU does not have an ACPI managed sensor. - Guard the charger participant with an ifdef so it can be left out if not supported. - Use the EC methods for setting auxiliary trip points and for handling the event when those trip points are crossed. - Add _NTT _DTI _SCP methods for thermal sensors. I'm not clear if these are required or not but they seem to be expected by the other DPTF framework components. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi and load ESIF framework Change-Id: I3c9d92d5c52e5a7ec890a377e65ebf118cdd7087 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181662 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5028 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: don't SMI on tco timer firingAaron Durbin
The SMI on TCO timer timeout policy was copied from other chipsets. However, it's not very advantageous to have the TCO timer timeout trigger an SMI unless the firmware was the one responsible for setting up the timer. BUG=chromium:321832 BRANCH=rambi,squawks TEST=Manually enabled TCO timer. TCO fires and logged in eventlog. Change-Id: I420b14d6aa778335a925784a64160fa885cba20f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181985 Reviewed-on: http://review.coreboot.org/5035 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: clear the pmc wake status registersAaron Durbin
The PMC in baytrail maintains an additional set wake status in memory-mapped registers. If these bits aren't cleared the device won't be able to go to S5 or S3 without being immediately woken up. Therefore clear these registers. BUG=chrome-os-partner:24913 BRANCH=rambi,squawks TEST=Ensured PRSTS bit 4 is cleared after a reboot and S3 and S5 work correctly. Change-Id: I356e00ece851961135b4760cebcdd34e8b9da027 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181984 Reviewed-on: http://review.coreboot.org/5034 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: log reset, power, and wake events in elogAaron Durbin
When CONFIG_ELOG is selected the reset, power, and wake events are logged in the eventlog. BUG=chrome-os-partner:24907 BRANCH=rambi,squawks TEST=Various resets and wake sources. Interrogated eventlog to ensure results are expected. Change-Id: Ia68548562917be6c2a0d8d405a5b519102b8c563 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181983 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5033 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: snapshot power state in romstageAaron Durbin
The memory reference code doesn't maintain some of the registers which contain valuable information in order to log correct reset and wake events in the eventlog. Therefore snapshot the registers which matter in this area so that they can be consumed by ramstage. BUG=chrome-os-partner:24907 BRANCH=rambi,squawks TEST=Did various resets/wakes with logging patch which consumes this structure. Eventlog can pick up reset events and power failures. Change-Id: Id8d2d782dd4e1133113f5308c4ccfe79bc6d3e03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181982 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5032 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13baytrail: add cpuid for C0Aaron Durbin
The C0 part uses a new cpuid. BUG=None BRANCH=squawks,rambi TEST=None. Change-Id: Iddf1bc4d6f7bbec3ca92bff8edf613e00a4b4286 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181980 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5031 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-12baytrail: align with intel recommendationsAaron Durbin
The BISOC.EXIT_SELF_REFRESH_LATENCY field should not be updated from the default. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I6e701a520513372318258648e998dd8c7ab29ea4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180730 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5025 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-12baytrail: add way to load reference code from vboot areaAaron Durbin
When employing vboot firmware verification the reference code loading should load from the verified firmware section. Add this ability. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted rambi. Noted firmware being loaded from rw verified area. Also noted S3 resume loading from cached area. Change-Id: I114de844f218b7573cf90107e174bf0962fdaa50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180026 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5023 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-12baytrail: Expose IOSF as ACPI objectDuncan Laurie
The kernel iosf driver uses HID INT33BD to probe and be provided the 12 bytes in PCI for access. BUG=chrome-os-partner:17279 BRANCH=none TEST=build and boot on rambi, load iosf_mbi driver and verify that it gets address 0xe00000d0 Change-Id: I865eafe664f00f21d1ebb967c291083830d895b9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180098 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5021 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-12baytrail: Put devices in ACPI mode after setupDuncan Laurie
Make sure reg_script is executed before the device is put into ACPI mode. BUG=chrome-os-partner:24380 BRANCH=none TEST=build and boot rambi from eMMC in ACPI mode Change-Id: I4090babbfc7fb0f3be4da869386e998d87a513ba Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179896 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5017 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-12baytrail: Add header include wrapper and offset defineDuncan Laurie
Since this file will get added to payloads it is useful if it exports what offset in NVS it lives. BUG=chrome-os-partner:24380 BRANCH=none TEST=build and boot rambi with emmc in ACPI mode Change-Id: I52860980c91dfe2525628e142b34ca192e69b258 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179848 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5014 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-10baytrail: cache reference code for S3 resumeAaron Durbin
In order to use the same reference code on S3 resume that was booted the program needs to be cached. Piggy back on the ramstage cache to save the loaded reference code program. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Noted locations of reference code caching and load addresses in console. Change-Id: I90ceaf5697e8c269c3244370519d4d8a8ee2eb4a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179777 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5013 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: allow ramstage_cache_location() usage in ramstageAaron Durbin
To prepare for caching reference code for S3 resume the ramstage cache needs to be accesible in ramstage as well. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I4c825c965b98cd71ea0eb9c93fe168a358da4c97 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179776 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5012 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: note S3 resume status earlierAaron Durbin
Certain code paths want to know if S3 resume is happening. However, the current baytrail code doesn't note S3 resume early enough. Therefore, mark S3 resume just after pattr setup. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I5e5cc285940e4567521afb8483614ce6f813ddde Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179774 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5010 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: utilize reg_script_run_on_dev()Aaron Durbin
The inclusion of reg_script_run_on_dev() allows for removing some of the chained reg_scripts just to set up the device context. Use the new reg_script function in those cases. BUG=None BRANCH=None TEST=Built and booted. Didn't see any bizarre dmesg or coreboot console output. Change-Id: I3207449424c1efe92186125004d5aea1bb5ba438 Signed-off-by: Aaron Durbin <adurbin@chromium.og> Reviewed-on: https://chromium-review.googlesource.com/179541 Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5009 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: initialize perf/power registersAaron Durbin
According to the reference code all these registers need to be set to their best known values. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. Suspend and wake. No idea about observable impact yet. Change-Id: I0e31505a165eee1d177e5d726edcfa6947430476 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179749 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5008 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: add more iosf access functionsAaron Durbin
There's a slew of ports required to initialize baytrail's perf and power values. Therefore, add the necessary functionality in the iosf module as well as the reg_script library. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. Change-Id: Id45def82f9b173abeba0e67e4055f21853e62772 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179748 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5007 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: remove verbosity in iosfAaron Durbin
The iosf access functions already use some common code, however there is a duplication for setting up the proper control register for port and opcode. Introduce macros to remove this verbosity. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. Suspend and wake. Change-Id: I5bad7e2a11fa8e8bd4a3d7fa53d917b2565644f8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179747 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/5006 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10baytrail: Add support for LPSS and SCC devices in ACPI modeDuncan Laurie
This adds the option to put LPSS and SCC devices into ACPI mode by saving their BAR0 and BAR1 base addresses in a new device NVS structure that is placed at offset 0x1000 within the global NVS table. The Chrome NVS strcture is padded out to 0xf00 bytes so there is a clean offset to work with as it will need to be used by depthcharge to know what addresses devices live at. A few ACPI Mode IRQs are fixed up, DMA1 and DMA2 are swapped and the EMMC 4.5 IRQ is changed to 44. New ACPI code is provided to instantiate the LPSS and SCC devices with the magic HID values from Intel so the kernel drivers can locate and use them. The default is still for devices to be in PCI mode so this does not have any real effect without it being enabled in the mainboard devicetree. Note: this needs the updated IASL compiler which is in the CQ now because it uses the FixedDMA() ACPI operator. BUG=chrome-os-partner:23505,chrome-os-partner:24380 CQ-DEPEND=CL:179459,CL:179364 BRANCH=none TEST=manual tests on rambi device: 1) build and boot with devices still in PCI mode and ensure that nothing is changed 2) enable lpss_acpi_mode and see I2C devices detected by the kernel in ACPI mode. Note that by itself this breaks trackpad probing so that will need to be implemented before it is enabled. 3) enable scc_acpi_mode and see EMMC and SDCard devices detected by the kernel in ACPI mode. Note that this breaks depthcharge use of the EMMC because it is not longer discoverable as a PCI device. Change-Id: I2a007f3c4e0b06ace5172a15c696a8eaad41ed73 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179481 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5004 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 20:19:22 +0000