Age | Commit message (Collapse) | Author |
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Invert the default instead of selecting it everywhere. Restores the
ability to use its Kconfig prompt.
Beside Qemu targets, the only platforms that didn't select it seem
to be samsung/exynos5420, intel/cannonlake, and intel/icelake. The
latter two were about to be patched anyway.
Change-Id: I7c5b671b7dddb5c6535c97c2cbb5f5053909dc64
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30891
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Provide options to disable xHCI Link Compliance Mode. Default is FALSE
to not disable Compliance Mode. Set TRUE to disable Compliance Mode.
BRANCH=octopus
BUG=b:115699781
TEST=Verified booting to kernel.
Change-Id: I2a486bc4c1a8578cfd7ac3d17103e889eaa25fe4
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30816
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move early_mainboard_romstage_entry before console_init.
Allows to setup a SuperIO, if any, for serial console.
Change-Id: I370263a6197a4c0c805352f07fedddbee1b8e247
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Useful for debugging FSP.
Change-Id: I06e837cf1b051c55a531c3361e94fa1449bc8526
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
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* Disable FSP serial output if not CONSOLE_SERIAL
Tested on wedge100s.
Change-Id: Idd825d2d6eb423452d3e81265860205980f6aa5b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Use hexdump() instead of dump_mem().
Change-Id: I7f6431bb2903a0d06f8ed0ada93aa3231a58eb6f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Hook Coffeelake U43e and Coffeelake H/S/E3 microcode into SOC and remove
the MICROCODE_BLOB_NOT_HOOKED_UP.
BUG=N/A
TEST=Boot up with coffeelake rvp board and check microcode revision in
coreboot log.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I6593081374dd4898a82db5b43c3b5bf154b3ef60
Reviewed-on: https://review.coreboot.org/c/30864
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It's been hooked up in the meantime.
Change-Id: I64176b09e375034189000ea4308c58771f0019a1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30812
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TCO2_STS_SECOND_TO was renamed to TCO_STS_SECOND_TO but one use
slipped through.
Change-Id: I9e3b1cc5cb2f319db35416edf6cea612d755d40a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30805
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch cleans soc/intel/{apl/cnl/icl/skl} by moving common soc
code into common/block/smbus.
BUG=b:78109109
BRANCH=NONE
TEST=Build and boot KBL/CNL/APL/ICL platform.
Change-Id: I34b33922cafee9f31702587e0f9c03b64f0781b8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/26166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Silence PCI resource warning due to missing set_resources.
Change-Id: I8253e9ca137bda1cdd1c06273679693c4b7803ec
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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It was relying on bad weak implementation for postcar
and verstage.
Change-Id: I5a520e0166198c0565349c164f143f4a43649861
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Guckian
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
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The option to specify a binary file name was added later for platforms
that do not provide microcode updates in our blobs repository. Alas,
it wasn't visible what platforms these are. And if you specified a file
for a platform that already had one, they were all included together.
Make it visible which platforms don't provide binaries with the new con-
figs MICROCODE_BLOB_NOT_IN_BLOB_REPO, MICROCODE_BLOB_NOT_HOOKED_UP and
MICROCODE_BLOB_UNDISCLOSED. Based on that we can decide if we want to
include binaries by default or explicitly show that no files are inclu-
ded (default to CPU_MICROCODE_CBFS_NONE).
Also split CPU_MICROCODE_CBFS_GENERATE into the more explicit
CPU_MICROCODE_CBFS_DEFAULT_BINS and CPU_MICROCODE_CBFS_EXTERNAL_BINS.
And clean up the visibility of options: Don't show CBFS related options
on platforms that don't support it and don't show external file options
if the platform uses special rules for multiple files (CPU_MICROCODE_
MULTIPLE_FILES).
Change-Id: Ib403402e240d3531640a62ce93b7a93b4ef6ca5e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29934
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Everything is wrong here, the Kconfig symbols are only the tip of the
iceberg. Based on Kconfig prompts the SoC code performed pad configu-
rations! I don't see why the person who configures coreboot should have
the board schematics at hand.
As a mitigation, we remove the prompts for UART_DEBUG, which is renamed
to INTEL_LPSS_UART_FOR_CONSOLE (because the former didn't really say
what it's about), and for UART_FOR_CONSOLE in case the former is selec-
ted.
Change-Id: Ibe2ed3cab0bb04bb23989c22da45299f088c758b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This patch provides an option to enable or disable IPU (image processing unit),
* Add an entry for SA IPU in the pci_devs.h.
* Enable/Disable the IPU based on devicetree entry.
Change-Id: Ia155bc242dd33e816d056bbea1e3d4c1cbbe23da
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/30698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Expose the FSP tunables for the chipset minimum assertion width
settings which can be configured per-board.
The defaults appear to be different from what is listed in the FSP
header documentation so I tried to list what the actual default is
based on the source rather than what is stated the header comments.
Change-Id: Ie0606c2984727adf13c9fb8395586287162e49ca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Add logging of chipset events on boot into the flash event log.
This was tested on a google/sarien board to ensure that events
like "System Reset" are added to the log as expected.
Change-Id: I38498cef36d8cc9c8a1f63d12618ea768b65254c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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This structure is declared as a static CAR_GLOBAL in the common
PMC library code and in the SOC specific code. Remove the SOC
specific version and instead get the chipset_power_state pointer
from the PMC library.
This fixes events that were recorded in chipset_power_state at
boot but were reading as all zero when it was time to parse the
structure when logging events to flash.
Change-Id: I67a4f724c0707d98766ad28abd8d0b66a5615745
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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Link walkfcbfs.S in the C_ENVIRONMENT_BOOTBLOCK case and also in the
romstage.
This is useful for cbfs access in pre-CAR environments.
Change-Id: I9a17cdf01c7cbc3c9ac45ed1f075731f3e32f64b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Pass timestamps and BIST to romstage using the same signature
as C_ENVIRONMENT_BOOTBLOCK will.
Change-Id: Ic90da6b1b5ac3b56c69b593ba447ed8e05c8a4e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Have same usage of registers with romcc bootblock
and C_ENVIRONMENT_BOOTBLOCK.
Change-Id: Ibfa80e40f0b736a904abf4245fc23efc0cdc458d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This patch fixes icelake build brokenness due to bootblock size
issue.
Increase the bootblock size to 48K to match skylake. With UART
enabled we are very near the 32K limit, and with upcoming changes
to add USB devices in devicetree for a icelake board it is over
the current 32K limit.
BUG=b:122485106
TEST=Able to build dragonegg
Change-Id: I66706e66ac1bce677fe11022d0eef44b9efc2e76
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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Use defined name in Intel 64 and IA-32 Architectures Software
Developer’s Manual.
Renamed MSRs are (register address, register name):
0x35 MSR_CORE_THREAD_COUNT
0x121 MSR_EMULATE_PM_TIMER
0x1f4 MSR_PRMRR_PHYS_BASE
0x1f5 MSR_PRMRR_PHYS_MASK
0x2f4 MSR_UNCORE_PRMRR_PHYS_BASE
0x2f5 MSR_UNCORE_PRMRR_PHYS_MASK
Change-Id: I53f11a2ce831456d598aa21303a817d18ac89bba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
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It's not needed anymore.
Change-Id: I273acb2bf1675dc947927e3e6d2ebb78aa94518a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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The newest and most useful incarnation was hiding in soc/intel/common/.
We move it into the Mainboard menu and extend it with various flags to
be selected to control the default and which options are visible. Also
add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the
boolean to int conversion into Kconfig:
0 - S5
1 - S0
2 - previous state
This patch focuses on the Kconfig code. The C code could be unified as
well, e.g. starting with a common enum and safe wrapper around the
get_option() call.
TEST=Did what-jenkins-does with and without this commit and compared
binaries. Nothing changed for the default configurations.
Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Currently this needlessly initializes the hardware in the both the
romstage and the bootblock, but it works.
Build option is renamed to USBDEBUG_IN_PRE_RAM to reflect the
use better, related support files can be built to pre-ram stages
regardless of usbdebug being enabled or not.
Tested on Google/peppy (adapted to C_ENVIRONMENT_BOOTBLOCK).
Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Expose the function that can unconditionally re-initialise
EHCI debug host and gadget.
Given the missing header in soc/intel files that prevented
building with USBDEBUG_IN_ROMSTAGE=y, it is not actually
known if those SOCs work at all for usbdebug.
Change-Id: I8ae7e144a89a8f7e5f9d307ba4e73d4f96401a79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add possibility to update microcode from BLOBs repo.
No need to copy headers around which have an unclear license.
Tested on wedge100s:
* Microcodes are included into FIT.
* Still boots to Linux.
* 3rdparty/blobs at dd00ad1260ef1dc0ba8c55c06ab10c7639dc3eb1
Change-Id: I8ecfb7302a7fc847a51934942f6d323a4f96abba
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Follow instrcution from https://doc.coreboot.org/acpi/gpio.html to
implement GPIO toggling method, covered for both CNP_LP and CNP_H pch.
BUG=N/A
TEST=Build and boot up fine on sarien platform, add an dummy STSX in
DSDT table, read back from iotools to confirm the GPIO tx state get
updated.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I006a6a8fc580c73ac0938968397a628a4ffe504f
Reviewed-on: https://review.coreboot.org/c/30461
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Cases of *dev = PCI_DEV(b,d,f) are invalid. Not caught
because files only build with __SIMPLE_DEVICE__ defined.
Remove cases of testing __SIMPLE_DEVICE__ in files that
are not build for ramstage.
Change-Id: If10a0efa187c9b1d9a5577008aa46f050f0aa309
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: If981fa3db12b3a4fe1411f4cce9bac8564697769
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/25466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Set PchCnvimode to Auto if CNVi is enabled in device tree. This will
allow FSP to configure CNVi.
Change-Id: I4f77fe5e9f561d3b498403e42dfc7afdcfaedf6f
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30516
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Macro hides that dev_find_slot() takes two arguments.
Change-Id: I639af31b9d4a2d702dfd2baebddbb8352e8bf9b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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The same file was replicated three times for certain
soc/intel bootblocks, yet there are no indications or need to do
chipset-specific initialisation.
There is no harm in storing the TSC values in MMX registers
even when they would not be used.
Change-Id: Iec6fa0889f5887effca1d99ef830d383fb733648
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Platforms have moved to POSTCAR_STAGE=y.
Change-Id: I79c87e546805dbe0a4c28ed95f4d12666734eb79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I9090be3ccaa8a61312293e9da3679a752a908062
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I3b9217a7d9a6d98a9c5e8b69fe64c260b537bb64
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Platforms moved to POSTCAR_STAGE so these are no longer used.
Change-Id: I9a7b5a1f29b402d0e996f2c2f8c6db3800cdddf3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This was selected twice.
Change-Id: I7e20b7d3f05ecae98db1addf5aea7bf1159f4682
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Platform has been moved to C_ENVIRONMENT_BOOTBLOCK and this
file was for romcc bootblock.
Change-Id: I2c249b18edd41c9a7798400d24b1c9228422d59b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This was empty stub call doing nothing, to avoid targeting
non-existing MMX registers.
Change-Id: I78b83e6724159ea1eb0f8a0cf9d5b7ddfc9877b7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Fix the following warning shown in dmesg:
"ACPI BIOS Warning (bug): Incorrect checksum in table [FACP]"
The table checksum was wrong as it was calculated twice and with the second
time the checksum field wasn't set to zero.
Change-Id: I375354bf3e95ebdac3b0dad43659d72c6ab3175a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Tested on wedge100s.
Change-Id: I0dcbce230c151cecbbbeec581964cd5f44fbe046
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29911
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modeled after Skylake implementation; uses duplicated
intel common SA functions to get RMRR addresses
Test: build/boot purism/librem13v1, observe IOMMU fully functional
with intel_iommu=on kernel parameter
Change-Id: I1a10a4f91b787b72f33150031b783d426148c25d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Newer CPUs/SoCs need to configure other features via the
IA32_FEATURE_CONTROL msr, such as SGX, which cannot be done if the
msr is already locked. Create separate functions for setting the
vmx flag and lock bit, and rename existing function to indicate that
the lock bit will be set in addition to vmx flag (per Kconfig).
This will allow Skylake/Kabylake (and others?) to use the common
VMX code without breaking SGX, while ensuring no change in functionality
to existing platforms which current set both together.
Test: build/boot each affected platform, ensure no change in functionality
Change-Id: Iee772fe87306b4729ca012cef8640d3858e2cb06
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30229
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use of device_t is deprecated.
Change-Id: Ic29891d78514db3b7eed48414a14e4ff579436c0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30004
Reviewed-by: David Guckian
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Expose the FSP interface to enable SATA and PCH side DMI power optimize
options. Actual step executed in FSP, step defined in cannonlake pch
BIOS spec(CDI# 570374).
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ic0c589bb21e56800090bc0c75a0256a0409efc78
Reviewed-on: https://review.coreboot.org/c/30211
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SaGv(system Agent Dynamic Frequency) have 4 settings
Disabled, Fixedlow, Fixedhigh, Enabled.
This patch add all 4 settings in enum definition and
used in devicetree.
BUG=None
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: I8f3b56f4d2bea1836373cc505ef5147144100b95
Reviewed-on: https://review.coreboot.org/c/30305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Use 'BAR 1' for the bar1 structure fields.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I1d1278f549fc8a2f3e743e2e2019d3e5f7005614
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/30277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Commit c37b0e3 [soc/intel/skylake: Generate ACPI DMAR table]
only generates DMAR tables for boards using FSP 2.0, which
leaves out Skylake Chromebooks, which use FSP 1.1.
Correct this omission by adding the same functionality for
FSP 1.1 boards.
Test: build/boot on U-series Skylake Chromebook, observe
IOMMU fully functional with intel_iommu=on kernel parameter.
Change-Id: I68837f58aac357fa3f58979fe92d8993fae58640
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Update HDAenable bit in Fsp memory init UPD data base on devicetree
settings.
BUG=N/A
TEST=N/A
Change-Id: I5159c00a855a2a9516714ccee8ee9933465c5063
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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FSP support two SATA modes as AHCI mode (0) and RAID mode (1), make it
more clear in header file.
Change-Id: I1edcadc0048df839da145260b60f9f7720d981fe
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30093
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CPU ratio will be fixed to non-turbo max value if CpuRatio UPD had been
set to zero.
BUG=N/A
TEST=Boot up into sarien system, cat /proc/cpuinfo and cpu frequency is
changing.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I3e82293c8b6027ddf9a528d0654fe46f233dcb82
Reviewed-on: https://review.coreboot.org/c/30216
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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RAM is reserved for Chromeos even when Chrome is not used.
Use CONFIG_CHROMEOS to determine if RAM must be reserved.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I3f55bf96ab2ec66cddbb54de03455a9bfd194682
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fix typo of "VGOIO" back to "VGPIO".
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ia2b7cb0e5fe2817acc3e3f4656b98dc2462b397f
Reviewed-on: https://review.coreboot.org/c/30147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Change-Id: Idef8c556ac8c05c5e2047a38629422544392cd62
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Expose the following FSP UPD interface into coreboot, which is the
following:
AcousticNoiseMitigation
FastPkgCRampDisableIa
FastPkgCRampDisableGt
FastPkgCRampDisableSa
FastPkgCRampDisableFivr
SlowSlewRateForIa
SlowSlewRateForGt
SlowSlewRateForSa
SlowSlewRateForFivr
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I21f53c594a085794474e87eb6781b51db88d0c10
Reviewed-on: https://review.coreboot.org/c/30207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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commit msg copied from
commit id: 64c9f1584c63403207ee85b1d54ca594ae1fbedf
The GPIO drivers in Windows and Linux for the Icelake CPU
have a sparse GPIO map and do not allocate pins contiguously.
Each GPIO group is allocated as 32 pads regardless of whether
the hardware actually has that many in the group.
It appears this originated with a bug in Windows/UEFI and was
carried over to Linux in order to work with existing firmware:
https://lore.kernel.org/patchwork/patch/855244/
In order to support using ACPI GPIOs it is necessary for coreboot
to be compatible with this implementation. The GPIO groups that
are usable by the OS are declared with a pad base which is then
used to compute the number for ACPI GPIOs.
Change-Id: I94fafd8af13cf229f5c467de5179aed021465739
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
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Change-Id: I64e061017ee0b1202ce5482b26c7550e4cd0f0a7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The Intel GMA ACPI opregion address needs to be set on S3 resume,
otherwise the Windows display driver fails to re-initialize correctly.
Fix by ensuring the address is set correctly regardless of display
init type used (GOP or VBIOS).
Test: build/boot on google/edgar, ensure internal display functional
following S3 resume under Windows 10.
Change-Id: I471c44e8ba4514e4a2ddf6739109b759145598ed
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Mirrors addition to Braswell SoC in commit d3d0f07.
Test: build/boot Windows 10 on Baytrail ChromeOS device, verify Windows shows
virtualization as enabled.
Change-Id: Ia1fafa73325814fed30b2ac91290b682dd8eab04
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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It seems they are not included anywhere, Jenkins?
Change-Id: I629cdeb337fce381c69bd1ba0520e524ccdd90dd
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/26756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The GPIO pin map for CNL-H does not match with the OS expected
pin numbers. This has been updated to match what is used by the
Linux kernel pinctrl driver and the pad base has been set for
the GPIO groups to match the sparse GPIO map used by the kernel.
I do not have CNL-H hardware to test this so it is verified against
the kernel driver at drivers/pinctrl/intel/pinctrl-cannonlake.c
Change-Id: Ife7d3090d654b0b88c6911befa08bf6abd4f2ff9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30134
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The GPIO drivers in Windows and Linux for the Cannonlake CPU
have a sparse GPIO map and do not allocate pins contiguously.
Each GPIO group is allocated as 32 pads regardless of whether
the hardware actually has that many in the group.
It appears this originated with a bug in Windows/UEFI and was
carried over to Linux in order to work with existing firmware:
https://lore.kernel.org/patchwork/patch/855244/
In order to support using ACPI GPIOs it is necessary for coreboot
to be compatible with this implementation. The GPIO groups that
are usable by the OS are declared with a pad base which is then
used to compute the number for ACPI GPIOs.
BUG=b:120686247
TEST=tested with write protect GPIO on sarien board. Before this
change the ACPI pin number was 220 which did not correspond to the
pin number in Linux. After this change the ACPI number is 303,
which maps to the correct GPIO in Linux. Now the GPIO value reported
by the kernel changes when the WP pin is toggled in hardware.
Change-Id: I4f1a9e118d7e48f2445ccbb62a12a22e9a832c51
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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In some situations the GPIO pad numbers used by the OS are not
contiguous and coreboot must provide a way for ACPI to provide
the expected GPIO number to the OS.
To do this each GPIO group can now have a pad base value, which
will be used as the starting pin number for this group and it
is added to the relative pin number of this GPIO to compute the
ACPI pin number for a particular GPIO.
By default this change has no effect because the existing uses
of INTEL_GPP() will set the pad base to PAD_BASE_NONE and the
GPIO number is used as the ACPI pin number without translation.
BUG=b:120686247
TEST=tested on a sarien(cannonlake) board
Change-Id: I25f73df45ffae18c5721a00ca230a6b07c250bab
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30131
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch introduces 3 helper function for cpuid(1) :
1. cpu_get_cpuid() -> to get processor id (from cpuid.eax)
2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx)
3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx)
Above 3 helper functions are targeted to replace majority of cpuid(1)
references.
Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Correct typo of 'resource'
BUG=N/A
TEST=N/A
Change-Id: I79dde87007759b7cab92061df37fd3a19d5e3d1f
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/30125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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This implementation configures below parameters:
1. Enable SaGv, isclk.
2. Set Pcie rootport enable, Clock source usage and clkreq.
3. Configure SATA and LPSS controllers parameters.
4. Enable CNVI controller, configure Wifi end device under PCIE RP1.
5. Add TPM device support under GSPI1.
Change-Id: I585e82799eea0bad19ad2c94d6b4b3024f930ed4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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The kernel GPIO driver only expects some GPIO communities to be exported
in the _CRS and it will not work correctly if the other communities are
exported.
CNL-LP: GPIO communities 0, 1, 4
CNL-H: GPIO communities 0, 1, 3, 4
Additionally one of the pin offset values was incorrect in GPIO
community 1 for CNL-LP. This doesn't have any specific failure mode but
it was found when auditing the GPIO code.
Details of the kernel expected map can be found in the linux kernel at
drivers/pinctrl/intel/pinctrl-cannonlake.c
BUG=b:120686247
TEST=check /sys/kernel/debug/pinctrl/INT34BB:00/pins to ensure that
pins >= 198 are not reading all zeros for the pin config registers.
Change-Id: Ie1a2f3b9f9f4b24a9fc57e468dee50e99753912f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Recently there has been a change to print ME version. But the stage at
which the version is printed causes the HECI device to remain in D0 state.
This in turn prevents the SoC from entering S0ix state.
This change moves printing ME version a little earlier so that the HECI
device is put into D0i3 state by FSP and the SoC can enter S0ix state
successfully.
BRANCH=octopus
BUG=b:120571529
TEST=Ensure that the ME version gets printed in BIOS logs. Ensure that
the device boots to ChromeOS. Ensure that the device enters S0ix
successfully(using suspend_stress_test -c 25).
Change-Id: I85bc45003a040c8347f929457792d78a9a077c6c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The input clock for the I2C controllers was set at 133MHz but should
really be 216MHz according to the kernel:
https://patchwork.kernel.org/patch/10408729/
"Intel Cannon Lake PCH has much higher 216 MHz input clock to LPSS I2C
than Sunrisepoint which uses 120 MHz. Preliminary information was that
both share the same clock rate but actual silicon implements elevated
rate for better support for 3.4 MHz high-speed I2C."
This change was tested on a sarien board where an I2C trackpad that was
measuring ~700MHz on I2C and is now measuring ~380MHz.
Change-Id: I792d1f013da5538a2b8157e2f99b754ca7b6bf70
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30061
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As part of the memory mapped BIOS region is covered by SRAM, check
that CBFS always fits the effectively mapped region of flash. This
is usually taken care of by reserving the SRAM range in the FMAP
(e.g. as BIOS_UNUSABLE), but can be missed.
Change-Id: If5a5b553ad4853723bf13349c809c4f6154aa5f2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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ISA timer is not configured.
Add call setup_i8254().
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: If45c4975d147f28a456198ea290efba1c8b0464b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Use common code to tear down CAR.
Change-Id: I62a70ae35fe92808f180f2b5f21c5899a96c2c16
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I77e375a2ff2fbf1be4ded922195b80b49ffa4cc5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29929
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch does the following:
- improve the style by removing tabs in front of jmp addresses
- Make the code for zeroing variable MTRR more readable (copied from
cpu/intel/car)
- Fetch PHYSMASK high from cpuid instead of Kconfig
Change-Id: I6ba67bb8b049c3f25b856f6ebb1399d275764f54
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This does the following:
- Reuse the cpu/intel/car/non-evict CAR setup and exit.
- Use postcar_frame functions to set up the postcar frame
Change-Id: I428832a2d7e46ce61a7f9bd498b609feb4518eb0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of SMMSTORE_APM_CNT use APM_CNT_SMMSTORE and define it in
cpu/x86/smm.h
Change-Id: Iabc0c9662284ed3ac2933001e64524011a5bf420
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30023
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Instead of ELOG_GSMI_APM_CNT use APM_CNT_ELOG_GSMI and define it in
cpu/x86/smm.h
Change-Id: I3a3e2f823c91b475d1e15b8c20e9cf5f3fd9de83
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30022
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Needed to fix up FSP-S bug on Apollo Lake.
Change-Id: If09fee07debb1f0de840b0c0bd7a65d338665f7c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Cache BIOS region can boost boot performance, however it can't be over
16MB, according to processor EDS vol1(Apollolake/Skylake/WhiskeyLake),
FLASH+APIC LT will be less than 20MB under 4G. Set the maxiam to 16GB
to save numbers of mtrr entries.
BUG=b:119267832
TEST=Build and boot up fine on whiskeylake rvp platform.
Change-Id: I46a47c8bf66b14fb2fcb7b6b1d30d02886c450a4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add the ACPI device names for the USB ports to match what
is in the DSDT so USB ports can be defined in the SSDT.
Change-Id: Ibb323bbd324811fa3178b0cba3d7f0a315169486
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Increase the bootblock size to 48K to match skylake. With UART
enabled we are very near the 32K limit, and with upcoming changes
to add USB devices in devicetree for a cannonlake board it is over
the current 32K limit.
Change-Id: I155cb0a6af1746af6833fa9f35c2ea6fe0bc709f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Define the constants that DPTF expects from the SOC in order to
use the common DPTF ACPI code. For cannonlake this indicates
the CPU device is called B0D4 and is at PCI address 00:04.0.
Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29759
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a method to convert from 1/10 Kelvin to Celsius. This
is useful for EC devices where the sensor temperature are
stored in Celsius instead of Kelvin.
Change-Id: I6b1154f5ba13416131a029966d6d5c1598904881
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29758
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to support using the common ACPI code on more platforms
than just Apollo Lake the DPTF code needs to be told what the
PCI address is for the CPU thermal device.
Change-Id: I638f2387330bbc42f64eb0fb676ee32c5df6572e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Backlight control of internal panels likely won't work as configuration
for that seems absent in coreboot. Also, libgfxinit doesn't support any
MIPI/DSI connections, yet, and neither Gemini Lake.
TEST=Booted work-in-progress port kontron/mal10 with VGA text and
linear framebuffer modes. DP display came up.
Change-Id: I7b111f1cdac4d18f2fc3089f57aebf3ad1739e5d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds support to print ME version if UART_DEBUG is
enabled. Check for UART_DEBUG is necessary because talking to ME to
get the firmware version adds ~0.6 seconds to boot time.
TEST=Verified on octopus that ME version printed is correct.
Change-Id: I41217371558da1af694a2705e005429155d62838
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29989
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make build still pass in case of no FsptUpd.h available.
BUG=N/A
TEST=Delete FsptUpd.h and build pass wihtout FSP_CAR set.
Change-Id: I3936d3deb8b079bd4db11e444f6bb7f9605520dc
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Sync the FSP settings with what coreboot does. Why both FSP and coreboot
configure this redundantly stays a secret.
TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC
works correctly now, but was confused by the wrong settings before
because the FSP defaults allowed to disable the LPC clock.
Change-Id: Id1c7180f460678bf0f9458228591050dd628c052
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: David Guckian
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Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: I01e4397b9a1c15eff4b856cbc697fa2b4bc9761f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: If482c64e7133cc6d82472d121ac138fc1b60a183
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: David Guckian
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Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: Id64f9857bbd7db520c94de949db8f823f71d6dae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Use acpigen_write_processor_cnot to implement notifications to the CPU.
Automatically generate \PPKG in SSDT.
Change-Id: I79d2eed9b89b420554ce10d1fc0f151b1872afe2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: I93c11e89da34c5432c6ce0415998b47bad339763
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29889
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: Ifb5a5c1255f9a922063293bf430e849909468eaf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29888
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: I182585fd09e4ce848c860d00eb612e8f5fdde35e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29884
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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