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Clang generates R_X86_64_32S symbols that get truncated.
TESTED:
- prodrive/hermes boots with GCC and clang
- MTRR are properly cleared (tested by filling in both
MTRR_FIX_64K_00000 and MTRR_FIX_4K_F8000 before clearing)
Change-Id: I6a5139f7029b6f35b44377f105dded06f6d9cbf9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The patch drops the unreferenced DP related timeout macros.
TEST=Build code for Rex
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3f4c7733a92d1b7cb107410fedaca20ede040050
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This fixes the following error:
In file included from src/mainboard/siemens/mc_apl1/dsdt.asl:21:
src/soc/intel/apollolake/acpi/northbridge.asl:15:12: warning: '/*' within block comment [-Wcomment]
PXEN, 1, /* Enable */
^
Change-Id: I1173eed69847f4c3b307ce96d76fb7185dc2f85c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70767
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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This was done previously for ADL. moving the code to common so
it can be leveraged for other platforms (e.g. MTL)
TEST=Built and tested on anahera by verifying SSDT contents
Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Change-Id: I6f1d7625eb457084ba893b25518fdfdb59cf64db
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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As per PCI Express Base Specification 5.0 section 5.4.1.3 ASPM
Configuration
+-----------------------+-------------------------------+
| Field Description | ASPM Support |
+-----------------------+-------------------------------+
| 00b | No ASPM support |
+-----------------------+-------------------------------+
| 01b | L0s Supported |
+-----------------------+-------------------------------+
| 10b | L1 Supported |
+-----------------------+-------------------------------+
| 11b | L0s and L1 Supported |
+-----------------------+-------------------------------+
100b aka 0x4 is added by FSP to allow auto configuration (to avoid
conflicting with the PCI specification defined values).
Additionally, changed enum definition which is now meeting the FSP expectations better.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8c9055f721e144f2ff5055e5f99ea641efc4d268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70719
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable L1 substates for PCIe compliance test mode in order to get
continuous clock output.
BUG=b:235863379
TEST=Boot in compliance mode, check FSP settings
Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Change-Id: I2a3b313425e00fe11f616d964f825baaef463c71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70165
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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The patch adds helper function to get the DP mode.
TEST=Build the code for Rex
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I02ed1f818e77c37ead8ce962fa12fddfdc8efeb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch drops the redundant macro to define CPU BCLK and instead
uses `CPU_BCLK_MHZ` config to calculate the
`smbios_cpu_get_max_speed_mhz`.
TEST=Able to see max cpu speed is correct in smbios table while trying
on Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5167f3a513c074b9e6986c960e1bcced65f1264c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70676
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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This patch drops NEM support from MTL and enables eNEM support.
BUG=b:217130861
TEST=Able to build and boot Google/Rex in eNEM mode.
Change-Id: I6ef915ec0caf0d95b488602950b0b25958ec4cbd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70673
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch combines all required configs under one umbrella config
named `METEORLAKE_CAR_ENHANCED_NEM`.
MTL SoC to select this config if default NEM (INTEL_CAR_NEM) is not
selected.
BUG=b:217130861
TEST=Able to build and boot Google/Rex.
Change-Id: Iceab7cdf2973f3858d4aa83fb431ba832c0868d6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70672
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch moves all required TCSS related configs under one umbrella
config named `SOC_INTEL_METEORLAKE_TCSS_USB4_SUPPORT`. This effort will
help in future to deselect the TCSS support for MTL SoC SKUs.
TEST=Able to build and boot Google/Rex.
Change-Id: Id86e52842d2f8ab4dbec4a8776791e1266b94298
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70671
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch calls into a helper function to fill `2nd microcode loading
FSP UPD` if FSP is running CPU feature programming.
This patch is backported from
commit fad1cb062e29c5e3a5bcfb6b67c3ce01ed765254 (soc/intel/alderlake:
Fill ucode loading UPD if USE_FSP_MP_INIT enable).
Change-Id: Id8c8bfd844b3213cc260df20c359b0b1437e3e28
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70599
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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This patch drops deprecated FSP UPD `SkipMpInit` as Intel MTL FSP
doesn't like to allow an option for boot firmware to perform CPU feature
programming being independent of FSP.
Change-Id: I6447937838ab91551d172936cbb4201ea86a614b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70557
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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This patch drops enable_bios_reset_cpl() as FSP sets the BIOS Reset
CPL before performing Graphics PM init (as part of FSP-S), hence,
enable_bios_reset_cpl() function getting called inside systemagent.c
is meaningless.
Also, drop 1ms delay after setting the BIOS reset CPL.
This patch is backported from
commit 3f980ca7be36339ad2cb5700bad0658643966cf2 (soc/intel/alderlake:
Drop enable_bios_reset_cpl() function).
Change-Id: Ia31867153b3b5f132c393a605c44616acfd7a34b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70556
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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Drops the `FIXME` comment and relevant code as this patch enables
VMX and VTD.
This patch also fixes the problem of additional reboot on every warm
boot due to overriding the CPU soft-strap.
TEST=No extra reboot seen while issuing warm reset from kernel
console.
without this patch:
950:calling FspMemoryInit 1,225,259 (20,537)
951:returning from FspMemoryInit 10,334,707 (9, 109,447)
with this patch:
950:calling FspMemoryInit 1,225,259 (20,537)
951:returning from FspMemoryInit 1,334,707 (109,447)
Change-Id: Ib130698e7255876c5a12abc93dd7d8a34dfae968
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70553
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `Store (a, b)` with `b = a`.
Change-Id: I2dd154c3d4e152a14783ea82e08a7d1257abebc3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Replace `Store (a, b)` with `b = a`.
Change-Id: I9ddb71d93781c813a69dc72ce0589ffaea7b64c7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Replace `Store (a, b)` with `b = a`.
Change-Id: I12560d151d26186e1f4eb0165aa8cef33b7a16aa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Replace `Store (a, b)` with `b = a`.
Change-Id: Ic171f3343bb35e43be5fdb50c5c926eede6a1d93
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Add two macros:
- PAD_CFG_NF_OWNERSHIP()
- PAD_CFG_GPIO_OWNERSHIP()
to support setting the Host Software Ownership (own) fields.
Signed-off-by: lichenchen.carl <lichenchen.carl@bytedance.com>
Change-Id: Ia3f2ad8658b751156456b69366fa4b1badb8b595
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70421
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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This patch skips sending CONN IPC command to PMC if system is resuming
from S3.
Sending CONN IPC command as part of `tcss_configure_dp_mode()` function
results into ERROR while system is resuming from S3.
Additionally, skip `configure_aux_bias_pads()` during S3 resume.
BUG=b:260984500
TEST=Able to test on Google/Rex.
Without this patch:
[ERROR] pmc_send_ipc_cmd status: fatal
[ERROR] Port 1 connect request failed
[SPEW ] [TCSS] TcssInit() - End
With this patch:
No error seen during S3 resume.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1dab7dc8b4ad76ca0c9630456803c1b9a320fe40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Change-Id: I89bfbab7850dd9bd29ca2097ee2efce058720ca7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change-Id: I80b1535b86c7fc05354404d628a0a527a6701498
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change-Id: I6168be71913d00eb59d38dd4c5cf8f9c7f7ab678
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change-Id: Iab3215487d0a19e0791a78f953a8545dfae3d2dc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change-Id: Ic40f1e935b244f39fa3c1322e5128465c57f5e26
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70579
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change-Id: I3062e5b8a0524059b9695dfd32254c5c53598925
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70578
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Replace `Multiply (a, b, c)` with `c = a * b`.
Change-Id: I97332e3008ed2e26a75c067baffdabfc7cfcf65f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Replace `Subtract (a, b)` with `a - b`.
Change-Id: I77028c17dcd7925a392d56488d34090837d660f2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Replace `Subtract (a, b, c)` with `c = a - b`.
Change-Id: If6455ab2c91619f884abae227f1ac2e2c2af6ba9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Replace `Add (a, b)` with `a + b`.
Change-Id: I0b7f22acf153fe02b471c196f8161fc0fa5a1450
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70624
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Replace `Add (a, b, c)` with `c = a + b`, respectively `a += b` where
possible.
Change-Id: I96390f565d6c1ca0f4e06db9ad07af784051650c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70622
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Replace `LNotEqual (a, b)` with `a != b`.
Change-Id: Ia1bd22a62ec2868324a88400e27ed52c9f169751
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70619
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `LEqual (a, b)` with `a == b`.
Change-Id: I7b74d026d0800df647fb0c981fa7865be492d3ac
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70590
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `LEqual (a, b)` with `a == b`.
Change-Id: I9d50ddcb4427774681aedba945079f5d04401f07
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70589
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `LEqual (a, b)` with `a == b`.
Change-Id: I36137cbf63a36e68480029058f4426ed80ff6e3e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70588
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `Decrement (a)` with `a--`.
Change-Id: I5c9290aaa9fc969368d5934e4f48a75d915ca5ff
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add the HIDs that Windows uses for the DPTF driver.
Change-Id: Ic0cb4a45b5ebaf777a09bed1e5836e8afd873657
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66013
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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HEC1 and SRAM are defined in src/soc/intel/alderlake/chipset.cb:
device pci 16.0 alias heci1 on end
device pci 14.2 alias shared_sram off end
This patch adds entries for these devices in DSDT to prevent "AE_NOT_FOUND" errors from kernel
TEST=Built and tested on brya to confirm errors are not seen.
BUG=b:260258765
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: Ifd9c509e82ccf02a7801d51513597fe2e5d9e631
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70454
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The patch enables CPPCv3 support for Intel Meteor Lake which is based
on hybrid core architecture.
TEST=Build code for Rex.
Change-Id: Iddf15f01a401eedf695f2dd07fbee0b643d143e2
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70511
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Changes include:
- Add config for Meteor Lake SoC to select FirmwareVersionInfo.h
using 'DISPLAY_FSP_VERSION_INFO_2'
BUG=b:260183604
TEST=Verified Google/Rex0 build with all the patch in relation chain
and verified the version output prints no junk data.
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Change-Id: I789db9d280c45639eca6ceafea65b96a93a395cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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|
BUG=b:259716145
TEST=Dump SSDT and see that _PRW and _DSD for CNVi device contains
the value from the devicetree on google/redrix.
Before:
Scope (\_SB.PCI0.WFA3)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x6D,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
})
...
}
After:
Scope (\_SB.PCI0.CNVW)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x6D,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
})
...
}
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ia4ffedcb53afe350694eb03a144d12f714190cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70447
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
"Argh! Lack of consistency! UNACCEPTABLE!" - Emotions
Swap the position of two lines so that defaults are listed in
alphabetical order according to the PCH type: M, N, P, S.
Change-Id: I82a23eb2b5036d3b7ec6766ae9891078f1caab69
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70522
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch moves TCSS firmware latency related macros from SoC
specific tcss.h to IA common tcss.h
Additionally, ensure other structure definitions belonging to the
IA common code tcss.h are not causing compilation issues for ASL files
(due to including FW latency macros) hence, guarded against
`!defined(__ACPI__)`.
TEST=Able to build and boot Google/Rex and Google/Kano.
Change-Id: Id51545ef714979c6ba09a2b468231b1f4bab0be7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70487
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch moves TCSS firmware latency related macros from
`tcss_pcierp.asl` to SoC specific `tcss.h`.
TEST=Able to build and boot Google/Volteer.
Change-Id: I96416f3b68d853c9a5a44c499719f154aa15f0ca
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70486
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch moves TCSS firmware latency related macros from
`tcss_pcierp.asl` to SoC specific `tcss.h`.
TEST=Able to build and boot Google/Kano.
Change-Id: I96db2dbf050c8f09e4d9c4018a2caa286f7ef1d1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70485
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch fixes typo mistake `Pyhsical` -> `Physical`.
Change-Id: I211a3a710f5b63c4c16d4105f2eac50c992cfcf2
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70484
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch updates DPTF participants' ACPI IDs based on the Intel
Meteor Lake Reference Code.
TEST=Able to build and boot Google/Rex.
Change-Id: Iccc7f3cad26a028a3b11d5e5e761bbefa7776583
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70482
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The `soc_read_pmc_base()` function returns an `uintptr_t`, which
is then casted to a pointer type for use with `read32()` and/or
`write32()`. But since commit b324df6a540d ("arch/x86:
Provide readXp/writeXp helpers in arch/mmio.h"), the
`read32p()` and `write32p()` functions live in `arch/mmio.h`.
These functions use the `uintptr_t type for the address parameter
instead of a pointer type, and using them with the
`soc_read_pmc_base()` function allows dropping the casts to pointer.
BUG=none
TEST=Build and Boot verified on google/rex
Port of 'commit f585c6eeeafb ("soc/intel: Drop casts
around `soc_read_pmc_base()`")'
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I914190f2d2d0507c84b19340159990f9b62ce101
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70272
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way
to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer`
CMOS option to allow enabling and disabling the 8254 timer without
having to rebuild and reflash coreboot. If options are not enabled or
the option is missing in cmos.layout, the Kconfig setting is used.
BUG=none
TEST=Build and Boot verified on google/rex
Port of 'commit bc35bed18eba ("soc/intel/*: Allow configuring
8254 timer via CMOS")'
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ibf6c43ddecb3da325c22228205243bb6af00d1d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70423
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch fixes the `unknown` voltage field issue in processor SMBIOS
table.
This patch is backported from
commit 30e8fc1f4e7d4e79b1403acd3679ce08598687c3 (soc/intel/alderlake:
Fix unknown voltage in SMBIOS)
TEST=Able to see meaningful voltage data in the SMBIOS table.
Without this patch:
localhost ~ # dmidecode -t 4
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x0004, DMI type 4, 48 bytes
Processor Information
Socket Designation: CPU0
Type: Central Processor
Family: Pentium Pro
...
Voltage: Unknown
With this patch:
localhost ~ # dmidecode -t 4
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x0004, DMI type 4, 48 bytes
Processor Information
Socket Designation: CPU0
Type: Central Processor
Family: Pentium Pro
...
Voltage: 0.8 V
Change-Id: I0cd7c1e3c0746309600e4480f4822a4d72147041
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70424
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The validation process verifies that hardware components comply with
the standard hardware specifications. For instance, PCI express
implementation must comply with the hardware PCIe specification
requirements: Electrical, Configuration, Link Protocol and Transaction
Protocol. To perform these tests the hardware must be configured in a
particular state: some feature related to power management need to be
turned off, hot plug should be enabled...
This patch sets the appropriate FSP Updateable Product Data flags to
get the hardware in the proper configuration:
- Enable PCIe hotplug on all ports
- Set clock sources to run free
- Set the FSP compliance test mode flag
This patch is backported from
commit 096ce1444ec7fa204f331a75c2ac9d00ea00bf12 (soc/intel/alderlake:
Support PCIe hardware compliance test mode)
Change-Id: Idd7a1adf0f53b014093ba70fee599dbb7887a0fc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70416
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When an enabled root port without pcie_rp clock being specified, the
empty structure provides invalid info, which indicates '0' is the
clock source and request. If a root port does not use clock source, it
should still need to provide pcie_rp clock structure with flags set to
PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it
is considered that pcie_rp clock structure is not provided for that
root port.
Add check and skip PCIe CLKSRC programming without a clock structure.
In addition, a root port can not use a free running clock or clock set
to LAN.
Note that ClockUsage is either free running clock, LAN clock, or the
root port number which consumes the clock.
This patch is backported from
commit edf71a08b4cb7bd8683344aa4ad301f1526289c2 (soc/intel/alderlake:
Skip PCIe source clock assignment if incorrect)
Change-Id: Ie9179880a57796d8595874325203280590d7ee9d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70415
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
In some cases, partner may assign same clkreq on more than one devices.
This could happen when one device is in baseboard dev tree and another
one is in override dev tree.
This change adds a clkreq overlap check and shows a warning message.
This patch is backported from
commit ff553ba8b3d39fba6f1ed9b8e3513fc5412ba5a9 (soc/intel/alderlake:
Check clkreq overlap)
Change-Id: Ifc1c57578eca376685196ad497d9db825d63aa76
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70414
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
<device/mmio.h>` chain-include `<arch/mmio.h>:
https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes
Also sort includes while on it.
Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Introduce the mainboard-defined `mainboard_dimm_slot_exists()` function
to allow creating SMBIOS type 17 entries for unpopulated DIMM slots.
Change-Id: I1d9c41dd7d981842ca6f0294d9e6b0fedc0c98e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64036
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Found using 'Wmissing-include-dirs' command option.
Change-Id: Ie079dcf8c1e662ce6ef068befa43dfe90c89edd1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70395
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch adds SLP_S0 residency registers and enable LPIT support.
Added `SLP_S0_RES` in Meteor Lake pmc.c as per MTL EDS document.
TEST=Able to see LPIT Table after booting Google/Rex to ChromeOS.
localhost /home # ls -lt /sys/firmware/acpi/tables/
-r--------. 1 root root 254 Dec 5 06:59 APIC
-r--------. 1 root root 84 Dec 5 06:59 DBG2
-r--------. 1 root root 21819 Dec 5 06:59 DSDT
-r--------. 1 root root 276 Dec 5 06:59 FACP
-r--------. 1 root root 64 Dec 5 06:59 FACS
-r--------. 1 root root 56 Dec 5 06:59 HPET
-r--------. 1 root root 148 Dec 5 06:59 LPIT
-r--------. 1 root root 60 Dec 5 06:59 MCFG
-r--------. 1 root root 21078 Dec 5 06:59 SSDT
-r--------. 1 root root 76 Dec 5 06:59 TPM2
Change-Id: Id2d16d8514ce4b7867c9395617ad3ac73b1b9989
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70351
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch implements SoC overrides to set CPU privilege level for
Meteor Lake SoC.
Change-Id: I33794f51e57dd8e0ffe61dfd2f91c6ef3f9187c9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70352
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch adds missing ASL entry for GSPI2 device.
Change-Id: I8f8410947b77d1a9bab2fa5929f30c803a78266d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70354
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This avoids the need to hardcode the IOAPIC ID.
Change-Id: I0965b511e71c58f1c31433bc54595a5fabb1c206
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70268
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: I74f943e9b616458a16aa13c29706cf1551fcbbb2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
There are four requirements for the SMI to hit a printk()
this commit now removes.
Build must have DEBUG_SMI=y, otherwise any printk() is a no-op
inside SMM.
ASL must have a TRAP() with argument 0x99 or 0x32 for SMIF value.
Platform needs to have IO Trap #3 enabled at IO 0x800.
The SMI monitor must call io_trap_handler for IO Trap #3.
At the moment, only getac/p470 would meet the above criteria
with TRAP(0x32) in its DSDT _INI method. The ASL ignores any
return value of TRAP() calls made.
A mainboard IO trap handler should have precedence over
a southbridge IO trap handler. At the moment we seem to have
no cases of the latter to support, so remove the latter.
Change-Id: I3a3298c8d9814db8464fbf7444c6e0e6ac6ac008
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Shift is done in multiples of 8 (1 << 3) bits.
It was fixed already for i82801ix/jx.
Change-Id: I5e1c2b3bf4ba68f34eb43e59fe783d5cd6e0a39a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I83d05ce0b26b01fdfc95d1442a4c930ed77bf25c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
This is more robust than hardcoding whathever FSP has set up and is a
lot less code.
Change-Id: I6423ddc139d742879d791b054ea082768749c0a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70265
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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SOC_INTEL_CSE_SEND_EOP_EARLY breaks soft ME disable, which works using
a HECI message that needs to be sent before EOP. Make the option
configurable to allow soft ME disable on alderlake.
Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This replaces the mechanism with --ext-win-base --ext-win-size with a
more generic mechanism where cbfstool can be provided with an arbitrary
memory map.
This will be useful for AMD platforms with flash sizes larger than 16M
where only the lower 16M half gets memory mapped below 4G. Also on Intel
system the IFD allows for a memory map where the "top of flash" !=
"below 4G". This is for instance the case by default on Intel APL.
TEST: google/brya build for chromeos which used --ext-win-base remains
the same after this change with BUILD_TIMELESS=1.
Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Do not hide UARTs in ACPI mode from the OS, as this prevents using them
on at least Windows. Currently, the driver is only used on the Prodrive
Hermes mainboard.
Change-Id: I01bdccff1b11e1862970c924fd5fc7718a2d6ce9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70155
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The `HyperThreading` FSP UPD is set according to the `hyper_threading`
CMOS option using the value of the `FSP_HYPERTHREADING` Kconfig option
as fallback in case options are disabled or otherwise unavailable. The
`HyperThreadingDisable` devicetree setting isn't used by any mainboard
but it overwrites the value of the FSP UPD. Remove it so that the CMOS
and Kconfig options work as intended.
Change-Id: Iea60b89f6f970eb9aee8c7bec026ab5c2df30205
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69534
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:259716145
TEST=Verified SSDT on google/rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ib57dea9b16e4590ca2d75ac1512fdaf773ec50f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70065
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The patch adds timestamp around cse_fw_sync().
BUG=none
TEST=Verified on rex, cbmem -t:
948:starting CSE firmware sync 1,340,551 (50,657)
949:finished CSE firmware sync 1,379,348 (38,797)
Port of 'commit b647e35119c1 ("soc/intel/alderlake: Add timestamp
for cse_fw_sync")'
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I6cfbf84018e312fbf9482f0fba05b444603cd4b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70172
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The patch gets the cpu and pch's tracehub mode from the debug area
of the Descriptor Region and updates the respective UPDs.
TEST=Build, verify the tracehub mode values.
Update CPU' and PCH's Trace Hub modes:
img=coreboot.rom
printf '\x01' | dd of=$img bs=1 seek=3841 count=1 conv=notrunc
printf '\x01' | dd of=$img bs=1 seek=3842 count=1 conv=notrunc
Check coreboot logs:
[DEBUG] rt_debug: CPU TraceHub Mode: 1 PCH Tracehub Mode: 1
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I088b5d1f5569aacbf79834b44372702f8d3a189f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
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|
The devices in the list that was introduced in commit c66ea985776
("soc/intel/alderlake: provide a list of D-states to enter
LPM") are all internal. This CL skips the external buses (which caused
the addition of packages to non-existant paths such as
"_SB.PCI0.RP1.MCHC", and warnings from the kernel)
BUG=b:231582182
TEST=Built and tested on anahera by verifying SSDT contents
Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70163
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch refactors the `pmc_lockdown_cfg()` to remove the helper
functions and uses the `setbits32` function to enforce bit locking
as applicable.
This patch also locks PMC features like:
1. Debug mode configuration and host read access to PMC XRAM.
2. PMC soft strap message interface.
3. PMC static function.
and then calls into the PMC IPC function that informs about PCI
enumeration.
Port of -
1. commit 2eec87a553ec ("soc/intel/alderlake: Refactor
`pmc_lockdown_cfg` function")
2. commit bae4a0b5a1e4 ("soc/intel/alderlake: Implement PMC
feature lock")
3. commit c2570dc99800 ("soc/intel/alderlake: Implement PMC
soft strap interface lock")
4. commit f021952c4067 ("soc/intel/alderlake: Implement PMC
static function lock")
5. commit 457891415380 ("soc/intel/alderlake: Call into PMC
IPC to inform PCI enumeration done")
BUG=none
TEST=Boot to OS on google/rex.
Register values in OS -
# busybox devmem 0xfe0018d4 32 #bit31
0x80000000
# busybox devmem 0xfe001024 32 #bit21,18,17,4
0x00362610
# busybox devmem 0xfe001818 32 #bit27,22
0x2B4F0004
# busybox devmem 0xfe00104c 32 #bit0
0x00000001
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I3622748d8fecef69c60bb3fe9bfe68fc126764b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70132
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch selects SOC_INTEL_CSE_SEND_EOP_LATE config to let IA
common code to skip sending CSE EOP cmd during finalize operation
rather uses boot state machine (either payload load or payload boot)
to delay in sending EOP cmd to CSE.
BUG=b:260041679
TEST=Able to boot to Google/Rex with this patch and observed ~150ms
savings in boot time
Without this patch:
942:before sending EOP to ME 1,795,702 (354)
943:after sending EOP to ME 1,950,526 (154,824)
With this patch:
942:before sending EOP to ME 2,051,406 (35,484)
943:after sending EOP to ME 2,057,583 (6,177)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7d44d5eff890ac78e3075d49cc249f740686dd0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69999
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch allows to send late EOP cmd to CSE (after CSE .final)
using boot state machine (either BS_PAYLOAD_BOOT or BS_PAYLOAD_LOAD)
if the SoC user selects SOC_INTEL_CSE_SEND_EOP_LATE config.
Rename `set_cse_end_of_post()` to `send_cse_eop_with_late_finalize()`
to make the function name more meaningful with its operation.
BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
This patch creates an API that can perform essential CSE operation
after sending the late EOP command to the CSE and prior booting to OS.
Lists of operation are
- Perform global reset lock
- Put HECI1 to D0i3 and disable the HECI1 if the user selects
- Set D0I3 for all HECI devices.
BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69977
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This patch refactors common code to allow cse_final() function to send
EOP cmd if the SoC user selects `SOC_INTEL_CSE_SET_EOP` kconfig.
This patch helps cse_final_ready_to_boot() and
cse_final_end_of_firmware() function for being meaningful with its
operation and let cse_final() being that outer layer to perform three
operations based on the selected kconfig.
1. send cse eop command
2. perform cse_final_ready_to_boot() operations
3. perform cse_final_end_of_firmware() operations
Additionally, ensures the platform that choose to send EOP late
(like JSL and TGL) is not being impacted due to this code refactoring
hence, skip calling into CSE.final if SoC selects
`SOC_INTEL_CSE_SEND_EOP_LATE` config.
BUG=b:260041679
TEST=Able to send EOP command successfully for Google/Taeko.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I412291c9378011509d3825f9b01e81bfced53303
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69975
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Presently, coreboot supports two instances of sending EOP cmd to
the Intel CSE.
1. Sending EOP cmd to CSE during `.final` operation from cse pci driver.
2. Starting with Alder Lake, the recommendation was to send EOP to CSE
earlier than CSE `.final` operation. Since then it's referred to as
`Sending EOP Early`. This method helped to save the CSE EOP
response time significantly.
During Meteor Lake platform, CSE EOP response time has become
non-deterministic and we have figured that sending EOP command later
than CSE .final operation is actually helping to optimize the boot time
significantly (around ~150ms savings compared to sending from `.final`
ops and ~5sec compared to sending CSE early).
Hence, this patch intended to create yet another kconfig for sending
CSE late (specifically after `.final` operation). The idea for this
newer config is to use the boot state machine for sending CSE EOP cmd.
The patch train in this series would add the specific changes to allow
sending EOP late and perform other essential operations required prior
booting to OS as coreboot decided to skip calling into FSP Notify phase.
Starting with Jasper Lake, coreboot sends EOP before loading payload
hence, this config is applicable for those platforms.
The current plan is that Intel Jasper Lake, Tiger Lake and Meteor Lake
platform will select this newer config from SoC code.
BUG=b:260041679
TEST=Able to send EOP command successfully for Google/Taeko.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iea512cd5b79d61dd5d5a962079baf525027c831f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69976
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
This patch ensures dropping of the duplicate macro introduced with
'commit 9e4488ab06fd9c4 ("soc/intel/{adl,cmn}: Add/Remove LTR
disqualification for UFS")'
`PCH_PWRM_BASE_SIZE` macro represents the size of the PMC MMIO range
which can be used as is even in ufs.asl file.
BUG=b:252975357
TEST=Build and boot nirwen and see no issues in PLT runs.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic967c609e1330eca1b9e1143e7efd78db011f317
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70180
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
The patch logs CSE RO's write protection information for Meteor Lake
platform. As part of write protection information, coreboot logs status
on CSE RO write protection and range. Also, logs error message if EOM
is disabled, and write protection for CSE RO is not enabled.
Port of commit abe0d810f009 ("soc/intel/alderlake: Log CSE RO write
protection info for ADL").
BUG=none
TEST=Verify the write protection details on google/rex.
Excerpt from google/rex coreboot log:
[DEBUG] ME: WP for RO is enabled : YES
[DEBUG] ME: RO write protection scope - Start=0x4000, End=0x396FFF
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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|
BUG=none
TEST=Build and boot to google/rex.
Excerpt from google/rex coreboot log:
[DEBUG] ME: Manufacturing Mode : YES
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I8d2de3365126ba618c987c412c4e9784012f9e0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Change-Id: Ic64625bdaf8c4e9f8a5c1c22cece7f4070012da7
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69903
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 095c931cf12924da9011b47aa64f4a6f11d89f13.
Previously cpu_info() was implemented with a struct on top of an
aligned stack. As FSP changed the stack value cpu_info() could not be
used in FSP context (which PPI is). Now cpu_info() uses GDT segments,
which FSP does not touch so it can be used.
This also exports cpu_infos from cpu.c as it's a convenient way to get
the struct device * for a certain index.
TESTED on aldrvp: FSP-S works and is able to run code on APs.
Change-Id: I3a40156ba275b572d7d1913d8c17c24b4c8f6d78
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69509
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The coreboot CPU index for a lapic is arbitrary: it depends on which
CPU obtains a spinlock first. Simply using an increasing index will
result in consistent ACPI tables across each boot.
Change-Id: Iaaaef213b32b33e3ec9f4874d576896c2335211c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69510
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:259716145
TEST=Verified SSDT on google/rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I921b06e8d35ddac0bc8175b13a33c84515b282a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70028
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Name a variable based on its utility. `is_external` variable adds
`ExternalFacingPort` _DSD property to an ACPI device hence
rename it to `add_acpi_external_facing_port`.
BUG=b:259716145
TEST=Build google/rex with this flag and verify it in SSDT at
runtime.
SSDT snippet:
Name (_DSD, Package (0x04) // _DSD: Device-Specific Data
{
ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"),
Package (0x01)
{
Package (0x02)
{
"HotPlugSupportInD3",
One
}
},
ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"),
Package (0x01)
{
Package (0x02)
{
"ExternalFacingPort",
One
}
}
})
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I65100283ed9b65037c9890f28ecab41fcfa25d83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69970
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The message only makes sense if ACPI PM base address is
allowed to be dynamic. If requested, it can be logged
in common code.
Change-Id: Iad7a60098c0391cc23384035af49e373dad90233
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Later soc/intel/common/smbus addresses TCO2_STS as a separate
16-bit register, while baytrail and braswell assumes 32-bit
wide TCO1_STS to extend as TCO2_STS.
In src/soc/intel/denverton_ns:
#define TCO2_STS_SECOND_TO 0x02
In soc/intel/baytrail,braswell:
#define SECOND_TO_STS (1 << 17)
Elsewehere
#define SECOND_TO_STS (1 << 1)
It's expected that we remove the first (1 << 17) case and only
access TCO2_STS as a separate 16-bit register. For now, use
unique names to avoid confusion.
Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Tree is inconsistent with the use of TCO register space offsets and
related preprocessor defines. The legacy space was offset from ACPI
PM base by 0x60, but this changed with later platforms. The convenient
way is to define the TCO registers relative to its base address and
subtract 0x60 here, but this change cannot be easily done tree-wide or
in one go.
For the transient period, apply TCO_SPACE_NOT_YET_SPLIT flag until
all platforms use a clean style of tco_{read,write} accessor functions
instead of {read,write}_pmbase16(), or worse, inw/outl().
Change-Id: I16213cdb13f98fccb261004b31e81a9a44cb6e3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I4db09632a41d28b0c8e211e6232db4e6d85bdf5f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70051
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=none
TEST=Build and boot to google/rex.
Excerpt from google/rex coreboot log:
[DEBUG] ME: FPFs Committed : NO
[DEBUG] ME: Manufacturing Vars Locked : NO
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Iec07c1f951fbbf51541917c8b99d19f2f12980b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69739
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This patch creates a helper function `heci_finalize()` to keep HECI
related operations separated for easy guarding again FSP config.
Currently, `heci_set_to_d0i3()` function is getting called twice.
BUG=b:260041679
TEST=Able to build google/rex with this patch and observe coreboot log
modification as below:
Without this patch:
[DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms
[WARN ] HECI: CSE device 16.1 is disabled
[WARN ] HECI: CSE device 16.2 is disabled
[WARN ] HECI: CSE device 16.3 is disabled
[WARN ] HECI: CSE device 16.4 is disabled
[WARN ] HECI: CSE device 16.5 is disabled
[DEBUG] Finalizing chipset.
[DEBUG] apm_control: Finalizing SMM.
[DEBUG] APMC done.
[WARN ] HECI: CSE device 16.1 is disabled
[WARN ] HECI: CSE device 16.2 is disabled
[WARN ] HECI: CSE device 16.3 is disabled
[WARN ] HECI: CSE device 16.4 is disabled
[WARN ] HECI: CSE device 16.5 is disabled
[DEBUG] BS: BS_PAYLOAD_BOOT entry times (exec / console): 29 / 78 ms
With this patch:
[DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms
[WARN ] HECI: CSE device 16.1 is disabled
[WARN ] HECI: CSE device 16.2 is disabled
[WARN ] HECI: CSE device 16.3 is disabled
[WARN ] HECI: CSE device 16.4 is disabled
[WARN ] HECI: CSE device 16.5 is disabled
[DEBUG] Finalizing chipset.
[DEBUG] apm_control: Finalizing SMM.
[DEBUG] APMC done.
[DEBUG] BS: BS_PAYLOAD_BOOT entry times (exec / console): 28 / 52 ms
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7021a1d4c73d3fdfddfd6e809ebc1eeb1fa6d75e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
|
|
This patch drops the local implementation
`log_me_ro_write_protection_info` and adopts the API from IA common
code (cse_lite.c).
BUG=none
TEST=Able to compile the cse_lite.c file for google/kano without
any error.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I087ffb8ac94f14a6bd7f2bf6bb907c4047dc9899
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69969
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch creates an API for CSE-Lite specific SKU to retrieve the
Write Protect (WP) information (`cse_log_ro_write_protection_info`)
like WP range and limit, if the region is write-protected or not etc.
BUG=none
TEST=Able to compile the cse_lite.c file for google/kano without
any error.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8f4b7880534ded5401b6f8d601ded88019c636c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69968
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
These boards do no fill MADT with useful information.
Change-Id: Ie61e4e4b03c9b7fcd70aba7a2bd71eadd6f4dab1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69777
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
The cpu cluster is always present and it's the proper device to contain
the settings that need to be applied to all cpus. This makes it possible
to remove the fake lapic from devicetrees.
Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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