| Age | Commit message (Collapse) | Author |
|---|
|
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I85fc5dabf10c6df7f11fd1defe8a39afc9f95325
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72797
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This moves the definition for POST_BOOTBLOCK_CAR from the intel-specific
postcodes into the common postcode list, and uses it for the
cache-as-RAM init as needed.
Because POST_BOOTBLOCK_CAR was set to 0x20 in some spots and 0x21 in
most of the others, the values were consolidated into 0x21. This will
change the value on some platforms.
Any conflicts should get sorted out later in the conversion process.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8527334e679a23006b77a5645f919aea76dd4926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
Found-by: linter
Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This simplifies the code flow of the cpu init. APL can do CPU init after
calling FSP-S, while GLK needs to do that before. This is now reflected
directly in the cpu ops rather than using
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT as a proxy.
Change-Id: I7fd1db72ca98f0a1b8fd03a979308a7c701a8a54
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This patch requests FSP to enable the MRC fast boot feature along
with FSP v2473.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If4a621e55c853505f7a702181ae5a70dc56d5b5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72745
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
No bootstate hook is called on exit of BS_OS_RESUME or BS_PAYLOAD_BOOT.
Change-Id: I2b5b834d0663616a9523fd119f007e3bac8e7bf2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
|
|
This patch moves ME host firmware status register structures to ME
header file. It also marks unused structure fields to reserved.
The idea here is to decouple ME specification defined structures from
the source file `.c` and keep those into header files so that in future
those spec defined header can move into common code.
The current and future SoC platform will be able to select the correct
ME spec header based on the applicable config. It might be also
beneficial if two different SoC platforms would like to use the same
ME specification and not necessarily share the same SoC directory.
BUG=b:260309647
Test=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ib96fcb86fd2c3fe16f23c8f038f4930a832a5b01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
This commit provides a dev tree setting for partners to enable/disable
TccoldHandshake for the sighting in doc:723158
BUG=b:221461379
BRANCH=firmware-brya-14505.B
TEST=compile ok and FSP UPD is config properly
Change-Id: Ica13b98204acebef7f0b9a4411b4ac19f53cad6e
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68635
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Some reserved address range listed in Alder Lake Platform Firmware
Architecture Specification document 626540 section 6.4 ADL - System
Memory Map such as North TraceHub ranges were missing. Details about
North TraceHub (aka. Intel TraceHub) can be found in Intel Trace
Hub (Intel TH) Developer's Manual document 671536.
BUG=b:264648959
TEST=Compilation successful
Change-Id: I14803a7297c8c5edefe564d92bfe7314f6769942
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
This patch adds the {MCH:a706, TDP:28W} missing 28W configuration.
BUG=b:267666609
BRANCH=firmware-brya-14505.B
TEST=Power Limit are properly set on skolas 28W
Change-Id: Ice35d622eeec5799c53de086430d00dc8789097e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
If we show the user early signs of life during CSE FW sync or MRC
(re)training, log these to the eventLog (ELOG_TYPE_FW_EARLY_SOL).
These can be used to ensure persistence across global reset (e.g. after
CSE sync) so that they can be later retrieved in order to build things
such as test automation ensuring that we went through the SOL
path/display initialized.
BUG=b:264648959
TEST=event shows in eventlog after CSE sync and/or MRC
Change-Id: I8181370633a1ecff77b051d3110f593c3eb484a2
Signed-off-by: Tarun Tuli <taruntuli@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71295
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Intel SPR-SP (Sapphire Rapids Scalable Processor) was product launched
on Jan. 10, 2023.
Change-Id: I14cf115b02d8edff9b48e744b798a3b1ba18b8bf
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
|
This patch enables S0i2.2 by letting 1.5V Phy supply to control the
externa FET.
BUG=b:256805904
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8771c11ce3b305343c7e96510e1375538d5e7f04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72709
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
|
This patch moves ME host firmware status register structures to ME
header file. It also marks unused structure fields to reserved.
The idea here is to decouple ME specification defined structures from
the source file `.c` and keep those into header files so that in future
those spec defined header can move into common code.
The current and future SoC platform will be able to select the correct
ME spec header based on the applicable config. It might be also
beneficial if two different SoC platforms would like to use the same
ME specification and not necessarily share the same SoC directory.
BUG=b:260309647
Test=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I58faed286718f5eab714cd39001177e50feb4f8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This patch moves ME host firmware status register structures to ME
header file. It also marks unused structure fields to reserved.
The idea here is to decouple ME specification defined structures from
the source file `.c` and keep those into header files so that in future
those spec defined header can move into common code.
The current and future SoC platform will be able to select the correct
ME spec header based on the applicable config. It might be also
beneficial if two different SoC platforms would like to use the same
ME specification and not necessarily share the same SoC directory.
BUG=b:260309647
Test=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ic42c67163fe42392952499293e91e35537cb9147
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This patch moves ME host firmware status register structures to ME
header file. It also marks unused structure fields to reserved.
The idea here is to decouple ME specification defined structures from
the source file `.c` and keep those into header files so that in future
those spec defined header can move into common code.
The current and future SoC platform will be able to select the correct
ME spec header based on the applicable config. It might be also
beneficial if two different SoC platforms would like to use the same
ME specification and not necessarily share the same SoC directory.
BUG=b:260309647
Test=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I34d3c4a60653fe0c1766cd50c96b8d3fe63637d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
The D-state list lists the devices with the corresponding
D-state that the devices should be in, in order to enter LPM.
DPTF is not mentioned in Intel's document 595644 as one of
the devices.
This CL removes it to avoid a potential error seen in ADL
devices as mentioned in commit 3fd5b0c4cdeb ("soc/intel/adl:
remove DPTF from D-states list used to enter LPM")
TEST=Built and tested on Rex, saw SSDT generated properly.
BUG=b:231582182
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I9192ed9a7fb59ebba14f6d5082b400534b16ca72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72603
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>.
Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch moves ME host firmware status register structures to ME
header file. It also marks unused structure fields to reserved.
The idea here is to decouple ME specification defined structures from
the source file `.c` and keep those into header files so that in future
those spec defined header can move into common code.
The current and future SoC platform will be able to select the correct
ME spec header based on the applicable config. It might be also
beneficial if two different SoC platforms would like to use the same
ME specification and not necessarily share the same SoC directory.
BUG=b:260309647
Test=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I7dfd331e70f6d03c88248ca5147dbe6785a8e69d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
It turns out that the [0xfa000000-0xfaffffff] range conflicts with
some North TraceHub address space ranges ([0xfad00000-0xfadfffff] and
[0xfacfc000-0xfacfffff]).
Experiments have established that this conflicting range results in an
unpected PIPE A underrun issue reported by i915 and some visible
flickers on the display during boot.
The [0xf0000000-0xffffffff] range is a crowded memory space with
resources statically assigned to some devices but also some ranges
used at various point in the boot flow by the FSP.
To not run into any other potential conflicts, we want to pick a
unused memory space. But at this early stage of the boot, we do not
have full knowledge of what memory space is going to be used by the
FSP. As a result, we decided to pick the [0xaf000000-0xafffffff] range
as:
1. It does not conflicting with any coreboot memory space usage
2. It is the address the FSP uses by default for GFX MMIO BAR0 and as
such should not conflict with any FSP memory space usage.
BUG=b:264648959
BRANCH=firmware-brya-14505.B
TEST=No flickers observed on boot
Change-Id: I6a00350ff4007bb7692d2ff6598b946cc6123302
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72605
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This fixes a NULL pointer deref introduced by 69cd729 (mb/*: Remove
lapic from devicetree).
Change-Id: I816fddfe3efe3c3aefe1b2ee28426dc1e1f3c962
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72599
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
The LPC BIOS decode lock bit is defined in EBG EDS documentation.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I60df7e6da2b22b8eeb2094aeb5ee9667043bb30b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71954
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Intel SPR-SP (Sapphire Rapids Scalable Processor) chipset
belongs to Xeon-SP family. It was product launched on
Jan. 10, 2023.
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Ifece05e2fbcc454cdee8e849cb4f146c89f54333
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
The PMC registers are quite different between LBG and EBG. Move pmc.h
to lbg directory to differentiate.
Change-Id: I6f14059942210c222631e11cced0b5c05d3c1dc6
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72399
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I43590f0f792fca1c90ee8f8b32e6be47943c59df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72453
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add functions that allow checking and changing PTT state at runtime.
Can be useful for platforms that want to use dTPM instead and have no
means to stitch ME firmware binary with disabled PTT.
The changing function also checks for the current feature states via
HECI to ensure that the feature state will not be changed if not
needed.
TEST=Successfully switch to dTPM on Comet Lake i5-10210U SoC.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I8426c46eada2d503d6ee72324c5d0025da3f2028
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
|
|
The D-state list lists the devices with the corresponding
D-state that the devices should be in, in order to enter LPM
DPTF is not mentioned in Intel's document 595644 as one of
the devices.
This CL removes it to avoid an error seen after it was added
to that table:
"ACPI Error: AE_NOT_FOUND, While resolving a named reference
package element - \_SB_.PCI0.DPTF (20200925/dspkginit-438)"
TEST=Built and tested on anahera and saw the error is gone
BUG=b:231582182
Change-Id: I00eddd7e4cc71a0c25e77ff53025dee5bf942de1
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
This CL adds claimed memory regions that were missing for the
resource allocator. See commit ca741055e6b6 ("soc/intel/adl: Add
missing claimed memory regions") for details.
TEST=Booted rex and saw the previously missing ranges getting added
from AP Log (with this CL):
SA MMIO resource: MCHBAR -> base = 0xfedc0000, size = 0x00020000
SA MMIO resource: DMIBAR -> base = 0xfeda0000, size = 0x00001000
SA MMIO resource: EPBAR -> base = 0xfeda1000, size = 0x00001000
SA MMIO resource: REGBAR -> base = 0xd0000000, size = 0x10000000
SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x00004000
SA MMIO resource: CRAB_ABORT -> base = 0xfeb00000, size = 0x00080000
SA MMIO resource: LT_SECURITY -> base = 0xfed20000, size = 0x00060000
SA MMIO resource: APIC -> base = 0xfec00000, size = 0x00100000
SA MMIO resource: PCH_RESERVED -> base = 0xfd800000, size = 0x01000000
SA MMIO resource: MMCONF -> base = 0xc0000000, size = 0x10000000
SA MMIO resource: DSM -> base = 0x7c000000, size = 0x04000000
SA MMIO resource: TSEG -> base = 0x7b000000, size = 0x00800000
SA MMIO resource: GSM -> base = 0x7b800000, size = 0x00800000
dmesg:
BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] reserved
BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable
BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved
BIOS-e820: [mem 0x0000000000100000-0x00000000759c9fff] usable
BIOS-e820: [mem 0x00000000759ca000-0x000000007fffffff] reserved
BIOS-e820: [mem 0x00000000c0000000-0x00000000e0ffffff] reserved
BIOS-e820: [mem 0x00000000f8000000-0x00000000f9ffffff] reserved
BIOS-e820: [mem 0x00000000fd800000-0x00000000fe7fffff] reserved
BIOS-e820: [mem 0x00000000feb00000-0x00000000feb7ffff] reserved
BIOS-e820: [mem 0x00000000fec00000-0x00000000fecfffff] reserved
BIOS-e820: [mem 0x00000000fed20000-0x00000000fed83fff] reserved
BIOS-e820: [mem 0x00000000feda0000-0x00000000feda1fff] reserved
BIOS-e820: [mem 0x00000000fedc0000-0x00000000feddffff] reserved
BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
BIOS-e820: [mem 0x0000000100000000-0x000000027fffffff] usable
BIOS-e820: [mem 0x000003fff0aa0000-0x000003fff0aa1fff] reserved
Change-Id: I749e7b6e969f8d6314fcd2906acd7de69d4d9f9c
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
The Alder Lake PEIM graphics driver executed as part of the FSP does
not wait for the panel power cycle to complete before it initializes
communication with the display. It can result in AUX channel
communication time out and PEIM graphics driver failing to bring up
graphics.
If we have performed some graphics operation in romstage, it is
possible that a panel power cycle is still in progress. To prevent any
issue with the PEIM graphics driver it is preferable to ensure that
panel power cycle is complete.
This patch replaces commit ba2cef5b5493
("soc/intel/common/block/early_graphics: Introduce a 200 ms delay")
workaround patch.
BUG=b:264526798
BRANCH=firmware-brya-14505.B
TEST=Developer screen is visible in the recovery flow
Change-Id: Iadd6c9552b184f7d6ec8df9d0d392634864ba50b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72419
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
We were using the libgfxinit `Initialize' function with the
`Clean_State' parameter because the more appropriate `Update_Output'
function was not performing all the necessary clean up operations for
the PEIM driver to be successful when libgfxinit was used in romstage.
Thanks to a lot of experiments and some log analysis efforts, we were
able to identify the missing operation and fix the `Update_Output'
function (cf. https://review.coreboot.org/c/libgfxinit/+/72123).
The `initialized' global variable is now unnecessary as we track the
initialization in the Ada code instead.
Since the `Update_Output' function does not return any value, this
patch modifies the `gma_gfxstop' prototype accordingly. This does not
have any impact as the return value was not used anyway.
BUG=b:264526798
BRANCH=firmware-brya-14505.B
TEST=Developer screen is visible
Change-Id: I53d6fadf65dc09bd984de96edb4c1f15b64aeed0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72125
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Getting an error from the Kernel on Rex devices:
> ACPI Error: AE_NOT_FOUND, While resolving a named reference
> package element - \_SB_.PCI0.FSPI (20210730/dspkginit-438)
FSPI is defined in src/soc/intel/meteorlake/chipset.cb:
device pci 1f.5 alias fast_spi on end
This CL adds the corresponding FSPI device to the DSDT to prevent
the error mentioned above.
See commit feed8e4bd9dc ("soc/intel/adl/acpi: add FSPI to DSDT") for
the corresponding ADL CL.
TEST=Built and tested on brya by verifying the error is gone.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id8d2a1b5e074f036345e028b117d420bf36a9042
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This function reads out the current value set to output for a GPIO pin.
Ex: GPP_E0 is set to output
int e0_val;
e0_val = gpio_tx_get(GPP_E0);
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ib02b9ab50d378eb163d91aed1576428b49cec2cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72127
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
|
|
Current size of the cbmem premem buffer (8KB) is sometimes insufficient
to contain the complete debug log causing the cbmem console buffer to
indicate overflow.
This patch increases the premem cbmem buffer size to 16KB so that
the complete debug log can be stored in it.
TEST=Make sure that logs from all the boot stages can be seen using
'cbmem -c'.
Change-Id: I60c68322c52191eabf7e06b4be06e66f90ff8751
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71290
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently ASPM cannot be disabled by individual mainboards, if the
soc Kconfig includes SOC_INTEL_COMMON_PCH_CLIENT. Other options like
PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE are already configurable by
individual mainboards if needed. This change makes PCIEXP_ASPM one of
these configurable options.
Test: build prodrive/atlas and see that build/config.h lists the
option CONFIG_PCIEXP_ASPM as disabled.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ic9c049f1d225bc21d8da5bd208651ad847ae0c6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72117
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Currently most of the FSP debug messages (when enabled) are truncated due to insufficient size of cbmem buffer.
Increase premem cbmem console size to 0x16000 bytes and cbmem buffer size to 0x100000 bytes so that cbmem buffer can contain most of the debug logs when FSP debug messages are enabled.
TEST=Verify output of 'cbmem -c' when FSP debug messages are enabled but MRC debug message.
Change-Id: I0273fb14916f213b686270a9dec4c1b47612af4d
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71289
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Current size of the cbmem buffer (128KB) is insufficient to contain the
complete debug log causing the cbmem console buffer to wrap.
This patch increases cbmem buffer size to 256KB so that the complete
debug log can be stored in it.
TEST=Make sure that logs from all the boot stages can be seen using
'cbmem -c'.
Change-Id: I2099386dd87a010c3a5937bd896620270f587b1c
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71288
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Intel SPR-SP (Sapphire Rapids Scalable Processor) was product launched
on Jan. 10, 2023. The chipset includes Emmitsburg PCH.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I05ed8f753bf63b6cb3035e973eb6a7974edfd673
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
|
This patch implements a new API to make the UFS controller function
disabled. Additionally, perform a warm reset post disabling the UFS
controller to let PMC know about the state of the UFS controller
and disable the MPHY clock.
BUG=b:264838335
TEST=Able to build and boot Google/Marasov successfully.
From the AP log, I am able to confirm that UFS is function disabled
using PSF.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I940a634f70f8c97ef1234866d4c5a1ff224c6e24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
This patch makes it easy for OEMs to keep a unified AP firmware image
to boot different SKUs with UFS and non-UFS as boot media.
With a unified image while booting on non-UFS SKU is exhibiting S0ix
failure due to UFS remain enabled in the strap although FSP-S is
making the UFS controller function disabled.
The potential root cause of this behaviour is although the UFS
controller is function disabled but MPHY clock is still in active
state.
A possible solution to this problem is to issue a warm reboot (if
boot path is S5->S0 or G3->S0) after disabling the UFS and let PMC
read the function disable state of the UFS for disabling the MPHY
clock.
Mainboard users with such board design where OEM would like to use
an unified AP firmware to support both UFS and non-UFS sku booting
might need to choose this config to allow disabling UFS while booting
on the non-UFS SKU.
Note: selection of this config would introduce an additional warm
reset in cold-reset scenarios due to function disabling of the UFS
controller.
BUG=b:264838335
TEST=Able to build and boot Google/Marasov successfully.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0a811d8f4aad41dab6f8988329eaa1d590a4637a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
This patch calls into `pmc_clear_pmcon_pwr_failure_sts()` to clear
GEN_PMCON_x register status bits after determining the
`prev_sleep_state`.
Having those bits being set across reboot might be misleading.
For example: although the last boot was not due to power failure but
the power failure bit still remains the same (unless cleared).
Note: clearing `GBL_RST_STS` bit earlier than FSP-M/MRC having an
adverse effect on the PMC sleep type register which results in
calculating wrong `prev_sleep_state` post a global reset, hence,
just clearing the power failure status bits rather than clearing
the complete PMC PMCON_A register.
BUG=b:265939425
TEST=Able to clear the GEN_PMCON_A register power failure bits aka
BIT16 and BIT14 on google/marasov platform over next boot to avoid
having its persistent effect.
Without this patch:
pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
...
GEN_PMCON: d0215238 00002200
With this patch:
pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
...
GEN_PMCON: d1001038 00002200
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4f5dfe0251aeb85b667fbfc44fbf17b025aec090
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
|
This patch converts below chip configs from camel case to snake
case to match with the other chip configs belongs to the chip
structure.
- SaGv
- RMT
Additionally, updated the `sagv` help text and operation as
applicable based on the FSPMUPD.h file (belongs to the vendorcode).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I62e521cf3f46e888e2c995d83ac7dc666de1af82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
|
This patch implements an API named `pmc_clear_pmcon_pwr_failure_sts()`
to clear power failure status bits of PMC General PM Configuration A/B
based on the underlying SoC.
Based on the available PMC register definitions between Sky Lake till
latest Meteor Lake platform, the SoC platform that selects
SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION config has power failure bits
mapped into the MMIO mapped GEN_PMCON_A register where else for the
other SoCs, those power failure bits are belongs to the PCI config
space mapped GEN_PMCON_B register.
BUG=b:265939425
TEST=Able to build the google/marasov.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icbbe47ccfd489edf9c38f52bdf7cf2de7aa9eedf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72053
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
|
Some boards may want to perform a specific operation before the CSE FW
update final operation begins. For instance, on Brya this new callback
can be used to inform the end-user that an update is in progress.
BUG=b:264648959
BRANCH=firmware-brya-14505.B
TEST=Compilation success
Change-Id: Ia4d32a71f3ae61d2e24197fee6b458512f7778a9
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72097
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
If a CSE update is going to happen and early graphics is supported by
the mainboard, an on-screen text message is displayed to inform the
end user.
CSE update can take a while and an impatient end user facing a black
screen for a while may reset the device unnecessarily.
BUG=b:264648959
BRANCH=firmware-brya-14505.B
TEST=On screen text message during CSE update observed on skolas
Change-Id: I28c4fef9345d577be287b76a2a767b5c852ec742
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72098
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This reverts commit 80b1fa33.
Reason for revert:
"Error: CONFIG() used on unknown value (ENABLE_FSP_ERROR_INFO) at src/soc/intel/xeon_sp/romstage.c:20"
Change-Id: I843322fc9d7ebbc30e9209ae933313f2668bfa40
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Provide D-states to enter LPM (S0ix) for MTL
Values were copied over from corresponding ADL file (as MTL data
sheet is not yet available).
TEST=Built and tested on Rex by verifying SSDT contents
Change-Id: If367511a29726669fe25ad2124e2f9b877a31ee8
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
|
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes
alphabetic ordering of included headers.
BUG=b:261778357
TEST=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I3138edd8125601b6c9dff5f9252a4bba8385146d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
For SPR-SP FSP MRC cache, NO_FSP_TEMP_RAM_EXIT should not
be selected.
Change-Id: I63101f286809d6cebb9a7d74443446cb3fe650c4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71928
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
|
After calling FSP MemoryInit API, if there is an error, some FSPs
(such as SPR-SP FSP) is capable of generating FSP_ERROR_INFO_HOB.
Check existence of such a HOB and handle it accordingly.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I612393ffac90815606f3f2544bc1518f6912e605
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71952
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
|
DEFAULT_SOFTWARE_CONNECTION_MANAGER
Needs to be selected for ChromeOS mainboards even for non-ChromeOS
builds, else Thunderbolt/USB4 doesn't work under Windows (and likely
Linux as well).
TEST=build/boot Windows on drobit/banshee, verify TB functional
Change-Id: Iee3f99840f0c6cc384d9fdef6dff55bcbfc0380f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72140
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Possible Buffer Overflow - Array Index Out of Bounds. Array
regions size is 256 but 'i' iterates from 0 to 256.
Found-by: Klockwork
BUG=None
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Iee45a5821b9dd3f9e6f9816599beebf34555426d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72049
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch adds new macros (i.e. SUS Power Failure and Power Failure)
from the APL EDS vol 1 (doc 569262) to be able to implement common
code API to clear the power failure status bits.
Note: as per the EDS those newly added power management failure bits
are RO and shouldn't change any functionality of the existing APL SoC
code. The reason behind adding those macro definitions is to fix the
compilation issue due to code change targeted for the Intel SKL and
Xeon-SP.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0bbf11ada2b2f8735173be69ad157b8055021126
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72130
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch adds new macros (i.e. SUS Power Failure and Power Failure)
from the DNV EDS vol (doc 558579) to be able to implement common
code API to clear the power failure status bits.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6ed962eae79154a8faea382dbe8367133cb05eda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
This patch fixes the alignment of the PMC macros defined in the
pm.h file.
Change-Id: Ib5ff87e2f6524ca1be69027080149a3fbe2df7d9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72158
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch fixes the alignment of the PMC macros defined in the
pm.h file.
Change-Id: I9a55e1b099a53180e40eedcc52120d65558e7f8b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72157
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch fixes the alignment of the PMC macros defined in the
pm.h file.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia8d35a5d104658b7900fde7f7b8c6f88530a614e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72129
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: If44a07503470f57037b59d03eea830703a3c604a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72100
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I8432d799c9bf23058b7b903bb07f6c2b4308eeba
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72103
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Id2b408e24f74367777b1b949623d6692f2f19e6d
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72076
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
|
|
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to
control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.
This new option is hooked with `SkipMbpHob` UPD and is always
disabled for ChromeOS platforms.
This made skip_mbp_hob SOC chip config variable redundant
which is also removed as part of this change.
BUG=none
TEST=Build and boot to Google/Rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Iaba1ea29a92a63d2b287e1ccdea1a81ec07b9971
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Currently most of the FSP debug messages (when enabled) are truncated
due to insufficient size of cbmem buffer.
Increase premem cbmem console size to 0x16000 bytes and cbmem buffer
size to 0x100000 bytes so that cbmem buffer can contain most of the
debug logs when FSP debug messages are enabled.
BUG=b:265683565
TEST=Verify output of 'cbmem -c' when FSP debug messages are enabled
but MRC debug message.
Note: Still 350/2200 lines of premem messages are missing.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I120423e1dd2bc468cf9cec6da1246ac3c0a155e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72048
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Current size of the cbmem buffer (128KB) is insufficient to contain the
complete debug logs which is more than 166KB hence, cbmem console buffer has wound off to contain the maximum possible debug messages within the allocated buffer as results, we are seeing truncated debug message while looking into the cbmem console.
This patch increases cbmem buffer size to 256KB so that the complete
debug log can be stored in it.
BUG=b:265683565
TEST=Make sure that logs from all the boot stages can be seen using
'cbmem -c'.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ibeabb61d60491b831252b7161c9d3181fbe09e73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72047
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Intel Ice Lake is unmaintained and the only user of this platform ever
was the Intel CRB (Customer Reference Board). As it looks like, it was
never ready for production as only engineering sample CPUIDs are
supported.
As announced in the 4.19 release notes, remove support for Intel
Icelake code and move any maintenance on the 4.19 branch.
This affects the following components and their related code:
* Intel Ice Lake SoC
* Intel Ice Lake CRB mainboard
* Documentation
Change-Id: Ia796d4dc217bbcc3bbd9522809ccff5a46938094
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72008
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add a INFO print indicating that we did infact attempt to display the
MRC training message to the user.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Print seen in cbmem -c
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I1a20fb221aa2fa0eeaf9b7f8cf3d8a8ab0b91133
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
|
|
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).
As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.
Without this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 5
With this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib43d3402f94f47dc576fb99a6b2a7acf6f0af220
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71982
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).
As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.
TEST=Able to build and boot google/dragonegg.
Without this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 5
With this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0e5a6e54abc7c03a2fbffa308db20c392e2a600b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71983
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).
As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.
TEST=Able to build and boot google/dedede.
Without this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 5
With this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id2c1f24a8fa54eea512b5bd3dd91423f9892687d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71984
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).
As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.
TEST=Able to build and boot google/volteer.
Without this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 5
With this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0e48b110826f16d13d18c138fce03a56c85b9d1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71985
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).
As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.
TEST=Able to build and boot google/taeko.
Without this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 5
With this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I52f9c261f4eea34e6d2300c8de97ee018d886189
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71987
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).
As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.
TEST=Able to build and boot google/rex.
Without this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 5
With this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Idc40045445cccc5b34fb49901d9ef548f2f0560b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71986
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The patch fixes indication of incorrect `prev_sleep_state` on the next
boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power
failure. As a result, every early warm/global reset is considered
as power failure after looking into the PMC MMIO CON-A register
alone (as ignoring the ACPI PM_CTRL.WAK_STS bit).
As per the code comment this code logic is expected to check the power
failure reason if PCH doesn't set the WAK_STS while waking from G3
state.
TEST=Able to build and boot google/hatch.
Without this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit
is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 5
With this patch:
Observation: Resuming after a warm reset is considered as
`prev_sleep_state 0`. It matches with the SLP_TYP is zero and
WAK_STS bit is set.
pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000
GEN_PMCON: d1215238 00002200
....
prev_sleep_state 0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I05a2fab75c3d931651885db0003ab8c5748a1568
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71934
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h.
BUG=b:261778357
TEST=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I73bac9560d0ff315d6fe6f4efc3ee9011f77c660
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72036
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h.
BUG=b:261778357
TEST=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Iccf37a340880e4b5a18f51c3add9a15a74e1d7b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72030
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes
alphabetic ordering of included headers.
BUG=b:261778357
TEST=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I55fa5941a9255f60c2aa23b90d16cf342d6f458f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72032
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes
alphabetic ordering of included headers.
BUG=b:261778357
TEST=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: If069e66f2762eb373d35d635c09226ac5be99c7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72039
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes
alphabetic ordering of included headers.
BUG=b:261778357
TEST=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I02fe236506abbc0d97982747cfcf3c0e9ef4897a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72040
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes
alphabetic ordering of included headers.
BUG=b:261778357
TEST=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I8135dc918cb04c854dc003966b7657806a42bad9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72042
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes
alphabetic ordering of included headers.
BUG=b:261778357
TEST=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I12497d46e58aae41ec8dcb5d567267579dc12fc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72041
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes
with the common gpio.h which includes soc/gpio.h which includes
intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes
alphabetic ordering of included headers.
BUG=b:261778357
TEST=Able to build and boot.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I349a2b24ecdee347548b5c7b292c5075e6150a19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72033
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch refactors the mainboard_romstage_entry() function to avoid
redundant chipset programming caused by global reset due to CSE FW
sync operation. Hence, keeping only the minimal and mandatory
operations required to perform CSE FW sync successfully.
This would help to optimize the boot flow by removing redundant
programming like SA, SMBUS twice in every CSE FW update path.
TEST=Able to build and boot Google/Rex successfully.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1a13fac1e99341991d8dd818d4ab8a20d209a94c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71933
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch refactors the mainboard_romstage_entry() function to avoid
redundant chipset programming caused by global reset due to CSE FW
sync operation. Hence, keeping only the minimal and mandatory
operations required to perform CSE FW sync successfully.
This would help to optimize the boot flow by removing redundant
programming like SA, SMBUS twice in every CSE FW update path.
TEST=Able to build and boot Google/Marasov successfully.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iba9767ef51d7fc7ecf9de14454105865433ba041
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71932
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix
cbmem buffer overflow issue.
BUG=b:261800015
Test=Boot MTL simics and check cbmem -c | grep 'CBFS: Found'
lists all stages.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6a49f88aff07841d105cd3916086aa9e496654c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71921
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Now that multiple platforms are trying to initialize eMMC in coreboot
instead of depthcharge, lets move common functionality into commonlib
instead of copying the same functionality between multiple platforms.
Note for consistency, changed name of set_early_mmc_wake_status() to
mmc_set_early_wake_status(). Also adding an mmc_send_cmd1() function
for retrieving the Operating Conditions Register (OCR) contents.
BUG=b:218406702
BRANCH=None
TEST=emerge-herobrine coreboot chromeos-bootimage
flash onto villager device and make sure still boots ChromeOS
Change-Id: Id00535b05bbd379081712601ef10e762c1831747
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Found using -Woverride-init command option.
Change-Id: I9f0755de9fae678fc5d78a709453fd1098d70e50
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I3256c3c6a4ea331efae00d78192355a1fd78d6d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
|
MSR_PPIN_CTL may need to be read more than once, so lock PPIN CTL
MSR at a late BS_PAYLOAD_LOAD boot state.
This MSR is in platform scope and must only be locked once on each
socket. Add a spinlock to do so.
Tested=On OCP Craterlake single socket, rdmsr -a 0x04e shows 1.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I8deb086339267cf36e41e16f189e1378f20b82f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
|
|
The patch uses 'enum cb_error' values as return values for below
functions:
1. cse_get_rw_rdev()
2. cse_erase_rw_region()
3. cse_write_rw_region()
4. cse_locate_area_as_rdev_rw()
5. cse_get_target_rdev()
6. cse_copy_rw
TEST=Build, boot and perform CSE downgrade test on the Gimble board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I9c664430a5015d37b9c329f85886f8622deaa497
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
The patch uses cb_err enum values as return values for function
cse_get_boot_performance_data() instead of true/false.
TEST=Build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I0153d5496c96fb0c2a576eef1fe2fa7fa0db8415
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
The patch uses cb_err enum values as return values for below functions:
1. cse_hmrfpo_enable()
2. cse_boot_to_ro()
3. cse_prep_for_rw_update()
4. cse_sub_part_get_target_rdev()
5. cse_get_sub_part_fw_version()
6. cse_prep_for_component_update()
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I1bdb7d6b2051a69f1021673d464bfad63dd39431
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
|
|
Use 'enum cb_err' values for below cse lite functions instead of true or
false.
Functions whose return values updated in this patch:
1. cse_set_next_boot_partition()
2. cse_data_clear_request()
3. cse_set_and_boot_from_next_bp()
4. cse_boot_to_rw()
5. cse_fix_data_failure_err()
TEST= Do boot test on Gimble.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I7fec530aeb617bab87304aae85ed248e51a6966b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
The patch uses 'enum cb_err' values as return values for
cse_get_bp_info() function.
TEST=Build the code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I900e40b699de344f497e61d974bca3fee7f6ecbf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
The patch updates return type for below functions as they uses
'enum csme_failure_reason' type return values.
1. cse_sub_part_trigger_update()
2. handle_cse_sub_part_fw_update_rv()
3. cse_sub_part_fw_update()
TEST=Build coreboot code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I43bc2d518a275894860e4d3c930c3c4d9685fb3a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71792
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Fix:
cc1: error: 3rdparty/blobs/mainboard/asrock/h110m: No such file or directory [-Werror=missing-include-dirs]
cc1: error: 3rdparty/blobs/mainboard/acer/aspire_vn7_572g: No such file or directory [-Werror=missing-include-dirs]
...
Change-Id: Icc43e40514a12944fa180197ffe3230ff9800de9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Found using 'Wmissing-include-dirs' command option.
Change-Id: I420b60341dfd0119b14e8492722af62e49fceff8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
Change-Id: Iba5b39c6189d3224ba209c7985153701fe8896fb
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
It has been reported that the PEIM graphics driver may temporarily
fail communication with the display if the time between libgfxinit
turning off the displays and the PEIM driver initialization is too
short. 200 ms has been identified as a safe delay.
This is a temporary workaround and an investigation is in progress to
come up with a better and long term solution.
BUG=b:264526798
BRANCH=firmware-brya-14505.B
TEST=Developer screen is systematically seen
Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de1
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71656
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
If memory training is going to happen and early graphics is supported
by the mainboard, an on-screen text message is displayed to inform the
end user.
Memory training can take a while and an impatient end user facing a
black screen for a while may reset the device unnecessarily.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=On screen text message during MRC training observed on skolas
Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70300
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Verify that VGA text mode is functional in romstage
Change-Id: I727b28bbe180edc2574e09bf03f1534d6282bdb2
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70303
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch introduces an early graphics driver which can be used in
romstage in cache-as-ram mode. The implementation relies on
`libgfxinit' and provide VGA text mode support.
SoCs wanting to take advantage of this driver must implement the
`early_graphics_soc_panel_init' function to set the panel power
sequence timing parameters.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Graphics bring up observed on skolas with extra patches
Change-Id: Ie4ad1215e5fadd0adc1271b6bd6ddb0ea258cb5b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70299
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
