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2018-10-12drivers/intel/fsp2_0: Hook up IntelFSP repoPatrick Georgi
With https://github.com/IntelFsp/FSP/pull/4 merged, this allows using Intel's FSP repo (that we mirror) to build a complete BIOS ifd region with a simple coreboot build, automatically drawing in headers and binaries. This commit covers Apollolake, Coffeelake, Skylake, and Kabylake. Skylake is using Kabylake's FSP since its own is FSP 1.1 and Kabylake's also supports Skylake. Another candidate (given 3rdparty/fsp's content) is Denverton NS, but it requires changes to coreboot's FSP bindings to become compatible. Cannonlake, Whiskeylake require an FSP release. Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28593 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-11src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-11src: Replace MSR addresses with macrosElyes HAOUAS
Change-Id: I849dd406f5ccc733d4957eaf1c774745782f531a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-10-11selfboot: remove bounce buffersRonald G. Minnich
Bounce buffers used to be used in those cases where the payload might overlap coreboot. Bounce buffers are a problem for rampayloads as they need malloc. They are also an artifact of our x86 past before we had relocatable ramstage; only x86, out of the 5 architectures we support, needs them; currently they only seem to matter on the following chipsets: src/northbridge/amd/amdfam10/Kconfig src/northbridge/amd/lx/Kconfig src/northbridge/via/vx900/Kconfig src/soc/intel/fsp_baytrail/Kconfig src/soc/intel/fsp_broadwell_de/Kconfig The first three are obsolete or at least could be changed to avoid the need to have bounce buffers. The last two should change to no longer need them. In any event they can be fixed or pegged to a release which supports them. For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the value needed in 1999 for the 32-bit Linux kernel, the original ramstage) to 0xe00000 (14 Mib) which will put the non-relocatable x86 ramstage out of the way of any reasonable payload until we can get rid of it for good. 14 MiB was chosen after some discussion, but it does fit well: o Fits in the 16 MiB cacheable range coreboot sets up by default o Most small payloads are well under 14 MiB (even kernels!) o Most large payloads get loaded at 16 MiB (especially kernels!) With this change in place coreboot correctly still loads a bzImage payload. Werner reports that the 0xe00000 setting works on his broadwell systems. Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/28647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-11soc/intel/common/block/gpio: check for NULL using if statementBora Guvendik
Remove assert() and instead use if statement to check if comm->groups is NULL. Found-by: klockwork BUG=None TEST=Boot to OS Change-Id: I85a6bc700b52d04c61ca8f2baac62000f40cf2cb Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/28940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-10soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabledFurquan Shaikh
This change sets PCIEXPWAK_DIS in PM1_EN register if WAKE# pin is not enabled on the platform. This is required to prevent unnecessary wakes if the WAKE# pin remains not connected on the platform. Function to set PCIEXPWAK_DIS gets called in normal boot path (BS_PAYLOAD_LOAD) as well as S3 resume path (BS_OS_RESUME). BUG=b:117284700 TEST=Verified that no spurious wakes are observed on nocturne. Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-10-09soc/intel/cannonlake: Add PCIE ASL entrySubrata Banik
This patch creates _PRT entires for each PCIE root port devices. TEST=Able to see PCIE wake device in cat /proc/acpi/wake list Change-Id: I183c89c92139e15e0bfc39620710dbdc6597b351 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devicesSubrata Banik
This patch provides option for PCI IRQ mapping in both PIC and APIC mode. TEST=Build and Boot on CNL RVP. Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/common/acpi: Fix ACPI Namespace lookup failure, AE_ALREADY_EXISTS ↵Subrata Banik
issue This patch fixes below ACPI compilation issue: Found 1 external control methods, reparsing with new information Pass 1 parse of [DSDT] ACPI Error: [EPCS] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660) ACPI Error: [EMNA] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660) ACPI Error: [ELNG] Namespace lookup failure, AE_ALREADY_EXISTS (20160318/dsfield-660) Pass 2 parse of [DSDT] ACPI Warning: NsLookup: Type mismatch on EPCS (Integer), searching for (RegionField) (20160318/nsaccess-664) ACPI Warning: NsLookup: Type mismatch on EMNA (Integer), searching for (RegionField) (20160318/nsaccess-664) ACPI Warning: NsLookup: Type mismatch on ELNG (Integer), searching for (RegionField) (20160318/nsaccess-664) Parsing Deferred Opcodes (Methods/Buffers/Packages/Regions) TEST=Able to build sgx.asl without any ASL error. Change-Id: If4e7d4c66b6aab6c081fa272d8c2c9a1f0651ef7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/common/block/pcr: Add NULL pointer check in pcr_execute_sideband_msg()Subrata Banik
This patch to fix KW issue due to msg, data and response pointers NULL check fail. Change-Id: I39324514079f240ba1683a04e579de85485299bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/cannonlake: Disable Legacy PME for Root portsSubrata Banik
Legacy PME are enabled by default in FSP-S UPD. This policy sets PME Interrupt Enable (PIE) bit of RCTL register to trigger interrupt generation when RSTS.PS state has changed (either due to 0->1 transition or due to this bit being set with RSTS.PS already set). Due to this interrupt generation, system wakes from sleep immediately it enters. This patch overrides root port legacy pme upd policy from coreboot to ensure no false SCI is triggerd when system is in S3/S0ix state. BUG=b:113083354 BRANCH=none TEST=Able to make S3 resume using wake on wifi connect/disconnect usecase without any failure. Change-Id: I779fac711eeeed65ea379fad1cc400052d8a00eb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registersSubrata Banik
This patch save and restore ITSS IPCx register before and after FSP-S call. Change-Id: Iea9356b4404d2fa49ea62ef7bc2c72f125054ff3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-09soc/intel/skylake: Ensure FSP don't override ITSS IPCx registersSubrata Banik
This patch save and restore ITSS IPCx register before and after FSP-S call. Change-Id: Ib731f27826d604c305dc52a8488fd6240b01148a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-09soc/intel/common/pch: Select Kconfig for ITSS polarity configurationSubrata Banik
This patch selects Kconfig for Intel Core Platform in order to ensure proper ITSS IPCx programming. Change-Id: I81e75e17ceb23c364b78300c3950144be1580700 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08soc/intel/skylake: Fix ‘dev’ pointer NULL before being dereferencedSubrata Banik
This patch fixes KW issue due to pointer being NULL and will be dereferenced Change-Id: Iedb59daf5f448e31c0097873a086e4d08cd4a979 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28948 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08smmstore: Add a key/val store facility in flash, mediated through SMMPatrick Georgi
It exposes an interface that is as generic as possible, so payloads and/or kernels can use it for their data. Change-Id: I9553922f9dfa60b9d4b3576973ad4b84d3fe2fb5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/25182 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08src: Use tabs for indentationElyes HAOUAS
Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28934 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-06soc/intel/common, mb/google, mb/siemens: Use lower case x for RXDFurquan Shaikh
In order to make the macro name consistent for all PAD_CFG1_IOSSTATE_* macros, this change uses lower case x for *RXD*. It helps avoid confusion when using the macros. Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28924 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-06soc/intel/common/block/hda: Enable static scanning of devices under HDAFurquan Shaikh
This change sets scan_bus operation for HDA to scan_static_bus to allow enumeration of static devices under HDA. BUG=b:112888584 TEST=Verified that devices added under HDA get enumerated on Nocturne. Change-Id: I20759c2b702b2f107f0913e7ce92a82c6070ddc4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28807 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-06soc/intel/.../hda: Add and use config for initialization of HDA codecsFurquan Shaikh
Config option SOC_INTEL_COMMON_BLOCK_HDA is currently used for initialization of HDA codecs only. This prevents adding of any static devices under the HDA device node. However, there can be boards which want to add devices under HDA node (e.g. nocturne that wants to provide DMIC properties to OS) without performing any codec initialization using the HDA. This change: 1. Adds a new config option SOC_INTEL_COMMON_BLOCK_HDA_VERB that can be set explicitly by the boards that want to perform codec initialization. 2. Uses newly added config option is used to guard the initialization functions for the codec. Rest of the device operations can still be used by all the other boards without having to use HDA codec initialization. 3. Selects the newly added option SOC_INTEL_COMMON_BLOCK_HDA_VERB in kblrvp which is the only board enabling HDA codec initialization using common block code. 4. Selects original config SOC_INTEL_COMMON_BLOCK_HDA for skylake SoC. Above changes need to be bundled and pushed in as a single change in order to avoid breaking existing users. BUG=b:112888584 Change-Id: Ie6f39c13a801833b283120a2d4b6f6175688999c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-05soc/intel/skylake: check for NULL with if conditionPratik Prajapati
This patch removes assert() and checks if the dev is NULL with "if" condition only. Found-by: klockwork Change-Id: Icd2c8490c8bda14ecd752437d463a7110fe40aea Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/28888 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-05src: Fix MSR_PKG_CST_CONFIG_CONTROL register nameElyes HAOUAS
Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-10-04soc/intel/cannonlake: Move the FSP related callbacks to separate filesRizwan Qureshi
Move funtions callbacks used to override FSP upd values to separate files. This serves as a base change for SoCs for which FSP is still under development, and hence the FSP header files are not available yet and in turn the UPDs cannot be referred. These newer SoCs will implement empty callbacks. The code will compile with basic header files which only include the architectural FSP structures. This allows plugging in these separate files for compilation in an environment where FSP header files are available. The fact is, FSP header files are not released externally until PRQ. However the teams at intel and some partners have access to the development version of these files. This code refactor helps to continue development on the pre-PRQ silicons and submit related code to coreboot.org. BUG=None BRANCH=None TEST=Build for cnlrvp Change-Id: Iffadc57f6986e688aa1bbe4e5444d105386ad92e Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/28661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04soc/intel/common: add acpi_get_sleep_type to pmclibBora Guvendik
Change-Id: I3f4123657a375211f802a7d484a15353f9a256e9 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/28795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com>
2018-10-04src/soc/intel/cannonlake: Fix IA32_PLATFORM_DCA_CAP addressElyes HAOUAS
Change-Id: Id4f99e82bb97a260d654b49a2ba94fde207d318b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28847 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-03soc/intel/commom/block/i2c: Make I2C controller out of resetSubrata Banik
This patch ensures I2C controllers are out of reset without any assumptions. BUG=b:116191230 BRANCH=none TEST=Dump MMIO offset 0x204 to check if I2C host controller is NOT at reset (by reading Bit 0-1 as 3) Change-Id: I4b335a834333e01cfa2d802e4aad0735d0212dcc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-02src/soc/intel/broadwell/me.c: Correct HMRFPO misspellingAngel Pons
`HMRFPO` was spelled as `HMRPFO` twice. Change-Id: Ibd04004ac5edcdeee49a6a69fcdd5c73603e92e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-10-02soc/intel/skylake: Fix spelling mistakeSubrata Banik
Make correct spelling for THERMAL_IRQ macro in irq.h file. Change-Id: I83593822e2abbb07e60fc336b774199fea3b368f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2018-10-02soc/intel/skylake: Replace white space with tabSubrata Banik
This patch unified line indentation. Change-Id: Ife3396e36a0684490d9ed9b31b4c0a543a3e3d24 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28801 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2018-10-01soc/intel/fsp_broadwell_de: Fix IA32_MC0_* namesElyes HAOUAS
Regarding the SDMs, IA32_MC0_STATUS register is at 0x401, and IA32_MC0_CTL is at 0x400. So replace MSR at (0x400+1) by IA32_MC0_STATUS and the one at 0x400 by IA32_MC0_CTL. Change-Id: I3f53c80f39078bd0c47c25013657e1169fc6c4a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-09-28soc/intel/cannonlake: Fix ACPI FADT table generationDuncan Laurie
The function to fill out the FADT table exits early if the devicetree config option to disable the legacy timer is set. This means it never gets to the later check for s0ix config option and so the flag to indicate that it supports low-power idle in S0 is not set. Change-Id: Ia0416f21b6445f6feecb6f0301d48fdf2522b8a6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/28755 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28soc/intel/cannonlake: Move SkipMpInit config to FSPMLijian Zhao
SkipMpInit UPD had ben moved from Fsp SiliconInit UPD to Fsp MemoryInit UPD, hence change the settings in coreboot side as well. The old options in SiliconInit get deprecated, so leave the code as is will be harmless. Make the changes limited to coffeelake itself. Change-Id: If968de78117068668e4f0006c412442c50658ba9 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28740 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28soc/intel/cannonlake: Add ACPI entry for LANLijian Zhao
Add ACPI DSDT entry for integrated Gigabit LAN controller. Change-Id: I15bf1d4065894531871380b3318f553b637f4a97 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28743 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28soc/intel/cannonlake: Update UPD from device switchLijian Zhao
Some of the FSP silicon UPD entry can be updated base on device switch in pci device tree, have both static config setting and device tree "on" and "off" will be redundant. BUG=N/A TEST=Build and boot up fine with Whiskey Lake RVP platform. Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27766 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-26soc/intel/common/block: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Id82059898844fbe20665250062b67652d6cc1f9e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-22skylake,kabylake: Add support to set eMMC tuning param from dev treePratik Prajapati
Add support to set eMMC tuning params from the device tree so that it can be configured per board. BUG=b:112718426,b:112690628 BRANCH=none TEST=Build nocturne image and checked values passed in dev tree is set by FSP. Change-Id: Ic71934dce9a1c380a057e579ca3fda41983b9385 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/28274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-09-21soc/intel/denverton_ns/csme_ie_kt.c: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I9dde92314af8ef87a5acb550f0fb25b8ce875174 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-21soc/intel/braswell/ramstage.c: Add SoC stepping D-1 supportFrans Hendriks
No support for SoC D-1 stepping is available. According to Intel doc #332095-015 stepping C-0 has revision id 0x21 and D-1 revision ID 0x35. Also correct the RID_C_STEPPING_START value for C-0. BUG=none TEST=Built, Intel Cherry Hill Rev F. Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/27471 Reviewed-by: Wim Vervoorn Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21soc/intel/quark/uart.c: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ia50aa96901b979b947fd4d269b077814c06f60c6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28677 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21soc/intel/skylake: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ifd1471a9cd76d2cea72262ed81b7071f31f7b375 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-21soc/broadwell: Don't use device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: Ifdf3d1870500812a417eaa5e93fcc168629c094f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-21soc/intel/skylake: Include some microcode blobsArthur Heymans
This included the microcode for some CPUID's found in soc/intel/skylake/bootblock/report_platform.c (others are likely pre-release SKU's) The amount of FIT entries needed is currently 7 so setting CPU_INTEL_NUM_FIT_ENTRIES is set to a safe 10 will be able to fit them all. Change-Id: I3ba504a07b2697fe55ff8f28a934f761ae05a4ec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-09-21soc/intel/cannonlake: Correct ITSS port id.praveen hodagatta pranesh
According to cannon lake PCH BIOS specification document #570374 target port id for interrupt and timer subsystem(ITSS) is C4 instead of C2. BUG=None TEST=None Change-Id: I9f8783c682d2c4c4a86e1c9cf4b9c27a18fdf494 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com> Reviewed-on: https://review.coreboot.org/28698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Kin Wai Ng <nelsonaquik@gmail.com>
2018-09-20soc/intel/cannonlake: Remove const for spd_smbus_addressLijian Zhao
Remove const define for spd_smbus_address, the value can be updated depends on platform configuration. TEST=Build and Run on Whiskey Lake rvp platform. Found-by: Converity Scan #1395725 Change-Id: Ib933ed872e9f85087bb3cd76a1f1e29cca75cd54 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28664 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20soc/intel/fsp_broadwell_de: Add fixed VT-d MMIO range to the resourcesWerner Zeh
FSP initializes the VT-d feature on Broadwell-DE and assigns an address space to the MMIO range. coreboot's resource allocator needs to be aware of this fixed resource as otherwise the address can be assigned to a different PCI device. In this case addresses are overlapped and the VT-d range is not accessible any more. To deal with it the right way add a fixed MMIO resource to the resources list if VT-d BAR is enabled. TEST=Booted into Linux and checked coreboot log for resource assignment. Change-Id: I626ac17420eadc0b49031e850f0f40b3b221a098 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/28672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-20fsp_broadwell_de: Move DMAR table generation to corresponding VT-d deviceWerner Zeh
The DMAR table generation depends on the VT-d feature which is implemented in its own PCI device located in PCI:00:05.0 for Broadwell-DE. Add a new PCI driver for this device and move DMAR table generation to this device driver. Change-Id: I103257c73f5e745e996a441a2535b885270bc204 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/28671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-18soc/intel/common/block: Don't use device_t in ramstageElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: If2d643eafea854563f56a7f867b7b492b6d09a19 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28631 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-18cpu/*/car: fix ancient URL explaining XIP range run-time calculationStefan Tauner
Change-Id: I49526b6aafb516a668b7b5e983a0372e3d26a8fc Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-17soc/intel/broadwell: Add PCH_GPIO_PIRQ_INVERT definitionMatt DeVillier
Add definition for PCH_GPIO_PIRQ_INVERT, which is needed for google/buddy, a to-be-merged variant of google/auron. Taken from Chromium commit 70ee99b [buddy: change trigger type of gpio53] Change-Id: I21448160cee791710df51d06efa32cdfecf38c0f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/28611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-14soc/intel/denverton_ns: Enable common block PMCJulien Viard de Galbert
Mainly update headers to build. Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove function configuring the global reset through PMC base. On denverton the global reset lock is not in PMC base but in the PCI registers so this code cannot be shared. Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/25426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Evandro Luiz Hauenstein <kingsumos@gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-13src/*/intel/: clarify Kconfig options regarding IFDStefan Tauner
HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid Inter Flash Descriptor to exist. It does *not* identify platforms or boards that are capable of running in descriptor mode if it's valid. Refine the help text to make this clear. Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply declare that IFD is supported by the platform. Select this value everywhere instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected. Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to the mainboard directory. Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-11soc/intel/baytrail: Remove trailing space in log messagePaul Menzel
Currently, there is a trailing space in the log message below. > Enabling VR PS2 mode: VNN VCC So, put the space before the word. Change-Id: Ic536d77aa910b1b98a3c2f35d595dee4251b1c18 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/28525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-09-10soc/intel/cannonlake: Correct number of root ports for CNL PCH HMaulik V Vaghela
CNL PCH H supports maximum 24 root ports while CNL PCH LP supports maximum 16 root ports. Change-Id: I2cc3ae282d4eb5da8b0618451e062a6c061f1d6f Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/28399 Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10soc/intel/skylake: Add support for CmdTriStateDis UPD in devicetreeShaunak Saha
This patch adds the support for CmdTriStateDis FSP upd in skylake soc structure so that we can define it in devicetree.CmdTriStateDis needed to be set for the skylake/kabylake based boards where LPDDR3 design is without RTT for CMD/CTRL.We need to set this bit for those designs for the margin to be proper. BUG=b:111812662 TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake boards and also check the margin data is proper in FSP. Change-Id: Ida69e443aa6ea4b524bd3ea2dcf26f4e63010291 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/28424 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07fsp_broadwell_de: enable spi consoleOkash Khawaja
this enables spi console for wedge100s with broadwell_de. the console size is 64kb. enabling spi console in `board.fmd` enables code which calls into `timer_monotonic_get` (from `spi_flash_cmd_poll_bit`) and `udelay` (from `ich_status_poll`). this patch selects `TSC_CONSTANT_RATE` in fsp_broadwell_de's Kconfig to satisfy that. Change-Id: Ib925c5aee88b65c46a81534405c364dd5649f8e8 Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com> Reviewed-on: https://review.coreboot.org/28528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-06soc/intel/cannonlake: Fix Coverity Scan reportLijian Zhao
Fix uninitialized variable OnModuleSpd, init bool with false first. BUG=CID 1395330, 1395331 TEST=N/A Change-Id: I050287370f7321ff9905937304bb3cc7f20d8c6a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06soc/intel/common: Add function to set BILD bit in RTCRizwan Qureshi
Add a function to set the Bios Interface Lock Down bit (bit 31) in RTC Configuration register (0x3400). This bit when set prevents the top swap enable bit (bit 0) in the RTC BUC register (0x3414) from being changed. Change-Id: Iacaeeb0d6cabcf0c2c46a58948457ab832351476 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/28057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06chromeos/gnvs: remove function and naming cleanupJoel Kitching
- Remove unused acpi_get_chromeos_acpi_info (see CB:28190) - Make function naming in gnvs.h consistent (start with "chromeos_") BUG=b:112288216 TEST=compile and run on eve Change-Id: I5b0066bc311b0ea995fa30bca1cd9235dc9b7d1b Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-31siemens/mc_apl1: Correct the Tx signal from SATA interfaceMario Scheithauer
Because of an incorrect transmit voltage swing, the signal must be adjusted. The factor of slices for full swing level can be corrected via the High Speed I/O Transmit Control Register 3. Change-Id: I116802cd2a944658fc3022e948eba43cebe52bb4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2018-08-30soc/intel/cannonlake: Fix comment errors for SMBUSLijian Zhao
On CannonLake PCH, SMBUS stays at Bus 0 Device 31 and Function 4, previous comment in southbridge.asl mention it as Function 3 that was a mistake. BUG=N/A TEST=N/A Change-Id: I29786457379809b6fcb592e1136ff612539e24dc Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-08-30soc/intel/cannonlake: Update PMC base address for CNP H and LPMaulik V Vaghela
PMC base address is different for CNP LP pch and CNP H pch. Added logic to determine PMC base addrress dynamically based on PCH ID. BUG=none BRANCH=none TEST=Boot Coffeelake U RVP board and check if PMC base address is determined correctly. Change-Id: I833395260e8fb631823bd03192a092df323250fa Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27523 Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28soc/intel/cannonlake: Change LPDDR4 to MEMCFGLijian Zhao
Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to make the infrasturture to handle both LPDDR4 and DDR4 cases in the future. Consider the case of reading SPD from SMBus other than providing SPD pointer directly. BUG=N/A TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28248 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28siemens/mc_apl1: Extend circuit life by clock gating and power gatingMario Scheithauer
The firmware of devices connected to LPC should deassert the LPC CLKRUN# signal when there is no bus activity on LPC. Necessary changes: - Enable LPC CLKRUN# - Enable LPC PCE (Power Control Enable) - Enable LPC CCE (Clock Control Enable) - Remove I/O decoding range on LPC for COM 3 - Disable I/O UART driver Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-27intel: Use common HPET table revision functionMarc Jones
Use get_acpi_table_revision(HPET) to keep all table versions in sync. Change-Id: Idb5e8ccd49ec27f87a290f33c62df3c177645669 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27update all FADT version 3.0 to use the get tables functionMarc Jones
Most FADT report using ACPIv3 FADT table. Using the get revision function keeps the table versions in sync. Change-Id: Ie554faf1be65c7034dd0836f0029cdc79eae1aed Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-24soc/intel/apollolake: Make eMMC max speed configurableMario Scheithauer
The eMMC maximum speed is set to HS400 mode per default. To increase the lifetime of the circuit, it is necessary to reduce the eMMC speed. Change-Id: I6fa5eb56a0593e24269ef143645c506232879889 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28282 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-22soc/intel/apollolake: Fix logical vs. bitwise operatorJohn Zhao
src/soc/intel/apollolake/chip.c Apply bitwise operator instead of logical one. Found-by: Coverity Scan BRANCH=None TEST=Built & booted Yorp board. Change-Id: I36746b04dec889f53c8d7eeb3b1d8118eff1de42 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-22cbtable: remove chromeos_acpi from cbtableJoel Kitching
Since we can derive chromeos_acpi's location from that of ACPI GNVS, remove chromeos_acpi entry from cbtable and instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET. BUG=b:112288216 TEST=None CQ-DEPEND=CL:1179725 Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-22acpi: remove CBMEM_ID_ACPI_GNVS_PTR entryJoel Kitching
Since we can retrieve the address of ACPI GNVS directly from CBMEM_ID_ACPI_GNVS, there is no need to store and update a pointer separately. TEST=Compile and run on Eve Signed-off-by: Joel Kitching <kitching@google.com> Change-Id: I59f3d0547a4a724e66617c791ad82c9f504cadea Reviewed-on: https://review.coreboot.org/28189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-21soc/intel/skylake: Remove unsupported sleepstates in ACPI tableLucas Chen
Some OS certification test (for example Windows) will fail if there are unsupported sleep states. Since these states are not really used today, we can remove them from ACPI table. BRANCH=eve BUG=b:72197653 TEST=certification system sleep test pass. Change-Id: I5f5122cac1bf61f7c580afb18cc66b5ff07286fb Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1065401 Commit-Queue: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://review.coreboot.org/28080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-20soc/intel/skylake: Support PL1 override optionWei Shun Chang
In legacy mode, DPTF on some systems may rely on MMIO to control PL1 settings. However, MSR PL1 also contributes to the decision of max PL1 power; and in the current design, the lower value takes effect. In order to align MMIO and MSR settings, a tdp_pl1_override option is added to override the MSR PL1 limitation. BRANCH=eve BUG=b:73133864 TEST=1. Write PL1 override setting in devicetree.cb 2. Verify the MSR PL1 limitation is set correctly. Change-Id: I35b8747ad3ee4c68c30d49a9436aa319360bab9b Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20soc/intel/skylake: add CPPC supportMatt Delco
ACPI 5.0 defines a method _CPC for "Continuous Performance Control" (CPPC). Linux has a driver that enables features like speed shift without consulting ACPI. Other OSes instead rely on this information and need a _CPC present. Prior to this change performance in Win10 never exceeds 80% and MSR 0x770 is 0, while with this change (and enabling eist) higher speeds can be achieved and the MSR value is now 1. Change-Id: Ib7e0ae13f4b664b51e42f963e53c71f8832be062 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-20soc/intel/common/block: Move common uart function to block/uartSubrata Banik
This patch moves uart functions which are common across multiple soc to block/uart. This will remove redundant code copy from soc {skylake/apollolake/cannonlake}. BUG=b:78109109 BRANCH=none TEST=Build and boot on KBL/APL/CNL platform. Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20soc/intel/common/block: Add WHL 2-core SKUKrzysztof Sywula
There are two SKUs of Whiskey Lake W0, 2-core and 4-core. Change-Id: Ia9b2707568702a5fbae3e9495ca53df34613a542 Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com> Reviewed-on: https://review.coreboot.org/28111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20soc/intel/apollolake: Force USB-C into host modeJohn Zhao
When USB OTG is set, GLK FSP enables xHCI SW ID pin and configures USB-C as device mode. Force USB-C into host mode. BUG=b:111623911 TEST=Verified that USB-C being host mode once USB OTG is set. Change-Id: Iaca3d25a1159f922b743963cbc508d8defa7b6ff Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20intel/common/block: Fix issues found by klockworkJohn Zhao
src/soc/intel/common/block/cpu/mp_init.c Function init_cpus: Pointer dev checked for NULL may be dereferenced. src/soc/intel/common/block/graphics/graphics.c Function graphics_get_bar: Pointer dev returned from call may be NULL and will be dereferenced. BRANCH=None TEST=Built & booted Yorp board. Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-17soc/intel/skylake: permit Kconfig to set subsystem IDMatt Delco
This change permits the subsystem ID to be specified via Kconfig for the devices on the SoC. Some devices are getting zero'ed subsystem IDs because the unset (and thus zero'ed) config options are overwriting the fsp defaults. With this change the fsp defaults will only be overwritten by non-zero config values. Change-Id: I0f7bb8e465f55e5dd6d8e0fad71b9b2a22f089dc Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-13soc/intel/broadwell/Kconfig: Clean up redefined config optionsArthur Heymans
All broadwell board set HAVE_IFD_BIN to default n, overloading the option in soc, therefore just use the defaults in sb/intel/common/firmware. Change-Id: I250dbbc9d61ecedc1a1eb48751ad966732604349 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28011 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13soc/intel/braswell/Kconfig: Clean up redefined config optionsArthur Heymans
There is no need to redefine option present in southbridge/intel/common/firmware/Kconfig. FAKE_IFD depends on out tree flashrom patches for which there are better alternatives available now, so don't build with FAKE_IFD by default. Change-Id: Icd41137a1bbfe519c89a71cc0c7c3755558bd834 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28010 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13fsp_broadwell_de: Increase CONFIG_MAX_CPUS to 32Samuel Jimenez
Fix to accomodate for boards with more than 16 cores. Change-Id: I35b61d94491c21ef76717f761e566ca815880f27 Signed-off-by: Samuel Jimenez <aerojsam@gmail.com> Reviewed-on: https://review.coreboot.org/27847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-13soc/intel/skylake: use unique _uidMatt Delco
There's two cases of 1 being used. This changes the eighth instance to use 8. Change-Id: I7057a4345dadcc6f8fb43093844d27007444f481 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-13intel/apollolake: Fix typo in dptf.aslChris Zhou
Fix define typo in dptf.asl BUG=none TEST=emerge-octopus coreboot PASS Change-Id: I1c3bd55d1507e6fffe638bba38c99a9851b8a96a Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-08-12soc/intel/apollolake: Get rid of cnvi.aslFurquan Shaikh
There is no need to add a special cnvi.asl file for the CNVi device. This can be handled by drivers/intel/wifi just like a PCIe WiFi device. This change gets rid of the cnvi.asl file and its usage in southbridge.asl file. BUG=b:112371978 Change-Id: I0b798cdd430768730b7ada61ca4cb1f63c2a4229 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-12soc/intel/apollolake: Add CNVi device to list of PCI devsFurquan Shaikh
This change adds CNVi device to list of PCI devs. BUG=b:112371978 Change-Id: I6def98db3846c2244812a9a2ce84340bd2149b48 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-10drivers/i2c: Add i2c TPM support for different stagesPhilipp Deppenwiese
Change-Id: Ib0839933f8b59f0c87cdda4e5374828bd6f1099f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/23759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-08-10src: Fix typoElyes HAOUAS
Change-Id: I689c5663ef59861f79b68220abd146144f7618de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-10src/soc/intel: Add new device IDs to support coffeelakeMaulik
1. Add new device IDs for SATA, GT and Northbridge to pci_ids.h 2. Add entry to identify CFL U GT and CPU to respective files 3. Add entry to identify CFL U to report_platform.c BUG=none BRANCH=none TEST=Boot to CFL U RVP board with this patch and check if coreboot is able to enumerate various devices and display correct component names properly in serial logs. Change-Id: I47c97fb9eb813587cd655e2bce05a686091619ed Signed-off-by: Maulik <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-08-09src/soc: Fix typoElyes HAOUAS
Change-Id: I8053d0f0863aa4d93692487f1ca802195c2d475f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-08soc/intel/apollolake: add new dimm info saving APIAaron Durbin
The current call for saving dimm info passed the lpddr4_cfg and memory sku id. In order to prepare decoupling the part number from lpddr4_cfg provide a new API, save_lpddr4_dimm_info_part_num(), which explicitly takes the part number. The previous API now uses the new one internally. BUG=b:112203105 Change-Id: Ieadf452b6daa3231a0c5e3be61b0603b40d0fff2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-08soc/intel/apollolake: Add support for LPDDR4 nWR settingRavi Sarawadi
nWR (Write-Recovery for AutoPre-charge commands), the programmed value of nWR is the number of clock cycles the LPDDR4-SDRAM device uses to determine the starting point of an internal Pre-charge operation after a Write burst with AP (auto-pre-charge) enabled. For >2133MHz speed parts the nWR needs to be set to 24 clock cycles. The nWR field, though, is only in the GLK FSP, so just update that field conditionally based on the GLK Kconfig option. BUG=b:112062440 TEST= build test Change-Id: I1147538f72f4e2f14e32f3657c05f1f505a56fbf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/27850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-08src/soc/intel/common: Configure the gspi chip select state correctlyAamir Bohra
This implementation updates the chip select control register programming in gspi controller setup call to program the correct bit fields for chip select state. Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920a53 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/27889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06src/soc/intel: Add AML IGD in platform reportingGaggery Tsai
This patch revises IGD naming and adds AML IGD in platform reporting. BUG=None BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage & Ensure AML IGD is shown in platform reporting. Change-Id: Id8f8379703abdaa5b14a4337a4fca04b370f3a2a Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06soc/intel/skl: Add AML IccMax and remove unused infoGaggery Tsai
This patch adds AML IccMax for VR configuration. From doc #594883, the IccMax for Core was changed to 28A, we need this patch to accommodate the changes. Besides, removes unused sku information from sku_icc_max_mapping structure. BUG=b:110890675 BRANCH=None TEST=Remove icc_max from DT & emerge-atlas coreboot chromeos-bootimage & Tested with AML-Y and KBL-Y SKUs. Change-Id: Ic22bae162b58b06b9519f1b708be55bde5e4641e Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27610 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-03soc/intel/cannonlake: Report Whiskey Lake infoLijian Zhao
According to #574725, report Whiskey Lake CPUID, MCH device ID and graphics device ID in bootblock stage. BUG=N/A TEST=Build and boot up whiskey lake rvp platform and check serial log to see proper CPU/MCH/GFX/PCH got recognized. Change-Id: I3fbc190e0520989d2fd4a9b3294e84d67e49b2cf Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2018-08-03soc/intel/coffeelake: Add initial coffeelake supportLijian Zhao
Add coffeelake config and include path to coffeelake fsp header files. BUG=N/A TEST=Using private mainboard file can boot up on coffeelake rvp platform. Change-Id: Ide180de32a9d1896bed85b9e093963721c3d6041 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27468 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-02google/cyan: Switch Touchpad and Touchscreen interrupts to be level-triggeredMatt DeVillier
Adapted from chromium commit 126d352 [Strago: switch Touchpad and Touchscreen interrupts to be level-triggered] The Elan and other touch controllers found in this device work much more reliably if used with level-triggered interrupts rather than edge-triggered. TEST=Boot several cyan boards, verify that touchpad and touchscreen work. Original-Change-Id: I59d05d9dfa9c41e5472d756ef51f0817a503c889 Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/894689 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia4f8cf83351dae0d78995ce0b0ed902d1e4ac3e8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-01soc/intel/common/block: Add WhiskeyLake (WHL) IDsKrzysztof Sywula
Specifically PCI device ID for graphics and PCI device ID for northbridge. Change-Id: Ide237d3274df0543409c8a23b9bb50c8e0a6b7a3 Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com> Reviewed-on: https://review.coreboot.org/27519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kin Wai Ng <kin.wai.ng@intel.com>
2018-07-30soc/intel/common: Add support to configure top swap featureAamir Bohra
RTC BUC control register provides a software interface to configure the top swap feature. This patch adds implementation to enable/disable top swap feature and gets it accessible in romstage as well. The top swap control functions are exposed only if INTEL_HAS_TOP_SWAP is selected. To use the topswap feature a second bootblock has to be added to the cbfs. Below configs aid in doing that, INTEL_HAS_TOP_SWAP INTEL_ADD_TOP_SWAP_BOOTBLOCK INTEL_TOP_SWAP_BOOTBLOCK_SIZE Enabling and Disabling topswap, using the added API enables user to boot alternatively from either bootblock. Change-Id: Iea31b891f81e76d4d623fcb68183c3ad3dcadbad Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/25805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-30soc/intel/fsp_baytrail: Add VBOOT supportPhilipp Deppenwiese
* Add vbnv_cmos_failed function to SoC. * Add VBOOT starts in romstage select. Change-Id: I90a051e2b8d303c918bef976d0bb07aae0b1f5b3 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/27728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 19:19:22 +0000