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2021-01-23ACPI: Add helpers for CBMEM_ID_POWER_STATEKyösti Mälkki
Create uniform logging for the (unlikely) case of a CBMEM entry disappearing. Change-Id: I7c5414a03d869423c8ae5192a990fde5f9582f2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-23intel/baytrail,braswell,broadwell: Add const qualifier for power_stateKyösti Mälkki
Change-Id: I37781c1423b49130ffd0d5f9fbdd28a36c9c6179 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49821 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-23ELOG: Add const qualifier for chipset_power_stateKyösti Mälkki
It is never allowed for ELOG to modify the state. Change-Id: Ie24df3969a3744f27b23997471666e2490e24b84 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-23soc/intel/cometlake: Add ucode for CML-HTim Crawford
Add microcode from 3rdparty repo for: - 06-a5-02 (CPUID signature: 0xa0652) Change-Id: I95419f44a1e804ce31338fe6d863f156c655321b Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47915 Reviewed-by: Jeremy Soller <jeremy@system76.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-23soc/intel/apl: drop LPC pad configuration codeMichael Niewöhner
Drop LPC pad configuration code since all boards now do pad configuration on their own. The comment about LPC_CLKRUNB when using eSPI is moved to `Documentation/getting_started/gpio.md`. Change-Id: I710d6aee8c3b2c8282cd321cd0688b9b26abea07 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49410 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22soc/intel/alderlake: Adding Kconfig for ADL_M PCHVarshit Pandya
1. Add SOC_INTEL_ALDERLAKE_PCH_M option in Kconfig 2. Select number of I/O based on PCH Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I38783595e4b85abf5b3bec234ba01667bd9ba754 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49630 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22soc/intel/commmon: Include Alder Lake device IDsVarshit Pandya
Add Alder Lake M specific CPU, System AGent, PCH (Alder Point aka ADP), IGD device IDs. Document Number: 619501, 626817 Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: Ib13fe229f9e65eae8967aa20e28e29ac5c319265 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49629 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-22soc/intel/baytrail,broadwell: Refactor acpi_wake_source()Kyösti Mälkki
Change-Id: I5c277a4b8536fd79bda040d4ada9b0c454399b09 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49356 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21soc/intel/quark: Add pwrs in <soc/nvs.h>Kyösti Mälkki
For the time being every soc/intel selects ACPI_SOC_NVS and pwrs is a required field for the common initialisation implementation of followup work. Change-Id: I4a0c7eb35f0646898e49fad15c6448607c398731 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49493 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-21soc/intel/cannonlake: Allow RP#1 usage for ClkSrcJeremy Soller
0 is converted to not used, so use a special value to allow using PCIe root port #1. Change-Id: I2d64afc9bb4627913492edad8f36566e7fb18166 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-21soc/intel/common/pcie_rp.h: Fix comment styleFurquan Shaikh
This change updates pcie_rp.h to reflow the comment blocks to fit within 80 columns to match the original style of the file. This addresses comment received on CB:49370 (https://review.coreboot.org/c/coreboot/+/49370/comment/0f3fe10d_4e218b5f/). Change-Id: I565ad602e0e3a2ee09e8345479d82e2ce0a31fd0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-21soc/intel/alderlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGDSubrata Banik
Make IGD disable when mainboard user selects SOC_INTEL_DISABLE_IGD. TEST=Able to get depthcharge pre-OS splash screen with AMD Radeon RX 5700 PCI-E DGPU when mainboard user selects SOC_INTEL_DISABLE_IGD. Change-Id: Ibbe9c8c4d77018de83815d7d203284b1fbc0da58 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-21soc/intel/common/graphics: Add new Kconfig SOC_INTEL_DISABLE_IGDSubrata Banik
This SOC_INTEL_DISABLE_IGD Kconfig will allow to skip IGD initialization using FSP GOP and eventually disable the IGD. TEST=Able to get depthcharge pre-OS splash screen when mainboard user selects SOC_INTEL_DISABLE_IGD with below HW/FW/SW configuration: HW: ADLRVP + AMD Radeon RX 5700 PCI-E DGPU FW: coreboot with depthcharge as payload for ADLRVP and OpRom for AMD PCI-E DGPU SW: Chrome OS RC10 release Change-Id: I465541cb45c9022d53a5beb3fff1f80660c357c9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-20soc/intel: fix indentation in intelblocks/lpc_lib.hMichael Niewöhner
Change-Id: I28be6091097f713472d5ca3b8b0921ee71238cf0 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-01-20soc/intel/*: drop broken LPC mmio codeMichael Niewöhner
The code for setting the LPC generic memory range uses an array of fixed address ranges not needing explicit decoding, to decide if the address needs to be written to the LGMR register. Most platforms only mistakenly add the PCH reserved mmio range, that is not decoded generally, effectively breaking the mechanism. Only APL uses the array correctly. That code, in it's current state, does not work (except for APL) and currently, there is not a single user. Thus, drop it before people start using it. Change-Id: I723415fedd1b1d95c502badf7b0510a1338b11ac Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-20ACPI GNVS: Drop most dev_count_cpu()Kyösti Mälkki
Only amd/picasso and amd/stoneyridge have reference to PCNT and that could be replaced with acpigen. Remove the PCNT name from GNVS OperationRegion elsewhere. Change-Id: I7dd45a840b3585fd24c31fd923b991c34ab4d783 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-19intel/xeon_sp, mb/ocp/deltalake: Rework get_stack_busnos()Maxim Polyakov
- Return the busno based on the stack number. - Replace pci_mmio_read_config32 with pci_io_read_config32 to get the register value before mapping the MMIOCFG space. - Remove the plural `s` as the function now provides one bus number. Change-Id: I6e78e31b8ab89b1bdcfdeffae2e193e698385186 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-18ACPI: Refactor ChromeOS specific ACPI GNVSKyösti Mälkki
The layout of GNVS has expectation for a fixed size array for chromeos_acpi_t. This allows us to reduce the exposure of <chromeos/gnvs.h>. If chromeos_acpi_t was the last entry in struct global_nvs padding at the end is also removed. If device_nvs_t exists, place a properly sized reserve for chromeos_acpi_t in the middle. Allocation from cbmem is adjusted such that it matches exactly the OperationRegion size defined inside the ASL. Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-18soc/intel/braswell/chip.c: Use __func__Elyes HAOUAS
Change-Id: I96b302f5a1f10daaed017a2453d1568a2e49e4ad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-18soc/intel/xeon_sp/uncore.c: Remove duplicated includeElyes HAOUAS
Change-Id: I2ac1035585b32ba65d0725067cff0c12c9f748c1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-18soc/intel/xeon_sp/skx/soc_acpi.c: Remove duplicated includeElyes HAOUAS
Change-Id: Icf4247a0a5fb7950c69c8f229a6629a4fa6980f7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-01-18soc/intel/broadwell/bootblock.c: Remove repeated wordElyes HAOUAS
Change-Id: I3aec07d782e4315120a4365a65bdbcbf4a22e6f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/intel/common/block/include/intelblocks/pmc_ipc.h: Remove repeated wordElyes HAOUAS
Change-Id: I646583f7f0d0e0f6a91bc99b7edda964337d837e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/intel/common/block/itss/itss.c: Remove repeated wordElyes HAOUAS
Change-Id: Icc4954bcc1540f1935b0e34107febb4a1e947a36 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/intel/skylake/chip.h: Remove repeated wordElyes HAOUAS
Change-Id: Id5bf9255e9a16a4f311e3b15eb77ad6e4bb13f66 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2021-01-18soc/intel/alderlake: Update PCH and CPU PCIe RP tableEric Lai
According ADL EDS to update the PCH and CPU PCIe RP table. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-18soc/intel/common: Move L1_substates_control to pcie_rp.hEric Lai
L1_substates_control is common define. Move out of soc level. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I54574b606985e82d00beb1a61cce3097580366a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-18soc/intel/common/pcie: Allow pcie_rp_group table to be non-contiguousFurquan Shaikh
In case of CPU PCIe RPs, the RP numbers might not be contiguous for all the functions in a slot. Example: In ADL, RP1 is 00:06.0, RP2 is 00:01.0 and RP3 is 00:06.2 as per the FSP expectations. Hence, this change updates the defintion of `struct pcie_rp_group` to include a `start` member which indicates the starting PCI function number within the group. All common functions for PCIe RP are accordingly updated to take the `start` member into account. Thus, in the above example, ADL can provide a cpu_rp_table as follows: { { .slot = PCIE_SLOT_6, .start = 0, .count = 1 }, { .slot = PCIE_SLOT_1, .start = 0, .count = 1 }, { .slot = PCIE_SLOT_6, .start = 2, .count = 1 }, } Since start defaults to 0 when uninitialized, current PCH RP group tables don't need to be updated. Change-Id: Idf80a0f29e7c315105f76a7460c8e1e8f9a10d25 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49370 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15soc/intel/braswell: Prevent NULL pointer dereferenceAngel Pons
Exit early if the chipset power state info isn't in CBMEM. Return -1 in order to ensure the one caller of this function exits early as well. Found-by: Coverity CID 1442304 Change-Id: Ifa42ba3024d3144de486d90ed7752820482549bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49359 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-15cpu/x86/mpinit: Serialize microcode updates for HT threadsPatrick Rudolph
This change affects Intel CPUs only. As most platforms are doing uCode update using FIT, they aren't affected by this code either. Update microcode in MP-init using a single spinlock when running on a Hyper-Threading enabled CPU on pre FIT platforms. This will slow down the MP-init boot flow. Intel SDM and various BWGs specify to use a semaphore to update microcode on one thread per core on Hyper-Threading enabled CPUs. Due to this complex code would be necessary to determine the core #ID, initializing and picking the right semaphore out of CONFIG_MAX_CPUS / 2. Instead use the existing global spinlock already present in MPinit code. Assuming that only pre-FIT platforms with Hyper-Threading enabled and at most 8 threads will ever run into this condition, the boot delay is negligible. This change is a counterproposal to the previous published patch series being much more unsophisticated. Change-Id: I27bf5177859c12e92d6ce7a2966c965d7262b472 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-14soc/intel/tgl: Add configurable value for UsbTcPortEnBrandon Breitenstein
As a requirement of TCSS this setting needs to be correctly set to determine what Type-C ports are enabled on the platform. Without this value correctly set there can be adverse effects on the other TCSS specific values. BUG=b:159151238 BRANCH=firmware-volteer-13672.B TEST=Built image for Voxel and verified that S0ix cycles no longer fail when the IomPortPad is set to 0 Change-Id: I6c5260cda71041439fe89d15bd3cafd4052ef1e7 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2021-01-14build system: Structure and serialize INTERMEDIATEPatrick Georgi
Target added to INTERMEDIATE all operate on coreboot.pre, each modifying the file in some way. When running them in parallel, coreboot.pre can be read from and written to in parallel which can corrupt the result. Add a function to create those rules that also adds existing INTERMEDIATE targets to enforce an order (as established by evaluation order of Makefile.inc files). While at it, also add the addition to the PHONY target so we don't forget it. BUG=chromium:1154313, b:174585424 TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2 timeout and sercon) and saw that they were executed. Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-13ACPI: Have single call-site for acpi_inject_nvsa()Kyösti Mälkki
Change-Id: I61a9b07ec3fdaeef0622df82e106405f01e89a9e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48719 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-13ACPI: Add common acpi_fill_gnvs()Kyösti Mälkki
Change-Id: I515e830808a95eee3ce72b16fd26da6ec79dac85 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48718 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-13soc/intel/tigerlake: Disable TC cold supportSrinidhi N Kaushik
This change lets IOM consider all USB connected devices as device attached(DA) scenario. While connecting a typec-to-a dongle, IOM would disable TC cold and help to resolve enemuration failure after usb3 device is plugged into the dongle. BUG=b:173054070 TEST=Build and boot on delbin. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I0ad0322693b4f8fbf1000b24eb21dddcebec686b Reviewed-on: https://review.coreboot.org/c/coreboot/+/49244 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-12soc/intel: rename uart_max_indexMichael Niewöhner
The name `..._index` is confusing since the maximum index of an array is not `ARRAY_SIZE(array)` but `ARRAY_SIZE(array) - 1`. Rename `uart_max_index` to `uart_ctrlr_config_size` to make the name match the variable´s value. Change-Id: I7409c9dc040c3c6ad718abc96f268c187d50d79c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-01-12soc/intel/denverton_ns: Drop redundant `DEFAULT_ACPI_BASE`Angel Pons
It is only used in one place, and there's two other equivalent macros. Change-Id: I7c8241e28f688abd2df8180559dd02ee441c7023 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-12soc/intel/common/pcie: Add helper function for getting mask of enabled portsFurquan Shaikh
This change adds a helper function `pcie_rp_enable_mask()` that returns a 32-bit mask indicating the status (enabled/disabled) of PCIe root ports (in the groups table) as configured by the mainboard in the device tree. With this helper function, SoC chip config does not need to add another `PcieRpEnable[]` config to identify what root ports are enabled. Change-Id: I7ce5fca1c662064fd21f0961dac13cda1fa2ca44 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48968 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-12soc/intel/alderlake: Add PCH ID 0x5182Subrata Banik
TEST=Able to build and boot ADLRVP. Change-Id: Ia331998b46abcf10e939078dea992589f09139bd Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49301 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11soc/intel/{icl,tgl,jsl,ehl}: add LPIT supportMichael Niewöhner
Add SLP_S0 residency register and enable LPIT support. Change-Id: Id1abbe8dcb7796eeb26ccb72f1f26cf7a040dba4 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49048 Reviewed-by: Lance Zhao Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11soc/intel/skl: add SLP_S0 residency register and enable LPIT supportMichael Niewöhner
Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1 boots without crashing with an INTERNAL_POWER_ERROR. Change-Id: Icccd9d15a9e9a22c9bfe7a9843e95d77013c9c8f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49047 Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11soc/intel/cnl: add SLP_S0 residency register and enable LPIT supportMichael Niewöhner
Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1 boots without crashing with an INTERNAL_POWER_ERROR. - Windows and Linux tested on google/akemi - Linux tested on clevo/cml-u Change-Id: I51fdf52419aa7f059b70a906fd8bdac88d5b6046 Tested-By: Matt DeVillier <matt.devillier@gmail.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49046 Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11acpi,soc/intel/common: add support for Intel Low Power Idle TableMichael Niewöhner
Add support for the Intel LPIT table to support reading Low Power Idle Residency counters by the OS. On platforms supporting S0ix sleep states there can be two types of residencies: * CPU package PC10 residency counter (read from MSR via FFH interface) * PCH SLP_S0 assertion residency counter (read via memory mapped interface) With presence of one or both of these counters in the LPIT table, Linux dynamically adds the corresponding attributes to the cpuidle sysfs interface, that can be used to read the residency timers: * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us * /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us The code in src/acpi implements generic LPIT support. Each SoC or platform has to implement `acpi_fill_lpit` to fill the table with platform-specific LPI state entries. This is done in this change for soc/intel/common, while being added as its own compilation unit, so SoCs not yet using common acpi code (like Skylake) can use it, too. Reference: https://uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.pdf Test: Linux adds the cpuidle sysfs interface; Windows with s0ix_enable=1 boots without crashing with an INTERNAL_POWER_ERROR. - Windows and Linux tested on google/akemi together with CB:49046 - Linux tested on clevo/cml-u, supermicro/x11ssmf together with CB:49046 Change-Id: I816888e8788e2f04c89f20d6ea1654d2f35cf18e Tested-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-11{soc,vc,mb}/intel: Drop support for Cannon Lake SoCFelix Singer
Drop the support for the Intel Cannon Lake SoC for various reasons: * Most people can't use coreboot on Cannon Lake, since the required FSP binaries aren't publicly available. Given that FSP binaries for several newer platforms have been released, it's very unlikely that Cannon Lake FSP will ever be released. * It seems there is no interest in this, since the reference mainboard is the only available mainboard in tree. Also, remove the related reference mainboard intel/cannonlake_rvp and its FSP headers in intel/fsp2_0/cannonlake. Change-Id: I8f698e16099acb45444b2bc675642d161ff8c237 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48775 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11soc/intel/common/uart: Use simple(_s_) variants of PCI functionsFurquan Shaikh
This change updates various uart_* functions to use simple(_s_) variants of PCI functions. This is done for a few reasons: * __SIMPLE_DEVICE__ check can be dropped since the same data type can be used in early stages and ramstage. * Removes the requirement on early stage to walk the device tree to get access to the device structure. This allows linker-based device tree optimizations for early stages. As part of this change, uart_get_device() is refactored and a new function uart_console_get_devfn() is added which returns pci_devfn_t in MMCONF format. It is then used directly by the _s_ variants of PCI functions. Change-Id: I344037828118572ae5eb27c82c496d5e7a508a53 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-11soc/intel/uart: Drop SoC callback `soc_uart_console_to_device`Furquan Shaikh
This change renames `struct uart_gpio_pad_config` to `struct uart_controller_config` and adds a new parameter devfn (which expects devfn for the UART controller corresponding to the index in PCI_DEVFN() format). This gets rid of the SoC callback to get `struct device` pointer to the UART controller device. Change-Id: Id0712a0038f2cc1a61b8b5a58fa155f14e7949a5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49212 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-SJeremy Soller
Prevent the FSP from writing its default SVID SDID values of 8086:7270 for internal devices as this locks most of the registers. Allows the subsystemid values set in devicetree to be used. A description of this SSID table override behavior, along with example code, is provided in the TigerLake FSP Integration Guide, section 15.178 ("SI_CONFIG Struct Reference"). The xHCI and HDA devices have RW/L registers rather than RW/O registers. They can be written to multiple times but cannot be modified after being locked, which happens during FspSiliconInit. Because coreboot populates subsystem IDs after SiliconInit, these devices specifically must be written beforehand or will otherwise be locked with their default values of 0:0. Tested by checking lspci output on System76 galp3-c (WHL), oryp5 (CFL), and oryp6 (CML). References: - TigerLake FSP Integration Guide - Intel Document Number 337868-002 Change-Id: Ieaa45ef7fa8e0da4a25b9174ded1ea0c5d9c4b4e Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49104 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-11soc/intel/cannonlake: Enable wake from USB in S4Patrick Rudolph
The xHCI controller supports waking the system from S1-S4. Thus specify that the deepest sleep state is S4 in _PRW. Tested on Prodrive/hermes. The board now wakes from S4 as well by pressing a key on the USB keyboard. Change-Id: I0bb266e70ee6b4eb8922671b7d0078db0d29a1da Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49224 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPsSubrata Banik
List of changes: 1. Create new Kconfig MAX_CPU_ROOT_PORTS and MAX_PCH_ROOT_PORTS as per EDS. 2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards. 3. Rename PcieRpEnable to PchPcieRpEnable. 4. Enable CPU RPs as below in mainboard devicetree.cb RP1: PEG60 : 0:6:0 : CPU SSD1 RP2: PEG10 : 0:1:0 : x8 CPU Slot RP3: PEG62 : 0:6:2 : CPU SSD2 Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49136 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10soc/intel/broadwell: Use `mp_cpu_bus_init`Angel Pons
This is needed to allow switching to Haswell CPU code in the future. Change-Id: Ic642f32f9c4a269a66ac470b7a7217f20ff8bfba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46886 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10mb/google/cyan: Move board_id() to mainboard_fill_gnvs()Kyösti Mälkki
Only a google/cyan variant evalutes BDID in ASL. Change-Id: I3d839333333b4762ae5350734c85471a3c12838a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49003 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Add missing include in nvs.hKyösti Mälkki
Change-Id: Ic779a668ebaa4f0c9bdef95fd6de8f0179e8a534 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49004 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10soc/intel: Rename to soc_fill_gnvs()Kyösti Mälkki
Replace acpi_create_gnvs() under soc/ to reflect their changed funcionality. Change-Id: I7bdbe0d6f795252e713e9785ada2b6320e6604b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48717 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10soc/intel: Replace acpi_init_gnvs()Kyösti Mälkki
Rename these to soc_fill_gnvs() and move the callsite away from mb/. Change-Id: I760c36f65c6122103f2be98fc11ee13832c2772e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48716 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10mb/x/acpi_tables: Rename to mainboard_fill_gnvs()Kyösti Mälkki
Rename acpi_create_gnvs() functions under mb/ to reflect their changed functionality. Remove now empty mb/acpi_tables.c files. Change-Id: Ia366867ef73d1ade9805dc29b8e14b3073f44f60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48707 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10sb/intel: Factor out soc_fill_gnvs()Kyösti Mälkki
Name the common part of GNVS initialisation as soc_fill_gnvs(). It is also moved before the call to acpi_create_gnvs(), which followup will rename to mainbord_fill_gnvs() to reflect that implementation is under mb/. Change-Id: Ic4cf1548b65a86212d6e45d460fcd23bb8036365 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48706 Reviewed-by: Lance Zhao Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Replace uses of CBMEM_ID_ACPI_GNVSKyösti Mälkki
Change-Id: I45a2d9cb7f07609a1ff03fd70f17c3f2d4f013b9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48705 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10soc/intel/braswell: Refactor acpi_init_gnvs()Kyösti Mälkki
Move GNVS details to different function, called from acpi_create_gnvs(). Change-Id: Ief02c078fe37753c0d29418394a351105a1aacc8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48704 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Drop redundant ChromeOS setup for GNVSKyösti Mälkki
Already done in common gnvs_get_or_create() implementation once gnvs_chromeos_ptr() is defined for platforms. Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Drop redundant CONSOLE_CBMEM setup in GNVSKyösti Mälkki
Already done from common gnvs_get_or_create() implementation after gnvs_cbmc_ptr() is defined. Change-Id: I77c292cd9590d7fc54d8b21ea62717a2d77e5ba4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48702 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-10ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocationsKyösti Mälkki
Allocation now happens prior to device enumeration. The step cbmem_add() is a no-op here, if reached for some boards. The memset() here is also redundant and becomes harmful with followup works, as it would wipe out the CBMEM console and ChromeOS related fields without them being set again. Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08soc/intel/common/uart: Restrict scope of uart_common_init to uart.cFurquan Shaikh
uart_common_init is not used outside of soc/intel/common/block/uart.c. This change restricts the scope to this file and drops the declaration from uart.h Change-Id: I499a53506f9b2e91ecc7334bf9b023d342e802fc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49211 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08soc/intel/common: Pass in pci_devfn_t into lpss_set_power_stateFurquan Shaikh
This change updates the parameter passed into `lpss_set_power_state()` from struct device * to pci_devfn_t. This allows the users in the early stages to use pci_devfn_t instead of having to walk the device tree to get a pointer to the relevant device structure. It is important for optimizing out unnecessary components of the device tree from the early stages. Change-Id: Ic9e32794da65348fe2a0a2791db47ab83b64cb0f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49210 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08soc/intel: Drop `dev` parameter from soc_get_gen_io_dec_range()Furquan Shaikh
This change drops the parameter `struct device *dev` from the function `soc_get_gen_io_dec_range()`. This function uses the parameter dev to get a pointer to config structure for extracting the decode ranges configured by mainboard in device tree. However, there is no separate chip driver for the LPC device which means that the SoC code can use `config_of_soc()` to get to SoC chip config instead of using the LPC device. This change is being done in preparation to clean up the device tree/chip config access in early stages that allows for optimizing the inclusion of device tree elements in the early stages. Change-Id: I3ea53ddc771f592dd0ea5e5e809be2d2eff7f16d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-08soc/intel/tigerlake: Enable USB2 port reset message on Type-C portsJohn Zhao
USB3 is in CPU and USB2 in PCH on Tigerlake. Cross die messaging is implemented between CPU and PCH through the IOSF SB bridge. a PCH xHCI USB2 port reset event issued by the xHCI driver shall trigger a message upstream to CPU to wake it from the low power state which allows a USB3 device that downgraded to USB2 to upgrade back to USB3. BUG=b:176575892 TEST=Built and booted to kernel on Voxel board. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f Reviewed-on: https://review.coreboot.org/c/coreboot/+/49052 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08*/Makefile.inc: Add some INTERMEDIATE targets to .PHONYArthur Heymans
Change-Id: I125e40204f3a9602ee5810d341ef40f9f50d045b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48897 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-08soc/intel/jasperlake: Update acoustic noise related parametersMaulik V Vaghela
We need to fill Acoustic noise mitigation related UPDs only in case when acoustic noise mitigation is enabled. This will also clarify the user that they need to enable Acoustic noise mitigation while using this config in mainboard. We're only filling UPD for domain VR index 0 since there is only one VR domain for JSL (VCCIN VR). Reference: JSL EDS (Document# 613601) (Chapter 3.4) BUG=None BRANCH=dedede TEST=UPD values are getting filled correctly when Acoustic noise mitigation is enabled. Change-Id: I0cf4ccfced13b0d32b3d20713eace63e66945332 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-01-08soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualificationKrishna Prasad Bhat
USBSUSPGQDIS is a disqualifier bit which will allow platform to enter s0ix even if USB2 PHY SUS is not power gated. Disabling this bit will ensure that USB2 PHY SUS is power gated before entering s0ix. BUG=b:175767084 BRANCH=dedede TEST=s0ix works on drawcia and USB wake from s0ix works fine. Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Evan Green <evgreen@chromium.org>
2021-01-07ACPI: Remove ACPI_NO_SMI_GNVSKyösti Mälkki
This was used as a guard to not raise SMI with APM_CNT_GNVS_UPDATE. The handler has been removed now completely. Change-Id: I7726367fd16630aa4b4b25b24b05f740645066db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-07arch/x86: Move prologue to .init sectionKyösti Mälkki
For arch/x86 the realmode part has to be located within the same 64 KiB as the reset vector. Some older intel platforms also require 4 KiB alignment for _start16bit. To enforce the above, and to separate required parts of .text without matching *(.text.*) rules in linker scripts, tag the pre-C environment assembly code with section .init directive. Description of .init section for ELF: This section holds executable instructions that contribute to the process initialization code. When a program starts to run, the system arranges to execute the code in this section before calling the main program entry point (called main for C programs). Change-Id: If32518b1c19d08935727330314904b52a246af3c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47599 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07soc/intel/icelake: Remove unused ENABLE_DISPLAY_OVER_EXT_PCIE_GFXSubrata Banik
Mainboard user can select VGA_ROM_RUN_DEFAULT Kconfig hence no need to have another ENABLE_DISPLAY_OVER_EXT_PCIE_GFX Kconfig to load/execute VGA OpRom. Change-Id: Id87f82d9c3657afad9db94b1ec0917121edfe2bb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49023 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07soc/intel/common/cse: Drop dependency on CHROMEOS for SOC_INTEL_CSE_LITE_SKUMatt DeVillier
The CSE lite SKU has 2 CSE firmware boot partitions vs 3 for the "normal" SKU; this has nothing to do with building for ChromeOS or not, and by having this dependency, boards with select the CSE lite SKU are unable to build with CONFIG_CHROMEOS unset due to Kconfig dependency issues. Test: build google/wyvern with CONFIG_CHROMEOS not set. Change-Id: I6959f35e1285b2fab7ea1f83a5ccfcb065c12397 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-06soc/intel/broadwell: Move MAX_CPUS from mb to SoCFelix Singer
All Broadwell boards use 8 for MAX_CPUS, so this option can be factored out into SoC Kconfig. Change-Id: I311b95ea75a7c6b76b32c7197a0cec86db644234 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49122 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06soc/intel/skylake: Move MAX_CPUS from mb to SoCFelix Singer
Configure MAX_CPUS in SoC Kconfig with 8 as default value and remove it from every mainboard where 8 is used. Change-Id: I825625bf842e8cd22dada9a508a7176e5cc2ea57 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49105 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06soc/intel/alderlake: Update CPU microcode patch base address/sizeSubrata Banik
This patch updates CPU microcode patch base address/size to FSP-S UPD to have second microcode patch loaded successfully to enable Mcheck flow. This is new feature requirement for ADL as per new Mcheck initialization flow. BUG=b:176551651 TEST=Able to reach beyond PC6 without any MCE. Change-Id: I936816e3173dbcdf82b2b16b465f6b4ed5d90335 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48847 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04arch/x86: Pass GNVS as parameter to SMM moduleKyösti Mälkki
Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04soc/intel/baytrail/southcluster.asl: Use consistent comment formattingMatt DeVillier
Change-Id: I479e1eb5819c42621e8b17367b964124d5433378 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-04soc/intel/baytrail: add LPEA resources to southcluster.aslMatt DeVillier
The LPEA device memory resources, required by Windows drivers, were not being set. Allocate required resources using soc/intel/braswell/acpi/southcluster.asl as a reference. This patch alone is not sufficient for working audio under Windows on Baytrail ChromeOS devices, but it is a necessary component. Test: boot Windows 10 on google/swanky, observe LPEA device working properly. Change-Id: I7994d9b2c6e134c01b05cd7c61d309b6ba6e88e5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48745 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04soc/intel/apollolake: Hook up GMA ACPI brightness controlsMatt DeVillier
Add struct i915_gpu_controller_info for boards to supply info needed to generate ACPI backlight control SSDT. Hook into soc/common framework by implementing intel_igd_get_controller_info(). Add Kconfig entries to set the correct register offsets for backlight frequency and duty cycle. Change-Id: Ia62a88b58e7efd90f550000fc5b2cef0cb5fade7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40593 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-03soc/intel: Drop indirect <soc/nvs.h> includeKyösti Mälkki
Change-Id: Ia19018685749efdd543cb09c06df117690ab9d66 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48803 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-03soc/intel: Replace <soc/nvs.h> with <soc/device_nvs.h>Kyösti Mälkki
Change-Id: Ib78e746875e330e47540a6199343be62aa7e92a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48830 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-03sb,soc/intel: Convert some CONFIG(CHROMEOS) preprocessorKyösti Mälkki
Change-Id: I964f4340caa20124a15e52c055d2f27ba5113687 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-01soc/intel/cnl: add panel and backlight configuration codeMichael Niewöhner
Add code for panel and backlight configuration. Tested successfully with libgfxinit on Clevo L141CU. Change-Id: If619b28478b4b0d18f28f318c16336e0de76e129 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-01nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settingsMichael Niewöhner
There are multiple different devicetree setting formats for graphics panel settings present in coreboot. Replace the ones for the platforms that already have (mostly) unified gma/graphics setup code by a unified struct in the gma driver. Hook it up in HSW, BDW, SKL, and APL and adapt the devicetrees accordingly. Always ensure that values don't overflow by applying appropriate masks. The remaining platforms implementing panel settings (GM45, i945, ILK and SNB) can be migrated later after unifying their gma/graphics setup code. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-01soc/intel/bdw,nb/intel/hsw: convert panel delays to ms representationMichael Niewöhner
For easier review of the switch to a new register struct in the follow-up change, the panel delay times get converted from destination register raw format to milliseconds representation in this change. Formula for conversion of power cycle delay: gpu_panel_power_cycle_delay_ms = (gpu_panel_power_cycle_delay - 1) * 100 Formula for all others: gpu_panel_power_X_delay_ms = gpu_panel_power_X_delay / 10 The register names gain a suffix `_ms` and calculation of the destination register raw values gets done in gma code now. Change-Id: Idf8e076dac2b3048a63a0109263a6e7899f07230 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-31soc/intel/skylake: Remove device_nvs.hKyösti Mälkki
Change-Id: I9d500be609d61ccf234260216bd5aae3f78e91a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48802 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-30drivers/intel/gma: Include gfx.asl by default for all platforms...Matt DeVillier
which select INTEL_GMA_ACPI. Rework brightness level includes and platform-level asl files to avoid duplicate device definition for GFX0. Include gfx.asl for Skylake/Kabylake, since all other soc/intel/common platforms already do. Adjust mb/51nb/x210 to prevent device redefinition. Some OSes (e.g. Windows, MacOS) require/prefer the ACPI device for the IGD to exist, even if ACPI brightness controls are not utilized. This change adds a GFX0 ACPI device for all boards whose platforms select INTEL_GMA_ACPI without requiring non-functional brightness controls to be added at the board level. Change-Id: Ie71bd5fc7acd926b7ce7da17fbc108670fd453e0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-30soc/intel/common: Move gfx.asl to drivers/intel/gmaMatt DeVillier
Adjust platform-level includes as needed. Change-Id: I376349ccddb95c166f0836ec1273bb8252c7c155 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-30soc/intel/cnl: add Kconfig values for GMA backlight registersMichael Niewöhner
Add the right register values for backlight control to CNL's Kconfig. To make iasl happy about the reversed register order, split the field. Change-Id: I05a06cc42397c202df9c9a1ebc72fb10da3b10ec Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-30soc/intel: hook up new gpio device in the soc chipsMichael Niewöhner
This change adds the required gpio operations struct to soc/common gpio code and hooks them up in all socs currently using the gpio block code, except DNV-NS, which is handled in a separate change. Also, add the gpio device to existing chipset devicetrees. Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with CB:48711 and OCP DeltaLake with CB:48672. Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6 Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48583 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29soc/intel/bdw,nb/intel/hsw: correct mask for panel power cycle delayMichael Niewöhner
Correct the mask for the power cycle delay from 0xff to 0x1f, to represent the actual maximum value according to Intel graphics PRM for Haswell, Volume 2c and Intel graphics PRM for Broadwell, Volume 2c. Change-Id: Ib187f1ca6474325475e5ae4cc1b2ffbce12f10bf Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48957 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29soc/intel/alderlake: Update chipset.cb for TCSS and USBEric Lai
Follow TGL chipset.cb to add alias for TCSS and USB ports. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/48793 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29soc/intel/skylake: Add 4 missing root ports to chipset dtFelix Singer
The Kaby Lake PCH can have up to 24 PCIe root ports. Thus, add 4 missing root ports to the chipset devicetree. Change-Id: I443fb736873d47f1b6fe7718a10e1bb4ae5df2a6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48947 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-29sec/intel/txt/Kconfig: Make TXT HEAP and SINIT size configurableArthur Heymans
More recent platforms (Cooperlake) need bigger sizes. Change-Id: Ia3e81d051a03b54233eef6ccdc4740c1a709be40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28soc/intel/apl: Fix indentsFelix Singer
Change-Id: Ide10889ad01ec6d31ee83158182876625a68a5da Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48888 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28soc/intel/xeon_sp: Lock PAM and SMRAM registersArthur Heymans
The CedarIsland FSP Integration recommends locking down some things. Change-Id: I72e04b55d69a8da79485e084b39c3bd38504897f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47168 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-28soc/intel/xeon_sp: Lock down IIO DFX Global registersArthur Heymans
This is required for CbNT. Change-Id: I565a95cd2e76cb1c648884be6d1954288f6e4804 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28soc/intel/xeon_sp: Lock down DMI3 PCI registersArthur Heymans
This is required for CBnT. Change-Id: If5637eb8dd7de406b24b92100b68c5fa11c16854 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-28kconfig: remove non-existent sourceJack Rosenthal
src/northbridge/amd/pi/00660F01/Kconfig does not exist. Remove the source statement. Also, no kconfig files under src/soc/intel/common/basecode/. Clean that up. Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I10917b76ff6c2a9d5a97d5c7dfa9e8925cd8c8a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-12-28soc/intel/skylake: Enable CHAP device depending on devicetreeBenjamin Doron
Now that CHAP device is declared in chipset devicetree, hook it up to devicetree configuration. Change-Id: Icc51f7b9cda32d5058dce958e386921b6d3d8ffb Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48323 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-03 21:39:14 +0000