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2020-11-17soc/intel/xeon_sp: Fix SKX SATA drive boot issueMarc Jones
SKX FSP doesn't support X2APIC setup, but CPX does. The CPX DMAR table needs the X2APIC opt out flag set. This fixes the hang loading a kexec'd kernel. The change is easy to see in the coreboot output: [DMA Remapping table] Flags: 0x3 or in the DMAR ACPI table. Change-Id: Iec977c893b70e30875d9a92f24af009c1e90389e Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-17src: Add missing 'include <console/console.h>'Elyes HAOUAS
"printk()" needs <console/console.h>. Change-Id: Iac6b7000bcd8b1335fa3a0ba462a63aed2dc85b8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-16soc/intel/xeon_sp: Synchronize DMAR and MADT IOAPIC id'sArthur Heymans
Add a soc specific callback for getting the IIO IOAPIC enumeration ID. Tested on ocp/deltalake. Change-Id: Id504c2159066e6cddd01d30649921447bef17b12 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47302 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-14soc/intel/xeon_sp: Improve generating PCH IOAPIC MADT entryArthur Heymans
The PCH IOAPIC ID is 0x8 so it needs to be generated before the IIO IOAPICs. Since we will get rid of the ioapic_id array this makes it more readable. Change-Id: I64a3b259e438ef666fb68a433cceda10aebdb1bf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-13soc/intel/xeon_sp/acpi.c Loop over HOB stack for MADT generationArthur Heymans
To align MADT generation with DMAR, we loop over HOB entries instead of over copied HOB entries fetched from get_iio_stacks(). This makes it easier to see what is going on. Tested on ocp/deltalake Change-Id: I8ffe0322bb182b7ec5887354ec801e1f9f3d3288 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-13soc/intel/xeon_sp: move get_iiostack_info() to a common placeArthur Heymans
All this function does is looping over IIO stacks in the FSP HOB. The only 'SOC/FSP specific' thing is the way to detect if the stack is an IIO stack so add a callback to determine this. Change-Id: I4fa9c54d50279213a4174186a23c3cc156e21c9a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-13soc/intel/xeon_sp: Change the return type of get_iio_stack_info()Arthur Heymans
The somewhat unrelated return value makes the function harder to understand and the return type is not consistently used. Use a different helper function to get the HOB Pci64BitResourceAllocation data. Change-Id: I9a03cbb0ebbb48cc052d4c082d359c0087aaeb3e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-13soc/intel/xeon_sp: Tidy up adding MADT ioapic entriesArthur Heymans
Add a helper function to print out debug info and add the MADT entry. Change-Id: I1a00f87c6edef530c5352929ee9279782be4b112 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-11-12soc/intel/xeon_sp: Use a common function to get the IIO HOBArthur Heymans
TESTED ocp/deltalake still boots. Change-Id: I69f336c1ff348b8e820340b84494929f2c58ce72 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47296 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09soc/intel/xeon_sp: Don't add memory resource twiceMarc Jones
The resource function is called for each device VID/DID. Only add the memory resource map from the boot CPU (bus 0) and not for each socket/CPU. This is a NUMA architecture and has a shared memory map. All the resources must match across the sockets/CPUs, so they should only be added to the map once. Change-Id: Ia336f604441ae8d30b8418300da7c34ab9907cae Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-09soc/intel/xeon_sp: Move set_bios_init_completion()Marc Jones
Move set_bios_init_completion() and helper functions from skx and cpx soc_util.c to xeon common util.c. There are some slight differences between skx and cpx, so used the more correct cpx functions. Both cpx and skx platforms boot as expected. Change-Id: Ie416b3a43ccdd14a0eb542786593c2eb4d37450f Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47172 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09soc/intel/xeon_sp: Look up the IIO_HOB only onceArthur Heymans
The HOB does not move, place its location in .bss. Change-Id: I2c6dbe4d64138e45fa1dfe7580ffa70d0441bd88 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47294 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-09soc/intel/xeon_sp/skx: Reorder soc_util.cMarc Jones
Reorder soc_util.c and remove the un-needed #if ENV_RAMSTAGE to match cpx version in preparation for more de-duplication. Change-Id: Iab343e903e2478709fe91739c9ca77f587286df7 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-06soc/intel/xeon_sp/skx: Fix MADT CPU indexesMarc Jones
The CPU index wasn't getting updated. Confirm MADT sets IOAPIC and CPU ID numbers. Change-Id: I72430cc48f4609ac408e723172ba1ed263cca8e3 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-06soc/intel/xeon_sp: Move CPU helper functionsMarc Jones
Continue Xeon-SP de-duplication. Move CPU helper functions from skx/ and cpx soc_util.c to common util.c. Functions only used by util.c are updated to be static. The following functions are moved: int get_threads_per_package(void); int get_platform_thread_count(void); const IIO_UDS *get_iio_uds(void); unsigned int soc_get_num_cpus(void); void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread); void xeonsp_init_cpu_config(void); Change-Id: I118a451b9468459cf2c2194f31da1055e1435ebe Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47170 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-06soc/intel/xeon_sp/cpx: Reorder cpu.c .h includesMarc Jones
Clean up the header includes. Change-Id: I9f61d1a82b37bc0ed803967dc64decf18f44adc9 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2020-11-05soc/intel/xeon_sp: Use common cpu/intel romstage entryArthur Heymans
This removes some boilerplate like starting the console and also adds a "start of romstage" timestamp. Change-Id: Ie85df5d244fa37c41f0b3177ca325c607fa54593 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-04soc/intel/xeon_sp: Add a smm_region functionArthur Heymans
This reports where TSEG is located and will be used when setting up SMM. Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-04soc/intel/xeon_sp: Convert to ASL 2.0 syntaxElyes HAOUAS
Change-Id: I43e36f2e736192603be61519d3e185605e81f0e8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-04soc/intel/xeon_sp: Pass IIO_RESOURCE_INSTANCE as pointerJacob Garber
IIO_RESOURCE_INSTANCE is a large struct, so it should be passed as a constant pointer rather than making a copy. Found-by: Coverity CID 1432759 Change-Id: Iebbb4d292f4d956e767bda28cbf20b0318586510 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46729 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-TArthur Heymans
The CAR set up by FSP-T is at base 0xfe800000 and has a 0x200000 size. FSP-M seems to have a very large stack usage so it would overflow other car symbols located below the coreboot stack such as timestamps and the pre-ram console, which are now fixed. TEST: boot with ocp/deltalake. Change-Id: I886f9391ad79fcfa0724109393e3781a08d954b4 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46895 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03soc/intel/xeon_sp/acpi: Fix uncore dsdt for multiple cpusMarc Jones
Fix the asl to use CONFIG_MAX_CPUS to create entries for multiple cpu uncores. Don't add the RTxx resource entries multiple times. The function is called for each CPUs. Change-Id: Ia4eb9716ae4bd72fb4eb98649105be629623cbef Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47060 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03soc/intel/xeon_sp; Use soc specific stack-port functionMarc Jones
Separate the get_stack_for_port into soc specific functions. This removes a #if in common code. Change-Id: Ib38a7d66947ded9b56193a9163e5128b2523e99c Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-02soc/intel/xeon_sp/bootblock.c: Report the FSP-T outputArthur Heymans
Change-Id: I03841f8263203ee306f83b8f8e859ec03edc3bd3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46885 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/xeon_sp: Call common soc_get_num_cpus()Marc Jones
Use a common function to get the number of CPUs for each soc. This removes a #if for different function names in the common code. Change-Id: I3348d37fcae72247731e465ec2a65d9583a2f180 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-30soc/intel/xeon_xp: Combine cpx and skx acpi.cMarc Jones
Prepare for common ACPI. Combine cpx and skx acpi.c into a single file in xeon_sp. This is almost the last step in using common/block acpi. Change-Id: I5f40eb7909bb796907682c548219c7515f2ae4d1 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46600 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/xeon_sp/skx/acpi.c: Update with cpx changesMarc Jones
Prepare for common ACPI. This primarily makes the skx madt table generation match cpx. There are a few other small changes to remove unused code and make the files match. Change-Id: I71a59181226d79c40a4af405653c50c970fb720b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46599 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/xeon_sp: Move read_msr_ppin() to common util.cMarc Jones
Move CPX and SKX read_msr_ppin() to common util.c file. Update drivers/ocp/smbios #include to match. Change-Id: I4c4281d2d5ce679f5444a502fa88df04de9f2cd8 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-30soc/intel/xeon_sp: Move common chip.c codeMarc Jones
Move common CPX and SKX chip.c code to chip_common.c. Change-Id: I158882ab15659858c2b13b4a3e02a26ef8d4ed3c Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-30soc/intel/xeon_sp/skx: Simplify pci_domain_read_resourceMarc Jones
Use a simpler pci_domain_read_resource for the stacks. This makes it the same as the cpx function, since both get the stack information from the FSP. This will be merged with common xeon cpx/skx in a later patch. Change-Id: I0130ce671fe9ff04e48021a0c5841551210aa827 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46308 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30soc/intel/xeon_sp/skx: Add resource allocator helpersMarc Jones
Add and use resource allocator helper functions from cpx. It also simplifies the allocator by removing IORESOURCE_PCI64 from the resource type check. It isn't needed since it is an attribute of IO and MEM and will be added with the appropriate type. This clean up matches CPX and will help with merging in the future. Change-Id: I5812b07ba00eeafb4d1e826e9cdf9a659b0248bb Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46306 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-29soc/intel/xeon_sp: Move function debug macrosMarc Jones
Move the macros for printing debug information to debug.h in the common console include directory and device include file. These are available if the platform selects DEFAULT_CONSOLE_LOGLEVEL_8. The macros could be used by any platform. Change-Id: Ie237bdf8cdc42c76f38a0c820fdc92e81095f47c Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-29include/device/device.h: Move resource debug macrosMarc Jones
Add general debug macros that print resource information. These are available to select if DEFAULT_CONSOLE_LOGLEVEL_8. The macros are helpful in debugging complex resource allocation with multiple buses. The macros are moved from soc/intel/xeon_sp, where they were originally developed. Change-Id: I2bdab7770ca5ee5901f17a8af3a9a1001b6702e4 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-28src/soc/intel/xeon_sp: Fill in the cache information in SMBIOS type 7Morgan Jang
TEST=Execute "dmidecode -t 7" to check if cache error correction type and cache sram type is correct for each cache level Change-Id: Ibe7c6ad03a83a6a3b2c7dfcfafaa619e690a418d Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28soc/intel/xeon_sp/cpx: Set SLEEP_BUTTON flag in ACPI FADTMorgan Jang
Keep SLEEP_BUTTON flag in ACPI FADT to indicate that no sleep button is present on Cooperlake platform. Change-Id: I2ce435a7bda780b2d2ed00be3f3a8a080c4434ab Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-28mb/ocp/deltalake: Rename motherboard_fill_fadt()Jingle Hsu
Rename motherboard_fill_fadt() to the common override mainboard_fill_fadt() function to override FADT. Tested=On OCP Delta Lake, verify FADT PM Profile is set to Enterprise Server. Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Change-Id: Ie9ea7cc6e712d0aca57bbeac1a4154921d123be4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-26src: Include <arch/io.h> when appropriateElyes HAOUAS
Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26soc/intel/xeon_sp/acpi: Add pch.aslMarc Jones
Add ASL for the PCH. Initially, this only contains soc/intel/common/block/acpi/acpi/lpc.asl. Additional PCH ASL may be added in the future. Change-Id: I70cb790355430f63f25e0dbc9fccc22462fe3572 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45836 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23soc/intel/xeon_sp/skx: Add missing includesAngel Pons
Commit 985d956 (soc/intel/xeon_sp/skx/: Clean up soc_util.c) removed some indirect header inclusions, which resulted in a build failure. Change-Id: I1ef9b416b52a6a1275d699708a805d4ba49baef0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46662 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22soc/intel/xeon_sp: Rename cpx_generate_p_state_entries()Marc Jones
Prepare for common ACPI. Rename cpx_generated_p_state_entries() to the common soc_power_states_generation() function. Add empty soc_power_states_generation() to skx. Change-Id: Ib7e8dfd2bb602f3e6ccdb5b221bc65236f66a875 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-22soc/intel/xeon_sp/skx: Move skx specific FADT settingMarc Jones
Prepare for common ACPI. Move the skx specific FADT settings from acpi.c to soc_acpi.c, soc_fill_fadt. This gets acpi_fill_fadt() to match common/block/acpi.c. Change-Id: I04873d13d822de514acbb58501171285bd5b020e Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-22soc/intel/xeon_sp: Move uncore_inject_dsdt() callMarc Jones
Prepare for common ACPI code. Move uncore_inject_dsdt() to the uncore device acpi_inject_dsdt call. Change-Id: Ida106238690eb1af17759ba6dbe4cb94344e3a94 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-22soc/intel/xeon_sp: Move ACPI prototypes from chip.hMarc Jones
Prepare for common ACPI. Move the soc ACPI function prototypes from cpx and skx chip.h to include/soc/acpi.h. Change-Id: Ib7037cfb58825a2f6c25c122b95f72d5992dc04e Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-10-22src/soc/intel/xeon_sp/skx: Update get_iiostack_info()Marc Jones
Add Pci64BitResourceAllocation return value to get_iiostack_info(). This matches cpx function and is used in future de-duplication. Change-Id: I939c0101c751d9afced4ab33487958b93e59924c Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46307 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22soc/intel/xeon_sp/skx/: Clean up soc_util.cMarc Jones
Remove unused c_util.c helper functions and clean up soc_util.h in preparation for merging common code with cpx/. Change-Id: Iff825f64b665aadcf8eac8a404191c0b74f92abd Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46094 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-22soc/intel/xeon_sp: Move common northbridge ACPI to nb_acpi.cMarc Jones
De-duplicate and prepare for common ACPI. Move common northbridge ACPI code to nb_acpi.c. There are a few differences between the skx and cpx defined FSP hob names and CSTACKS that are managed with #if (CONFIG(SOC_INTEL_*_SP)). Change-Id: I47ab1df3474d18643ef5ffc8199e09ea3dd32ccf Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-22soc/intel/xeon_sp/cpx: Add soc_acpi_fill_fadt()Marc Jones
Prepare for common ACPI code. Make acpi_fill_fadt() match intel/commom/block/acpi/acpi.c function. Use soc_acpi_fill_fadt() to set cpx fadt->flags. Change-Id: I9c04dd478aa5e0f1467e63d06da094128edd9650 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45845 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21soc/intel,mb/*: get rid of legacy pad macrosMichael Niewöhner
Get rid of legacy pad macros by replacing them with their newer equivalents. TEST: TIMELESS-built board images match Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19soc/intel/xeon_sp/cpx: Implement platform_fsp_silicon_init_params_cbMarc Jones
platform_fsp_silicon_init_params_cb is called by the fsp driver and calls mainboard_silicon_init_params which sets the mainboard PCH GPIOs. Change-Id: Icf401e76741a6a7484295e999ddd566fe9510898 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46309 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Bryant Ou <bryant.ou.q@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-15soc/intel/xeon_sp: Add get_system_memory_map()Marc Jones
Prepare for common ACPI. Add get_system_memory_map() helper function to soc_util.c and use it in the SRAT ACPI code to match the cpx code. Change-Id: I54675b52aaf2999d884b3c20ccb143fbbf8b138a Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45847 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-09soc/intel/xeon_sp: Use generic config_tMarc Jones
Don't use the silicon-specific struct type to get common config options. Instead, use the generic config_t typedef. This allows the function to be moved to common code in upcoming patches. Change-Id: If80b678037b4d79387e0a0f722c540df4aae2416 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46057 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-09soc/intel/xeon_sp: Set CPU_ADDR_BITS to 46 for SKX and CPXChristian Walter
According to document number 338846 and 336062 this should be set to 46 bits. Change-Id: I0bbe6c962ffc7d5dc722f1cacf55bc0d0615db59 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-10-09soc/intel/xeon_sp/cpx: skip DRHD generation for non-PCIe stackJonathan Zhang
Without skipping of DRHD generation for non-PCIe stack, the OS kernel detects incorrect DMAR table with following messages: [ 0.561817] Your BIOS is broken; DMAR reported at address 0 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I098605daf12a264f390613581427ec722afcddaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/45887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-08soc/intel/xeon_sp/cpx: Add locking of IA32_FEATURE_CONTROL and VMXChristian Walter
Change-Id: Ib329648f77acecccb0ced1806f61be252d03f2f4 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45869 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-08soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17Johnny Lin
For now only implement for one socket and some of the fields are hard-coded for DDR4 including memory device type, data width and ECC support. Change-Id: I3cb72d18027d972140828970206834ff55b72022 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-08soc/intel/xeon_sp/cpx: correct GSI bases for IO APICsJonathan Zhang
With CPX-SP FSP, PCH IOAPIC handles the first 120(0x78) GSIs. Correct the coreboot assignment of GSIs for IO APICs. Without this patch, there are following target OS boot messages: [    1.098771] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119 [    1.099159] GSI range [24-31] for new IOAPIC conflicts with GSI[0-119] After this patch, the boot messages are: [ 0.399498] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119 [ 0.399848] IOAPIC[1]: apic_id 9, version 32, address 0xfec01000, GSI 120-127 Also without this patch, there is boot stability issue. About one in 20 reboots, the target OS fails to boot with following failure: [ 4.325795] mce: [Hardware Error]: Machine check events logged [ 4.326597] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a [ 4.327594] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086 [ 4.328596] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 1601443875 SOCKET 0 APIC 0 microcode 700001d The MCE error happens in bank 9. The Model specific error code shows it is about SAD_ERR_WB_TO_MMIO error (doc 604926), which means something goes wrong when cache write back to mmio. It is a generic transaction type error in level 2. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I45e941591300dad6d583a6dcb41f45e984753c07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45941 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-06soc/intel/xeon_sp/skx: Move get_srat_memory_entries()Marc Jones
Prepare for common ACPI code. Move get_srat_memory_entries() from soc_util.c to soc_acpi.c where the other srat ACPI functions are located. Change-Id: If26641497e1c16d5cf493490711aa08d6e1cb640 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45846 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-06soc/intel/xeon_sp/cpx: Don't use SCI defineMarc Jones
Continue preparations for common ACPI code. Add code from skx and common/acpi to check the SCI register instead of using a define. Change-Id: I6b638d28775320894a6ab24ef486e67c181591eb Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45844 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-06soc/intel/xeon_sp/skx: Move soc specific ACPI functionsMarc Jones
Prepare for common ACPI code. Move skx soc ACPI functions to a separate file. Change-Id: I12526c17a0dcbc45494ae19c8abaf8bf9a1eab47 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/xeon_sp/cpx: Move soc specific ACPI functionsMarc Jones
Prepare for common ACPI code. Move cpx soc ACPI functions to a separate file, soc_acpi.c Change-Id: I4aaca660e2f94d856676681417ae6c5d8c28a1f1 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/xeon_sp/skx/: Reorder acpi.c functionsMarc Jones
Reorder the functions to make it easier to compare with soc/intel/common/block/acpi/acpi.c and cpx/acpi.c. Move the xeon_sp specific functions to the top. Change-Id: I7bc147781261c2fc39374f5bfe3ba79047b4993a Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/xeon_sp/cpx/: Reorder acpi.c functionsMarc Jones
Reorder the functions to make it easier to compare with soc/intel/common/block/acpi/acpi.c. Move the xeon_sp specific functions to the top. Change-Id: I9034eb774a14ee1e2f9b16c7bd7673ebad69c113 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/xeon_sp/acpi: Break out the ACPI PCH IRQ ASLMarc Jones
Continue separating the CPU from the PCH. Move the PCH IRQ ASL from the uncore_irq.asl to a new file, pch_irq.asl. Change-Id: Iaf8ae87ecc9f8365cc093516f15d9c5a31c7d1d5 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/xeon_sp/acpi: Move ACPI macros to a header fileMarc Jones
Move ACPI macros to a header file to be used in multiple ASL files. This could be moved to intel/common in the future to reduce the amount of duplicate ASL code. Tested by checking build/dsdt.asl doesn't change. Change-Id: Id2441763fe335154048c9a584a227a18e8c5391c Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06soc/intel/xeon_sp/acpi: Remove ASL Package() NumElementsMarc Jones
Remove the NumElements and allow the ASL compiler to fill them in. This is safer than hard coding the NumElements. For Package (NumElements) {PackageList}, "If NumElements is absent, it is automatically set by the ASL compiler to match the number of elements in the PackageList" ACPI v6.2 sec 19.6.101. Change-Id: I73df9e31011ad0861d4755fdbcbbd93e4e0b5a51 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel/xeon_sp/acpi: Rename pci_irq.aslMarc Jones
Rename pci_irq.asl to pci_irqs.asl to match other intel soc file names. This makes comparing differences much easier. Change-Id: I622dfef675c3df2dff7a3024ccbe14c356a5cd86 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45834 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp: Clean up pci_devs.hMarc Jones
Prepare for merging cpx and skx pci_devs.h. Remove duplicate defines. Move defines so they match each other. Checked TiogaPass and DeltaLake BUILD_TIMELESS. Change-Id: I146dd9e3f7eba053977d48dcf34d927dea310059 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45833 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel: Move pch_enable_ioapic() to common codeSubrata Banik
List of changes: 1. Move pch_enable_ioapic() into common block code. 2. Remove redundant LPC functions from SoC directory and refer from block/lpc directory. TEST=Able to build and boot hatch and tglrvp platform without seeing any functional impact. Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03soc/intel/xeon_sp/include: De-duplicate .h filesMarc Jones
Move duplicate .h files to top level xeon_sp/include/soc from silicon specific cpx/include/soc and skx/include/soc. Change-Id: I11d8a95a4b2f9451615b236798b3bd030c724858 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45221 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp/skx: Prepare acpi.* for mergingMarc Jones
Clean up acpi.h in preparation for merging with cpx/ acpi.* files Change-Id: I2a0dc964eeb7f8da53676eb94c4385ff8668f6af Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45218 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp: Use common ASL code for xeon_spMarc Jones
Move and use the common xeon_sp/cpx/acpi asl for skx/. There were only minor whitespace differences between the directories. Update the mainboards to build the moved files. TiogaPass coreboot.rom checked with BUILD_TIMELESS. Change-Id: I5058a3fe8d96075a266fb92f10707bb94308c85b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45217 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp/skx: Fix uncore.asl \_SB namespace issueMarc Jones
The skx uncore ACPI scope was missing the \ on \_SB causing the uncore IRQs to not be in the namespace. This addresses ACPI uncore IRQ routing issues. This was found preparing skx acpi to match cpx acpi for merging in the future. Check scope in dsdt.asl in tiogapass build. Change-Id: I799042babbe60287e5e4ec60b21c08d57ccda04b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45269 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp/skx: Update ITSS OperationRegion to ACPI2.0 notationMarc Jones
Prepare for merge with cpx. Use the C style operators instead of the ACPI1.x polish notation. This is much easier to read and matches the cpx code. This generates the same ASL code. Checked with BUILD_TIMELESS on TiogaPass. Change-Id: Id44138894d2ffed4c93afe5d4bbb4d59b538b577 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45270 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03soc/intel/xeon_sp/skx: Update uncore IRQ routing ACPI tablesMarc Jones
Update the skx uncore ACPI routing tables to match cpx. This adds the IRQ routing for B-D for legacy and IOAPIC modes. Change-Id: Iac0ffdb467a78b9befe7402c074835ea602d43c8 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-02drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES configShelley Chen
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability. BUG=b:150502246 BRANCH=None TEST=diff the coreboot.rom files resulting from running ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless with and without this change to make sure that there was no difference. Also did this for GOOGLE_CANDY board, which is baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES enabled). Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-09-28Revert "soc/intel/xeon_sp: Improve performance efficiencies"Subrata Banik
This reverts commit d51449d017410fedb55e93f71fb322749ba888b5. Reason for revert: Causing compilation issue as below src/soc/intel/xeon_sp/cpx/acpi.c: In function 'acpi_create_rhsa': src/soc/intel/xeon_sp/cpx/acpi.c:825:4: error: initialization discards 'const' qualifier from pointer target type [-Werror=discarded-qualifiers] &hob->PlatformData.IIO_resource[socket]; ^ Change-Id: I7050060f1db7b9a9b5a77b5a6245c8fda05623a4 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44998 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28soc/intel/xeon_sp/cpx: add ACPI name for CSTACKJonathan Zhang
Add ACPI name for CSTACK. The name is PC00 to match with ACPI table generated. The PCIe domain has multiple PCIe stacks. devicetree.cb at the moment does not support multiple PCIe stacks, eg. IIO stacks. For now, assign the name to PCIe domain. In future, the name needs to be assigned to CSTACK. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I24a6f29734452426218419cdcf66702edde96f46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-09-28soc/intel/xeon_sp: Improve performance efficienciesJohn Zhao
Coverity detects performance inefficiencies as IIO_RESOUCE_INSTANCE structure (size 623 bytes) is PASS_BY_VALUE. Fix it with PASS_BY_REFERENCE. Found-by: Coverity CID 1432759 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I9ae9ae38fe2c13c5433aa5e1dcbb30ebd30622ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/45608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-26arch/x86: Introduce `ARCH_ALL_STAGES_X86_32`Angel Pons
Nearly every x86 platform uses the same arch for all stages. The only exception is Picasso. So, factor out redundant symbols from the rest. Alder Lake is not yet complete, so it has been skipped for now. Change-Id: I7cff9efbc44546807d9af089292c69fb0acc7bad Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-21src/soc/intel: Drop unneeded empty linesElyes HAOUAS
Change-Id: Id93aab5630e928ee4d7e957801e15a4cc8739fae Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44594 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21soc/intel/xeon_sp: Enable PMC supportRocky Phagura
PMC support was not enabled on Xeon_sp platforms. This involves turning on SOC_INTEL_COMMON_BLOCK_PMC and then adding the proper hooks in SOC specific code. This patch leverages code from the Skylake project and adds the bare minimum hooks to leverage PMC common code. Most importantly this enables power management registers located in the PMC device (under ACPI_BASE_ADDRESS). Access to this device is also needed for SMM setup and handling. TEST=build for Tiogapass and enable the following Kconfig options: select SOC_INTEL_COMMON_BLOCK_PMC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select CPU_INTEL_COMMON_SMM Boot the system and ensure pmbase is programmed. (Look for pmbase in debug messages). Secondly check that SMIs are enabled by looking at the debug messages (search for "Enabling SMIs") and verifying in HW by reading IO port 0x530. Change-Id: I6d57a8282a8b6dc4314f156c39deb09535575cbd Signed-off-by: Rocky Phagura <rphagura@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-09-21soc/intel/xeon_sp/cpx: search IIO_UDS HOB once when creating DMAR tableJonathan Zhang
IIO_UDS HOB was searched several times during the creation of DMAR table. Reduce it to only once to improve boot time. Both DRHD and ATSR subtable creations involve addition of PCIe bridge device entries, combine the functions with acpi_create_dmar_ds_pci_br_for_port(). When looping through ports to create PCIe bridge device entries, use MAX_PORTS intead of NUMBER_PORTS_PER_SOCKET to improve boot time. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I469cd8473c50e105daeda6c5607592ae7cef6032 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-09-21soc/intel/xeon_sp/cpx: remove DMAR_X2APIC_OPT_OUT flagJonathan Zhang
CPX-SP processor supports X2APIC. Remove DMAR_X2APIC_OPT_OUT flag from DMAR table. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I63c9feda74c7abb591eac991cb98cdcad8afc158 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45375 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16xeon_sp/skx: Reorder pci_devs.hMarc Jones
Reorder to be similar to cpx/include/soc/pci_devs.h. We may be able to merge the files in the future. Checked TiogaPass with BUILD_TIMELESS=1 Change-Id: I939707cc9e58e23f053156f40df4c21a6072570b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45220 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-16xeon_sp/cpx/pci_devs.h: Remove duplicate definesMarc Jones
Change-Id: I8fc4e07269175eb2f40655b828e340697a9a892a Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45219 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14soc/intel/xeon_sp/cpx: display FSP_PREV_BOOT_ERR_SRC_HOBJonathan Zhang
Before MRC code execution, FSP interrogates EMCA MSR registers and other registers to see if there are fatal errors happened during previous boot session. If there are, error records are saved into FSP_PREV_BOOT_ERR_SRC_HOB. When the value of Length field of FSP_PREV_BOOT_ERR_SRC_HOB is 2, that means the HOB does not contain any valid error record. TESTED=Injects MCE error through cscript, reboot into OS, check boot log: 0x75904d70, 0x00000400 bytes: HOB_TYPE_GUID_EXTENSION 5138b5c5-9369-48ec-5b9738a2f7096675: FSP_PREV_BOOT_ERR_SRC_HOB_GUID ================ PREV_BOOT_ERR_SRC HOB DATA ================ hob: 0x75904d88, Length: 0x42 MCBANK ERR INFO: Segment: 0, Socket: 0, ApicId: 0x0 McBankNum: 0x3 McBankStatus: 0xfe00000000800400 McBankAddr: 0xf0ff McBankMisc: 0xfffffff0 MCBANK ERR INFO: Segment: 0, Socket: 0, ApicId: 0x0 McBankNum: 0x4 McBankStatus: 0xfe00000000800400 McBankAddr: 0xfff0 McBankMisc: 0xfffffff0 0x75904d88: 42 00 01 00 00 00 00 00 03 00 00 04 80 00 00 00 B............... 0x75904d98: 00 fe ff f0 00 00 00 00 00 00 f0 ff ff ff 00 00 ................ 0x75904da8: 00 00 01 00 00 00 00 00 04 00 00 04 80 00 00 00 ................ 0x75904db8: 00 fe f0 ff 00 00 00 00 00 00 f0 ff ff ff 00 00 ................ 0x75904dc8: 00 00 Change-Id: Idbace4c2500440b3c1cf2628dd921ca1a989ae81 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44974 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09soc/intel/xeon_sp: Select CPU_INTEL_COMMONAngel Pons
This is an intermediate step to have SOC_INTEL_COMMON_BLOCK_CPU select CPU_INTEL_COMMON directly, to avoid dependency problems. Tested with BUILD_TIMELESS=1: Without including the config file in the coreboot.rom, both OCP Tioga Pass and Delta Lake remain identical. Change-Id: I565e75869be730e7c2fe7114b829941bc9890e6c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45041 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02soc/intel/xeon_sp/Kconfig: Drop redundant 'select POSTCAR_CONSOLE'Elyes HAOUAS
POSTCAR_CONSOLE is already set to yes in console/Kconfig file. Change-Id: If520c33f5e36d569511b2441bf23aa90180591c7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44929 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-08-28vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt socJonathan Zhang
Intel CPX-SP FSP ww34 release added some features: a. change DDR frequency limit. b. define MRC debug message verbosity level. c. enable/disablee of PCH DCI. In addition, there are some changes to HOB data structures. Update UPD and HOB header files and adapt soc accordingly. TESTED=booted on YV3 DVT to target OS command line. Also rebooted okay. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iadbf5dc850c445f988bc7f07a24165abed2298c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44685 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-20soc/intel/xeon_sp/cpx/Kconfig: Relocate 'select CACHE_MRC_SETTINGS'Elyes HAOUAS
This will remove the warning: "src/soc/intel/xeon_sp/cpx/Kconfig:79:warning: config symbol 'CPU_BCLK_MHZ' uses select, but is not boolean or tristate" Change-Id: I2cfaf347b638e3847caa167e7efda89e9202960a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-08-18xeon_sp/cpx: Fix get_system_memory_map to return the correct addressJohnny Lin
Similar to commit b45ed65, the HOB structure is actually a 8 byte address pointing to the HOB data. Tested=Verified the values of the hob fields are the same printed by soc_display_memmap_hob(). Change-Id: I348d3cd80a56e86d22f20fcadf0316b462b86829 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-18xeon_sp/cpx: Enable ACPI P-state supportJingle Hsu
Implement ACPI P-state support to enable driver acpi_cpufreq. This patch leverages code from the Skylake project. Tested=On OCP Delta Lake cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies 1501000 1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 Change-Id: I3bf3ad7f82fbf196a2134a8138b10176fc8be2cc Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-14soc/intel/xeon_sp/cpx: add VT-d supportJonathan Zhang
Intel CPX-SP FSP added support for VT-d through adding UPD parameter X2apic. Based on devicetree.cb setting, enable VT-d programming through FSP-M. When VT-d is enabled, add DMAR ACPI table. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ic66374af6e53fb847c1bdc324eb3f4e01c334a94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-08-14soc/intel/xeon_sp/cpx: remove unsupported configsJonathan Zhang
coherency_support and ats_support are not supported by CPX-SP FSP. Remove them from soc_intel_xeon_sp_cpx_config struct. Remove corresponding settings from DeltaLake devicetree.cb. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ibe1c4e88817fc4be7915e95fa829f0a4c0d947f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-08-13soc/intel/xeon_sp/cpx: add CPUID for CPX-SP A1 processorJonathan Zhang
Add CPUID for CPX-SP A1 (also called QS) processor. DeltaLake DVT server uses CPX-SP A1 processor. TESTED=booted DeltaLake DVT server to target OS. [root@localhost ~]# dmidecode -t 1 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0001, DMI type 1, 27 bytes System Information Manufacturer: Wiwynn Product Name: Delta Lake DVT Version: YoDL03 Serial Number: BZA02200122N01A UUID: 000A0A22-2C29-1ED6-8259-000055DA2BFF Wake-up Type: Reserved SKU Number: Not Specified Family: DeltaLake Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ic8975f6bf752fd685b38b2d1f0a4da41983b57f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-08-11xeon_sp/cpx: Enable PCH thermal device via FSPJohnny Lin
Tested=On OCP Delta Lake, OpenBMC sensor-util can see PCH Temp readings. Change-Id: I39d0d0a982476f9fece51cfa19dcbd0da5dea690 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44075 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-08vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww32 release and adapt socJonathan Zhang
Intel CPX-SP ww32 release has a number of bug fixes: a. It fixed the issue related to some PCIe ports being hidden. This affected DeltaLake config A, made the onboard PCIe NIC device not working. ww32 release added two UPD parameters: PEXPHIDE, HidePEXPMenu. b. It fixed the regression related to MRC cache. c. It fixed the issue related to VT-d support, and added X2apic UPD paramter. A separate PR will be submitted to enable VT-d in coreboot. d. It fixed the issue related to enabling thermal device with PCI or ACPI mode. [CB:44075] was submitted to enable it in coreboot. e. It fixed the issue of FSP log level change UPD parameter DebugPrintLevel not working. There is a change in IIO UDS Hob. TESTED=booted YV3 config A, and rebooted it. Access the target OS remotely. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-07xeon_sp/cpx: Enable HWP Intel Speed ShiftJohnny Lin
Set HWP base feature, enable EPP, lock thermal interrupt and lock MSR Tested=On OCP Delta Lake, rdmsr 0x1aa shows 403040 Change-Id: I6d23de4032562095db1aaf96ddfd2b70a4517faa Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44171 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-03soc/intel/xeon_sp/cpx: configure STACK_SIZEJonathan Zhang
Before this change, we have this problem (boot log from DeltaLake config A server): Jumping to boot code at 0x00040000(0x755f6000) Stack overrun on CPU0 (address 0x7574a000 overwritten). Increase stack from current 4096 bytes ERROR: BUG ENCOUNTERED at file 'src/lib/stack.c', line 43 Linux version 4.16.18 Configure STACK_SIZE to make it larger to fix above problem. Now, we have this boot log: BS: BS_PAYLOAD_LOAD exit times (exec / console): 326 / 21727 ms Jumping to boot code at 0x00040000(0x752f2000) CPU0: stack: 0x75746000 - 0x7574a000, lowest used address 0x7574681c, stack used: 14308 bytes Linux version 4.16.18 TESTED=booted YV3 config A to target OS. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ia04a3ee0cd37177ecab65469855a1cf920742458 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-03soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2Jonathan Zhang
CPX-SP FSP is FSP 2.2, so select PLATFORM_USES_FSP2_2. SKX-SP continues to select PLATFORM_USES_FSP2_0, as SKX-SP FSP is FSP 2.0. Correct DCACHE_RAM_BASE. Increase FSP_TEMP_RAM_SIZE, DCACHE_BSP_STACK_SIZE, and adjust DCACHE_RAM_SIZE accordingly. Thus the workaround of hardcoding StackBase and StackSize FSP-M UPD parameters is removed. Add CPX-SP soc implementation of soc_fsp_multi_phase_init_is_enable() to indicate that FSP-S multi phase init is not enabled, since it is not supported by CPX-SP FSP. TESTED=booted YV3 config A to target OS. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I25e39083df1ebfe78871561b0a0e230b66524ea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44049 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-02 21:55:30 +0000