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2023-07-13soc/intel: Rename pcr.asl to pch_pcr.aslSubrata Banik
The PCR (Private Configuration Register) is applicable to access the P2SB register space starting with the Intel SkyLake generation of SoC. Prior to Intel Meteor Lake SoC generation, the only P2SB existed inside the PCH die. Starting with Meteor Lake SoC, there are two P2SB, one in SoC die (same as PCH die for U/H SoC) and another in IOE die. This patch renames pcr.asl to pch_pcr.asl to reflect the actual source of the P2SB IP in the die (i.e., SoC die or PCH die). BUG=b:290856936 TEST=Able to build and boot google/rex. Change-Id: Idb66293eaab01e1d4bcd4e9482157575fb0adf04 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76407 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-11soc/intel/xeon_sp: Clear reserved field in SRATNaresh Solanki
During the ACPI dump of the System Resource Affinity Table (SRAT), it was noticed that the reserved field within the Memory Affinity structure contained a non-zero value. This commit addresses the issue by performing a memset to zero on the reserved field, ensuring the avoidance of any potential problems arising from garbage values. TEST= Build for ibm/sbp1 & make sure SRAT Memory Affinity entries reserved fields read zeroes Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: I4ba697a6bd59054e74c84b98f3d9b517d333a5d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75417 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2023-07-07soc/intel/xeon_sp/spr: Fix upd_display.c build errorJohnny Lin
Fix below build error after DISPLAY_UPD_DATA is selected: src/soc/intel/xeon_sp/spr/upd_display.c:131:29: error: variable 'old' set but not used [-Werror=unused-but-set-variable] 131 | const FSP_S_CONFIG *old; | ^~~ src/soc/intel/xeon_sp/spr/upd_display.c:130:29: error: variable 'new' set but not used [-Werror=unused-but-set-variable] 130 | const FSP_S_CONFIG *new; Change-Id: I43ed5fadab58e0d4dc824457c7a1bdf48511198e Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76342 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious
The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \ src/commonlib/include/commonlib/console/post_codes.h; myArray=`grep -e "^#define POSTCODE_" \ src/commonlib/include/commonlib/console/post_codes.h | \ grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`; for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; grep -r "POST_$splitstr" util/cbfstool | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; done Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-15soc/intel: Add max memory speed into dimm infoEric Lai
Add MaximumMemoryClockSpeed if FSP have it, otherwise pass 0. TEST=check dmidecode dump the max speed. Handle 0x000C, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 16 GB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR5 Type Detail: Unknown Synchronous Speed: 5600 MT/s Manufacturer: Micron Serial Number: 3f064d84 Asset Tag: Channel-0-DIMM-0-AssetTag Part Number: MTC8C1084S1SC56BG1 Rank: 1 Configured Memory Speed: 5200 MT/s Minimum Voltage: 1.1 V Maximum Voltage: 1.1 V Configured Voltage: 1.1 V Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75810 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15soc/intel/*/include/soc/pmc.h: Add missing periodic SMI rate bitsMichał Żygowski
Based on: - Apollo Lake datasheet Vol. 3 Revision 005: https://cdrdv2.intel.com/v1/dl/getContent/334819 - 7th Generation Intel Processor Families I/O for U/Y Platforms Datasheet Vol.2 August 2017: https://cdrdv2.intel.com/v1/dl/getContent/334659 - edk2-platforms source for Whitley and Purley platforms (Xeon SP) Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ic600d39d49135808dd1f571c9eff3cdb98682796 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-06-14soc/intel/xeon_sp: Fix HEST table lengthJeff Li
"current" points to the start of HEST table, so "next - current" already includes the size of its header, no need for increment here. This issue was found on SPR-SP platform. The length of HEST table is now correct with this patch. Change-Id: I6ff1e8e24612b7356772d582ff9a7e53863419db Signed-off-by: Jeff Li <lijinfeng01@inspur.com> Signed-off-by: Ziang Wang <ziang.wang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75738 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-06soc/intel/xeon_sp/spr: Add RMT configNaresh Solanki
This commit adds a configuration option to enable RMT in the coreboot build for the Intel Xeon SP SPR platform. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: I9b9276116c22cfbbec132d7a1b0026a52a51398a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-28soc/intel/xeon_sp: Enable build for IO MarginingNaresh Solanki
This commit enables the build for IO Margining, ensuring that ASPM is disabled and certain FSP knobs are adjusted in coreboot as below 1. Enable DFXEnable 2. Disable PcieGlobalAspm 3. Disable KtiLinkL1En & KtiLinkL0pEn Since the FSP UPD does not provide all the necessary knobs for IO Margining, the following settings need to be applied during the FSP build process: 1. Enable PcdBiosDfxKnobEnabled 2. Disable PchDmiAspm 3. Enable SataTestMode 4. Enable WmphyMargining 5. Disable IioErrorEn TEST=Build for IBM sbp1 board. Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Change-Id: Ie306d12943adb76411d55358548b5cb2eb3a95be Reviewed-on: https://review.coreboot.org/c/coreboot/+/75415 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-23soc/intel/xeon_sp: move and rename set_cmos_mrc_cold_boot_flagJohnny Lin
1. Rename set_cmos_mrc_cold_boot_flag() to soc_set_mrc_cold_boot_flag in case a certain platform may not support this via CMOS data, and the function could in turn calls mainboard defined method in the future. Move the code into soc_util.c. 2. Remove redundant static get_system_memory_map() from cpx/romstage.c and call the soc_util.c one. Change-Id: Ib7d9bed9092814658f4a0b1d6dcf3c7d79178048 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-17console: Add format-checking __printf() to die()Nico Huber
Code changes are necessary because `-Wformat` warns about empty format strings by default. Change-Id: Ic8021b70f4cd4875b06f196f88b84940c9a79fe0 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75147 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-17soc/intel/xeon_sp/spr: Fix format specifier for __LINE__ (%d)Nico Huber
Change-Id: I1384a02fa2931002ddd629acef0a4368435cfeb5 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-16soc/intel/xeon_sp: Drop dummy FADT entryKyösti Mälkki
Specifying types without addresses for PM1B events is not useful. Change-Id: I839208eaecf689a32484b9154647fc66633e5eef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-13acpi/Kconfig: move \_SB scope out of ACPI_CPU_STRINGFelix Held
In ACPI 1.0 the processor objects were inside the \_PR scope, but since ACPI 2.0 the \_SB scope can be used for that. Outside of coreboot some firmwares still used the \_PR scope for a while for legacy ACPI 1.0 OS compatibility, but apart from that the \_PR scope is deprecated. coreboot already uses the \_SB scope for the processor devices everywhere, so move the \_SB scope out of the ACPI_CPU_STRING to the format string inside the 3 snprintf statements that use the ACPI_CPU_STRING. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I76f18594a3a623b437a163c270547d3e9618c31a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-10sb,soc/amd,intel: Sync FADT entries visuallyKyösti Mälkki
Change-Id: I20a66dce1612ab4394c26f9b0943dac14bcdcfc4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-09sb,soc/amd,intel: Apply minor FADT fixesKyösti Mälkki
Change-Id: I27a610255e5680be1b507d45c6695cf9419ee052 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-09soc/intel/xeon_sp/spr: Drop spurious FADT fieldsKyösti Mälkki
Assigning duty_offset while duty_width==0 has no purpose. Under intel/common/block, previous assignment for fadt->gpe0_blk resolves GPE0_STS(0) from xeon_sp/ebg/.../soc_pm.h and also assigns value matching pmbase + 0x60. Change-Id: Iaf688d9471ac527ac20307cf16216abdab731a06 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74827 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-05soc/intel/spr: Fix copy paste issue in error messagesFelix Singer
The commit a0b199c6b483 ("soc/intel/xeon_sp/spr: Add soc set_cmos_mrc_cold_boot_flag") introduced a copy-paste issue in two error messages. The error messages should mention the Intel platform SPR instead of CPX. Fix that. Change-Id: I4de61ec2cf9fbd98263a7a7a588938d548148656 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74956 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-29ACPI: Make FADT entries for RTC/CMOS architecturalKyösti Mälkki
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY that points to same offset. Since the century field inside RTC falls within the NVRAM space, and could interfere with OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY. There were no reference for the use of offset 0x48 for century. Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-21ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fieldsKyösti Mälkki
After the obsoletion of Processor() it is necessary to provide _CST package to define P_LVLx IO addresses for C2/C3 transitions. The latency values from _CST will always replace those in FADT. Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-14soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_configLean Sheng Tan
This fixes the Jenkins build error when building INTEL_ARCHERCITY_CRB that was caused by the API change in commit 36e6f9bc047f86e1628c8c41d3ac16d80fb344de. This patch removes the broken API function and also adds package_id log print same as previous commit mentioned above. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74436 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-04-14soc/intel/xeon_sp: Don't sort struct device cpus for numaArthur Heymans
Currently the xeon_sp code reassigns struct devices apic_id so that srat entries can be added in a certain order. This is not a good idea as it breaks thread local storage which contains a pointer to its struct device cpu. This moves the sorting of the lapic_ids to the srat table generation and adds the numa node id in each core init entry. Now it is done in parallel too as a bonus. Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68912 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13soc/intel/xeon_sp: Fix very small total memory when CXL is enabledJohnny Lin
Processor attached memory should not use reserved_ram_from_to and treat the calculation of gi_mem_size size as 64MB. By default SOC_INTEL_HAS_CXL is enabled for Sapphire Rapids platforms, this should fix small total memory issue. Before the fix running command 'free -g -h' under Linux shows the total memory is only 1.4Gi, after the fix it's showing the expected total memory size 15Gi. Tested=On AC without attaching CXL memory, the total memory size is the same as de-selecting SOC_INTEL_HAS_CXL. On OCP Crater Lake with CXL memory attached, CXL memory can be recognized in NUMA node 1: numactl -H available: 2 nodes (0-1) node 0 cpus: 0 1 2 3 4 5 6 .. 59 node 0 size: 95854 MB node 0 free: 93860 MB node 1 cpus: node 1 size: 63488 MB node 1 free: 63488 MB node distances: node 0 1 0: 10 14 1: 14 10 Change-Id: I38e9d138fd284620ac616a65f444e943f1774869 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74296 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-12soc/intel/xeon_sp: Drop Kconfig MAX_SOCKET_UPDPatrick Rudolph
The Kconfig is only used in common code to gather the build time maximum socket number FSP support. The same information is available in FSP header as MAX_SOCKET, thus use the FSP as truth of source. Currently MAX_SOCKET is 4. Change-Id: I10282c79dbf5d612c37b7e45b900af105bb83c36 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74339 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-11ACPI: Add helper for MADT LAPICsKyösti Mälkki
This avoids some code duplication related to X2APIC mode. Change-Id: I592c69e0f52687924fe41189b082c86913999136 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-04-11soc/intel/xeon_sp/acpi: Fix _OSC methodPatrick Rudolph
Fix a couple of bugs in the _OSC method for handling "PCI Host Bridge Device" on Xeon-SP. - Drop the Sleep. The code doesn't write to hardware at all, so there's no need to sleep here. - Make sure that the number of DWORD passed in Arg2 is at least 3. The existing check was useless as it would not create the DWordField, but then use it anyways. - Add check for CXL 2 device method calls which provide a 5 DWORD long buffer to prevent buffer overflows when invoking the "PCI Host Bridge Device" method. Test: Boot on Archer City and confirm that no ACPI errors are reported for _OSC. Change-Id: Ide598e386c30ced24e4f96c37f2b4a609ac33441 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-04-06soc/intel/xeon_sp/spr: Drop devicetree setting X2apicPatrick Rudolph
Drop devicetree setting X2apic as the same functionality is already exposed in Kconfig. To activate X2apic select X2APIC_ONLY or X2APIC_RUNTIME in the "APIC operation mode". Note: Your OS must have support for X2APIC. If you are using less than 256 CPU cores select XAPIC_ONLY here. Test: - Booted to OS in X2APIC mode when X2APIC_ONLY or X2APIC_RUNTIME was selected. - Booted to OS in XAPIC mode when XAPIC_ONLY was selected. Change-Id: I65152b0696a45b62a5629fd95801187354c7a93b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-06soc/intel/xeon_sp/spr: Default to X2APIC supportPatrick Rudolph
When more than 255 CPU cores are present on a board the X2APIC must be used. Select DEFAULT_X2APIC_RUNTIME to support X2APIC by default when a mainboard enables it in the devicetree. Change-Id: I3e84cfbd2a7f05b142dc4d782764edce81646c8a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74184 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-04-05soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systemsPatrick Rudolph
Inject ACPI code for all generated ASL templates. This fixes ACPI errors shown in linux when not all sockets are currently plugged in or some have been disabled. Test: Boot Archer City with CONFIG_MAX_SOCKET=4 Change-Id: I9562a37a92c6140a5623db3c8fb5972e6a90aaa4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74183 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
2023-04-01soc/intel/xeon_sp/spr: Add ACPI support for Sapphire RapidsJonathan Zhang
Add ACPI support for Sapphire Rapids. Passes FWTS ACPI tests. The code was written from scratch because there are Xeon-SP specific implementation especially Integrated Input/Output (IIO). Change-Id: Ic2a9be0222e122ae087b9cc8e1859d257e3411d6 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71967 Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-28soc/intel/xeon_sp: Use simple device function for setting PMAX_LOCKJonathan Zhang
Change to use simple device function for setting PMAX_LOCK because the Sapphire Rapids PCU device is not scanned during coreboot PCIe bus scan and would see "PCI: dev is NULL!" failure. Change-Id: I3156a6adf874b324b5f4ff5857c40002220e47ab Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72400 Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-25soc/intel/xeon_sp/chip_common.c: Probe all buses in attach_iio_stacks()Jonathan Zhang
For some Xeon-SP (such as SPR-SP), more buses should be probed. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ica3c61493a0ff6c699b500f30788b2cf5a06c250 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-25soc/intel/xeon_sp/uncore_acpi.c: Add SPR-SP supportTim Chu
Add support for Intel SPR-SP to uncore_acpi.c. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com> Change-Id: I4c436a60743bee21b3b6e4060d7874a6cdc75ecf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-24soc/intel/xeon_sp/smihandler.c: enable support for spr-spTim Chu
For SPR-SP, the SMM_FEATURE_CONTROL register is in UBOX_URACU_FUNC instead of UBOX_DEV_PMON. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ide46c5f9cdf65b7e05552449b08ad4d7246664cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-23soc/intel/xeon_sp: Report platform cpu infoNaresh Solanki
Add platform cpu info for known microcode, print cpuid & processor branding string. This will print as in the following example: CPU: Intel(R) Xeon(R) Platinum 8468H CPU: ID 806f6, Sapphire Rapids E3, ucode: 2b000130 CPU: AES supported, TXT supported, VT supported Change-Id: I9c08fb924aad81608f554523432ab6a549b1b75f Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-23soc/intel/xeon_sp: Fix PCH IOAPIC IDPatrick Rudolph
FSP may program a different ID under certain circumstances. Read IOAPIC ID from hardware instead of using some define that might not reflect how hardware is configured. Change-Id: Ia91cb4aef9d15520b8b3402ec10e7b0a4355caeb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-22soc/intel/xeon_sp/uncore.c: Add CXL memory into memory mapJonathan Zhang
If the host supports CXL, get proximity domain info from FSP HOB. The proximity domains may include both processor domains and CXL domains. Add header definition for proximity domain. Add CXL memory into memory map. Change-Id: If3f856958a3e6ed3909240ee455bb639e487087f Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/xeon_sp/uncore.c: skip configuring VTD devJonathan Zhang
DPR should not be configured for VTD devices of other stacks for SPR-SP. Such processor(s) would be configured with SOC_INTEL_MMAPVTD_ONLY_FOR_DPR. Change-Id: Ib33b1b62f59a10d362c6585b1403490d4a1aedeb Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72616 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/xeon_sp/uncore.c: Add NCMEM base/limit to map entriesJonathan Zhang
... instead of ME base/limit if the processor is configured with SOC_INTEL_HAS_NCMEM. Change-Id: I95783cad1a2d5a3599d120ea0c98e2aa8703bdb4 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72615 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/xeon_sp/spr: Add soc set_cmos_mrc_cold_boot_flagJohnny Lin
This soc utility function can set cmos flag to enforce FSP MRC training. Change-Id: I88004cbfdcbe8870726493576dfc31de4b6036a9 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/xeon_sp: Enable FSP_ERROR_INFO_HOB handlingTim Chu
After calling FSP MemoryInit API, if there is an error, some FSPs (such as SPR-SP FSP) is capable of generating FSP_ERROR_INFO_HOB. Check existence of such a HOB and handle it accordingly. Change-Id: Icb5c31daa223ba6b06ba1b2de4f8808e0b27899e Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-21soc/intel/xeon_sp/spr/cpu: add missing device_match_mask in CPU tableFelix Held
Commit 6a6ac1e0b929 ("arch/x86/cpu: introduce and use device_match_mask") added the device_match_mask element to the cpu_device_id struct and uses it to be able to mask off for example the stepping ID when checking for CPU table entry that matches the silicon the code is running on. Commit 3ed903fda9cb ("soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage code") added a CPU table that was missing the device_match_mask which results in this being 0, so the first entry of the CPU table would match for any Intel CPU which isn't the intended behavior. Also use CPU_TABLE_END instead of the final {0, 0, 0} array element. Likely all entries could be replaced by one entry that uses the CPUID_ALL_STEPPINGS_MASK instead of the CPUID_EXACT_MATCH_MASK, but that's out of scope for this fix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0be2e9fe3c31487c83c9b1cf305a985416760b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-19soc/intel/xeon_sp/Makefile.inc: Build EBG for SPR-SPTim Chu
Intel SPR-SP chipset has EBG instead of LBG. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I9429fe332bb5f01a41aa205c76ad9f0159f93eee Reviewed-on: https://review.coreboot.org/c/coreboot/+/71959 Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com> Reviewed-by: TimLiu-SMCI <timliu@supermicro.com.tw> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-19soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage codeJonathan Zhang
It implements SPR ramstage including silicon initialization, MSR programming, MP init and certain registers locking before booting to payload. Change-Id: I128fdc6e58c49fb5abf911d6ffa91e7411f6d1e2 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-19soc/intel/xeon_sp/spr: Add header files and romstage codeJonathan Zhang
Several FSP HOBs processing codes are similar to Intel Cooperlake-SP codes in soc/intel/xeon_sp/cpx. Register datasheet please reference Sapphire Rapids EDS Vol2 Doc#612246 and Emmitsburg PCH EDS Doc#606161. Change-Id: Ia022534e5206dbeec946d3e5f3c66bcb5628748f Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-19soc/intel/xeon_sp: add MSR definitions for SPR-SPDavid Hendricks
Some MSRs used in SPR code are common among currently supported Xeon-SP generations and are added to the top-level Xeon-SP msr.h. MSRs which have changed are added to SPR's soc_msr.h. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: I92b433a9686734716dc7936895fb79c7751f7f9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-19soc/intel/xeon_sp: Split SKX/CPX MSRs into separate headersJonathan Zhang
Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: I2ecfebdde453a48b7b0e6f21b3c4394411eed671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-19soc/intel/xeon_sp: Add P2SB definition for SPR-SPJonathan Zhang
Change-Id: I2ece7aac4339266068d4fc8fb1c58d0573eb2895 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-03-15soc/intel/xeon_sp: Rename nb_acpi.c to uncore_acpi.cJohnny Lin
With newer xeon_sp processors, the concept of "north bridge" became obsolete, instead uncore should be used. Therefore we use uncore_acpi.c (instead of nb_acpi.c) going forward. Change-Id: I91ec9023152996bf9f2300a369aff3c4f19d75fd Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-10xeon_sp: Setup x2apic in SRATNaresh Solanki
Set up SRAT table in X2APIC mode when necessary. Change-Id: Ib8b4cebefe81f7b5514524dba2fa364eee4bb157 Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-09soc/intel/xeon_sp: rework lock_pam0123() to accomodate hidden SAD deviceJonathan Zhang
For Intel SPR-SP, the SAD device is hidden, so pcidev_path_on_bus() returns NULL. Therefore use pci_s_write_config32() instead. Move lock_pam0123() from finalize.c to util.c, to be together with unlock_pam_regions(). Change-Id: Ib08d423d8c4d482612077b66dab3878018da8f2b Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-03-09soc/intel/xeon_sp: use get_socket_ubox_busno() to hide soc specificsJonathan Zhang
Intel SPR-SP has its specific way to get the bus number of ubox. Move the current implementations to CPX-SP and SKX-SP folders. Change-Id: I2b69be74d140115f9f78bc991fb690e3c90c88db Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-03-07soc/intel/xeon_sp: Add PM definition for SPR-SPDavid Hendricks
Change-Id: I13ed156a1b967e87fa30b1867feed03c3d17b992 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-04xeon/spr: Set ACPI CPU string for 12bitNaresh Solanki
On platforms with more than 255 cores the ACPI CPU string would overflow and generate duplicates. Fix that by changing the string to hex and use 3 digits. Test: Able to boot without ACPI errors on IBM/SBP1 which has 384 actives cores. Change-Id: I1887928da0c049c27e2ec129f49051b24048b33b Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-03soc/intel/xeon_sp: Fix CBMEM corruptionPatrick Rudolph
On the 4 socket IBM/SBP1 platform with 384 cores lots of space for ACPI tables is required. Bump MAX_ACPI_TABLE_SIZE_KB to 400 to fix CBMEM corruption. Change-Id: Ifbd79e84097231b41f900425a2e8750dce71a25a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-01soc/intel/xeon_sp/spr: Select DISABLE_ACPI_HIBERNATE to remove S4 stateTim Chu
Server platform doesn't have S4 state so select DISABLE_ACPI_HIBERNATE to remove S4 state from available sleepstates. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Ie5ddb1a98cd5bbd854b915c93694d1ebcb9bddd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-02-26soc/intel/xeon_sp: Drop unused cpu.h headerArthur Heymans
Change-Id: I42856424d3b55107f1758fb05f7ddbee3550d8b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-23soc/intel/xeon_sp/uncore.c: mark TSEG/SMM region as reservedJonathan Zhang
Change-Id: I5f534a898de4ba58ac7d65c5bd6ee10eafa648e4 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-23soc/intel: Use common codeflow for MP initArthur Heymans
This fixes MP init on xeon_sp SoCs which was broken by 69cd729 (mb/*: Remove lapic from devicetree). Alderlake cpu code was linked in romstage but unused so drop it. Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-22soc/intel/xeon_sp/spr: Add common device treeTim Chu
Add common device tree used for EGS platform. Also add register setting shared for all EGS platform. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I812f621ee9d1643fd4fa35df92443d64f7aaabc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-02-19soc/intel/xeon_sp/finalize.c: Set BIOS_DONE MSR as applicableTim Chu
If BIOS_DONE MSR is supported, set it after ReadyToBoot, because FSP programs certain registers via Notify phase ReadyToBoot and it cannot be modified by FSP after coreboot has set BIOS_DONE MSR, therefore we try to set BIOS_DONE MSR as late as possible to avoid this. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Change-Id: I4f19a7c54818231ebbccd2b6f8b23f47b117eb1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71964 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-17soc/intel/xeon_sp: move PCH specific code into lbg directoryJonathan Zhang
pmc_lock_smi() and pmc_lockdown_config() have PCH specific implementations. Move them from common lockdown.c and pmc.c into lbg/soc_pmutil.c. Move sata_lockdown_config() and spi_lockdown_config() to lbg/lockdown.c. While here, fix some coding style issues. Change-Id: I9b357ce877123530dd5c310a730808b6e651712e Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-02-16soc/intel/xeon_sp: add ebg (Emmitsburg PCH) directoryTim Chu
EBG (Emmitsburg) PCH is used in Intel SPR-SP chipset. These changes are in accordance with the documentation: * Intel(R) Emmitsburg Platform Controller Hub External Design Specification. Document Number: 606161 * Emmitsburg PCH BIOS Specification. Document Number: 631063. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I393c1df75a344519fca7d680116f41f5f8bd9e87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2023-02-13soc/intel/xeon_sp/chip_common.c: check SOC_INTEL_PCIE_64BIT_ALLOCJonathan Zhang
Some FSPs (such as SPR-SP FSP) support SOC_INTEL_PCIE_64BIT_ALLOC. In such case, is_pci64bit_alloc() return 1. Change-Id: Ic33967255baf4675cd72e0db32ef3fb7f5658296 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72441 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-09arch/x86/include/cpu: introduce CPU_TABLE_END CPU table terminatorFelix Held
Instead of having a magic entry in the CPU device ID table list to tell find_cpu_driver that it has reached the end of the list, introduce and use CPU_TABLE_END. Since the vendor entry in the CPU device ID struct is compared against X86_VENDOR_INVALID which is 0, use X86_VENDOR_INVALID instead of the 0 in the CPU_TABLE_END definition. TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Angel Pons <th3fanbus@gmail.com> Change-Id: I0cae6d65b2265cf5ebf90fe1a9d885d0c489eb92 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72888 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-08arch/x86/cpu: introduce and use device_match_maskFelix Held
Instead of always doing exact matches between the CPUID read in identify_cpu and the device entries of the CPU device ID table, offer the possibility to use a bit mask in the CPUID matching. This allows covering all steppings of a CPU family/model with one entry and avoids that case of a missing new stepping causing the CPUs not being properly initialized. Some of the CPU device ID tables can now be deduplicated using the CPUID_ALL_STEPPINGS_MASK define, but that's outside of the scope of this patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0540b514ca42591c0d3468307a82b5612585f614 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72847 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-02-02soc/intel/xeon_sp: add Kconfig file for SPR-SPJonathan Zhang
Intel SPR-SP (Sapphire Rapids Scalable Processor) was product launched on Jan. 10, 2023. Change-Id: I14cf115b02d8edff9b48e744b798a3b1ba18b8bf Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-29soc/intel/xeon_sp/Kconfig: add SOC_INTEL_SAPPHIRERAPIDS_SPTim Chu
Intel SPR-SP (Sapphire Rapids Scalable Processor) chipset belongs to Xeon-SP family. It was product launched on Jan. 10, 2023. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Ifece05e2fbcc454cdee8e849cb4f146c89f54333 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-29soc/intel/xeon_sp/include/soc/pmc.h: move to lbg directoryJonathan Zhang
The PMC registers are quite different between LBG and EBG. Move pmc.h to lbg directory to differentiate. Change-Id: I6f14059942210c222631e11cced0b5c05d3c1dc6 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72399 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-23Revert "soc/intel/xeon_sp: Enable FSP_ERROR_INFO_HOB handling"Elyes Haouas
This reverts commit 80b1fa33. Reason for revert: "Error: CONFIG() used on unknown value (ENABLE_FSP_ERROR_INFO) at src/soc/intel/xeon_sp/romstage.c:20" Change-Id: I843322fc9d7ebbc30e9209ae933313f2668bfa40 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-23soc/intel/xeon_sp: Remove NO_FSP_TEMP_RAM_EXIT from common configJohnny Lin
For SPR-SP FSP MRC cache, NO_FSP_TEMP_RAM_EXIT should not be selected. Change-Id: I63101f286809d6cebb9a7d74443446cb3fe650c4 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71928 Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-23soc/intel/xeon_sp: Enable FSP_ERROR_INFO_HOB handlingTim Chu
After calling FSP MemoryInit API, if there is an error, some FSPs (such as SPR-SP FSP) is capable of generating FSP_ERROR_INFO_HOB. Check existence of such a HOB and handle it accordingly. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I612393ffac90815606f3f2544bc1518f6912e605 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71952 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-20soc/intel/*/include/soc/gpio.h: Add "IWYU pragma: export" commentElyes Haouas
Change-Id: If44a07503470f57037b59d03eea830703a3c604a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72100 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/intel: Remove unused <stddef.h>Elyes Haouas
Change-Id: I8432d799c9bf23058b7b903bb07f6c2b4308eeba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72103 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/intel/xeon_sp: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which includes soc/gpio.h which includes intelblocks/gpio.h which includes soc/gpio_defs.h. This patch also fixes alphabetic ordering of included headers. BUG=b:261778357 TEST=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I8135dc918cb04c854dc003966b7657806a42bad9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72042 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15soc/intel/xeon_sp/Kconfig: set up HPET_MIN_TICKSTim Chu
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I3256c3c6a4ea331efae00d78192355a1fd78d6d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-15soc/intel/xeon_sp: lock MSR_PPIN_CTL at BS_PAYLOAD_LOADTim Chu
MSR_PPIN_CTL may need to be read more than once, so lock PPIN CTL MSR at a late BS_PAYLOAD_LOAD boot state. This MSR is in platform scope and must only be locked once on each socket. Add a spinlock to do so. Tested=On OCP Craterlake single socket, rdmsr -a 0x04e shows 1. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: I8deb086339267cf36e41e16f189e1378f20b82f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-11soc/intel/xeon_sp: Setup DPR for all VT-d devicesJonathan Zhang
The Data Protected Range (DPR) needs to be set for all DPR devices, not only the root device. Separate the setup from the memory resource map reservation. Change-Id: I7e49db23960e3938e8e158082be3c5ecf3cf95f3 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-01-09soc/intel/xeon_sp/skx: Remove nested check for ACPI supportMarc Jones
Remove redundant nested check for ACPI support. Change-Id: Ie4b40382d304028135bcdd7851e2f48333570421 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-01-08soc/intel/xeon_sp: select SCO_INTEL_COMMON_BLOCK_TCOJohnny Lin
Also disable TCO timer through calling tco_configure(). If tco_configure() is not called, the TCO timeout would trigger SMI periodically about every 2 seconds with SMM log: "TCO_STS: BIT18 TIMEOUT" Tested=On AC CRB, does not see periodic SMI log. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I2d307ad16109ae11862dd5e5acc0f12f47b22582 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2023-01-08soc/intel/xeon_sp: Improve final MTRR solutionJonathan Zhang
If cbmem_top is not 1M aligned there will be a hole between DPR base and cbmem_top that the allocator will consider as unassigned memory. Resources could incorrectly be assigned to that region and the final MTRR solution will also try to skip that hole, therefore using a lot more variable MTRRs than needed. TESTED on Archer City 2S system: Uses 1 variable MTRR in the final setup instead of 7. Change-Id: I198f8d83bcfcdca3a770bd7f9a7060d5782a49fe Signed-off-by: Arthur Heymans <arthur.heymans@9elements.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2022-12-27{acpi,arch,soc}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-25soc/intel: Move max speed API to commonDinesh Gehlot
This patch moves API "smbios_cpu_get_max_speed_mhz()" to common code from board specific. This API was made generic in 'commit d34364bdea12 ("soc/intel/alderlake: Utilize `CPU_BCLK_MHZ` over dedicated macro")' BUG=NONE TEST=Boot and verified that SMBIOS max speed value is correct on brya and rex. (brya) dmidecode -t : "Max Speed: 4400 MHz" (rex) dmidecode -t : "Max Speed: 3400 MHz" Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I87040ab23319097287e191d7fc9579f16d716e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70879 Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22soc/intel/xeon_sp: Move codes to support new PCHTim Chu
Different PCHs have different definitions for registers. Here create a lbg folder and move lbg specific codes to this folder so that we can add new PCH code under xeon_sp folder. * Create lbg folder and move lbg specific codes from pch.c to soc_pch.c under lbg folder. * Rename lewisburg_pch_gpio_defs.h to gpio_soc_defs.h and move to lbg folder. * Rename gpio.c to soc_gpio.c and move to lbg folder. * Move pcr_ids.h to lbg folder. * Move lbg specific codes from pmutil.c to soc_pmutil.c under lbg folder. * Create and revise makefile for files under lbg folder. TEST=Can boot into OS on OCP Delta Lake. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I06555ed6612c632ea2ce1938d81781cd9348017a Reviewed-on: https://review.coreboot.org/c/coreboot/+/70009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22soc/intel/xeon_sp: Lock down LPC configurationJonathan Zhang
For LPC, set BIOS interface lock. Also set the LPC BIOS control to match the SPI BIOS control settings. BIOS control EISS and WPD are set when the BOOTMEDIA_SMM_BWP config option is set. Change-Id: I3e3edc63c0d43b11b0999239ea49304772a05275 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2022-12-20soc/intel/xeon_sp: Set IA32_SMRR_PHYSMASK lock bitJohnny Lin
smm_relocation_handler is run for each thread but IA32_SMRR_PHYS_BASE and IA32_SMRR_PHYS_MASK are core scope, need to avoid writing the same MSR that has been locked by another thread. Tested=On OCP Crater Lake, rdmsr -a 0x1f3 can see all cores set the lock bit. Change-Id: I9cf5a6761c9a9e1578c6132ef83e288540d41176 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2022-12-13soc/intel/xeon_sp/nb_acpi.c: Use read{16,32,64}p()Elyes Haouas
Change-Id: I89bfbab7850dd9bd29ca2097ee2efce058720ca7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-09soc/intel/xeon_sp/cpx: Allow creating meminfo for empty DIMM slotsAngel Pons
Introduce the mainboard-defined `mainboard_dimm_slot_exists()` function to allow creating SMBIOS type 17 entries for unpopulated DIMM slots. Change-Id: I1d9c41dd7d981842ca6f0294d9e6b0fedc0c98e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64036 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-06soc/intel/xeon_sp: Read ioapic configuration from hardwareArthur Heymans
This is more robust than hardcoding whathever FSP has set up and is a lot less code. Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70265 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-29Revert "src/arch/x86: Use core apic id to get cpu_index()"Arthur Heymans
This reverts commit 095c931cf12924da9011b47aa64f4a6f11d89f13. Previously cpu_info() was implemented with a struct on top of an aligned stack. As FSP changed the stack value cpu_info() could not be used in FSP context (which PPI is). Now cpu_info() uses GDT segments, which FSP does not touch so it can be used. This also exports cpu_infos from cpu.c as it's a convenient way to get the struct device * for a certain index. TESTED on aldrvp: FSP-S works and is able to run code on APs. Change-Id: I3a40156ba275b572d7d1913d8c17c24b4c8f6d78 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69509 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-28sb,soc/intel: Address TCO SECOND_TO_STS name collisionKyösti Mälkki
Later soc/intel/common/smbus addresses TCO2_STS as a separate 16-bit register, while baytrail and braswell assumes 32-bit wide TCO1_STS to extend as TCO2_STS. In src/soc/intel/denverton_ns: #define TCO2_STS_SECOND_TO 0x02 In soc/intel/baytrail,braswell: #define SECOND_TO_STS (1 << 17) Elsewehere #define SECOND_TO_STS (1 << 1) It's expected that we remove the first (1 << 17) case and only access TCO2_STS as a separate 16-bit register. For now, use unique names to avoid confusion. Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-26src/soc/intel: Remove unnecessary space after castsElyes Haouas
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-17soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fillDavid Milosevic
The dimm_info structure (defined in src/include/memory_info.h) currently does not hold information about the DIMM's node/controller ID. This patch extends the dimm_info structure by adding a new field for the node ID, called node_num. Also, adapt the dimm_info_fill() function accordingly to populate the newly-added field. Background: These changes are necessary for the Atlas mainboard, where we are currently experiencing issues with the DIMMs device/bank locator. Our 2 DIMMs share the same CHANNEL and DIMM ID but have a distinct NODE ID. By looking at the smbios table we see Channel-0-DIMM-0 for both DIMMs. Thus, we need their NODE IDs in order to distinguish them. This patch was tested by building and booting for the Alderlake-P RVP board, which has the same DIMM slot configuration as the Prodrive Atlas mainboard. Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68525 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-16drivers/intel/fsp2_0: add log level parameter to fsp_print_guidFelix Held
Not all functions that call fsp_print_guid print their output with the BIOS_SPEW log level, so introduce a new log level parameter so that the caller of fsp_print_guid can specify which log level fsp_print_guid should use for printing the GUID. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3b37afe703f506d4913f95a954368c0eec0f862d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69599 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-10soc/intel/xeon_sp: Move SMBIOS type 4 override functions from mainboardJingleHsuWiwynn
to soc Move SMBIOS type 4 override functions from mainboard to soc so that all xeon family cpus share same functions without implementing again. Tested=On OCP Deltalake, dmidecode -t 4 shows expected info. Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com> Change-Id: I17df8de67bc2f5e89ea04da36efb2480a7e73174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-11-08soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitionsJonathan Zhang
Intel FSPs of XEON server platforms define FSPX_CONFIG instead of FSP_X_CONFIG, which is expected by coreboot. Re-define in the common code. Update coreboot code to use FSP_X_CONFIG consistently. Tested=On OCP Delta Lake, boot up OS successfully. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-11-04Revert "soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility function"Felix Held
This reverts commit 3bc9fbb496c7e1ae346c8d7e98d2bcabbbbe8673. The patch that added hob_enhancedwarningloglib.h was marked as private after the Jenkins run, so I didn't see and submit it before submitting the patch that gets reverted by this commit. Temporary revert this patch to fix the coreboot tree until the issue with the missing patch is sorted out. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If56609dd2d91a70fe7e99ce86e0341f2b3fee3d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69229 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-04soc/intel/xeon_sp/cpx: Add get_ewl_hob() utility functionJohnny Lin
Change-Id: I8f949e9c881099c3723fca056e2c4732ca8b64cf Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69144 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2022-11-04soc/xeon_sp: Add weak mainboard_ewl_check for EWL check after FSP-MJohnny Lin
EWL (Enhanced Warning Log) is a FSP HOB generated by FSP-M that may contain several warnings/errors related to core, uncore and memory, etc. mainboard can override it in its romstage.c for its own Enhanced Warning Log check. Change-Id: I6f542e71d20307397c398fd757d9408438f681ed Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69143 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-28soc/intel/xeon_sp: Remove unused madt setup functionArthur Heymans
Change-Id: I248974c5a88768ee12f63fa77f3fa67a72ea510e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 15:00:22 +0000