coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2021-02-17	soc/intel/xeon_sp/smmrelocate: Don't run twice on the BSP	Arthur Heymans
	This only makes sense if relocation via MSR is possible, to relocate APs in parallel. xeon_sp hardware does not support these MSR. TESTED: ocp/deltalake boots fine. SMM is relocated on CPU 0 just like all other cores. Change-Id: Ic45e6985093b8c9a1cee13c87bc0f09c77aaa0d2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-24	soc/intel/xeon_sp: Enable SMI handler	Rocky Phagura
	SMI handler was not installed for Xeon_sp platforms. This enables SMM relocation and SMI handling. TESTED: - SMRR are correctly set - The save state revision is correct (0x00030101) - SMI's are properly generated and handled - SMM MSR save state are not supported, so relocate SMM on all cores in series - Verified on OCP/Deltalake mainboard. NOTE: - Code for accessing a CPU save state is not working for SMMLOADERV2, so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS pointer are not supported. - This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS is broken and needs to be fixed separately. It is unknown if TCO is supported. This might require a cleanup in the future. Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506 Signed-off-by: Rocky Phagura <rphagura@fb.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>