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Don't rely on the FSP-S setting the HPET and IOAPIC BDF. This makes
coreboot in control of these settings.
Change-Id: I937ebf05533019cb1a2be771ef3b9193a458dddf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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This is required for CBnT.
Change-Id: I290742c163f5f067c8d529ddca8e2d8572ab6e6a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47449
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ACPI bar was not programmed previously for which is needed to enable SMI's and
to check SMI status registers. The architecture of Lewisburg PCH is very
similar to SunrisePoint PCH thus we can use code from soc/intel/skylake.
TEST=build for Tiogapass and check ACPI base. Log message will now show
pmbase=501 (bit 0 is enable) instead of 0. Check by reading and writing
to io port 0x500.
Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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