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This only makes sense if relocation via MSR is possible, to relocate
APs in parallel. xeon_sp hardware does not support these MSR.
TESTED: ocp/deltalake boots fine. SMM is relocated on CPU 0 just like
all other cores.
Change-Id: Ic45e6985093b8c9a1cee13c87bc0f09c77aaa0d2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add MMCONF_BUS_NUMBER=256 as this was not defined for
this SoC.
Change-Id: I6ba861d3b7d5ac083c9b16c8f6ad179efd403bcd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'
Change-Id: I0c2da6b0e019c53ac963ebf851243c126ae930b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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ACPI S3 is a global state and it is no longer needed to
pass it as a parameter.
Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Override SMBIOS type 4 max speed. This field should be maximum speed
supported by the system. 3900MHz is expected for Cooper Lake.
Tested=Execute "dmidecode -t 4" to check max speed is correct.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I67edf657a2fe66b38e08056d558e1b360c4b8adc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I2279e2d7e6255a88953b2485c1f1a3b51a72c65e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Get rid of custom microcode caching in MPinit and SGX code and
use the caching introduced in intel_microcode_find() instead.
Change-Id: If3ccd4dcff221c88839ffeafa812f4c38cede63f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The values can be used during SMBIOS type 16 creation.
Tested=On OCP Delta Lake, dmidecode -t 16 to verify.
Handle 0x000A, DMI type 16, 23 bytes
Physical Memory Array
Location: System Board Or Motherboard
Use: System Memory
Error Correction Type: Single-bit ECC
Maximum Capacity: 1146 GB
Error Information Handle: Not Provided
Number Of Devices: 6
Change-Id: Id8f92dc96a7a3eb2e6db330adda98a7fe6d516c8
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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With top-aligned bootblock this is no longer globally needed.
The default maximum is now a generous 256 KiB with couple
platforms having lower limits of 32 KiB and 64 KiB.
Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Add the soc ACPI _CST table.
The table may be customized to support the different state
combinations and set by the mainboard config.
Tested on deltalake with acpi_idle driver.
Note, intel_idle may not use ACPI _CST table.
Change-Id: I359daa9556edbe263ab0a7f1849c96c8fe1a0da0
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
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Commit 393992f (cpu/mp_init: Fix microcode lock) fixed the semantics
of parallel loading microcode updates.
So now '*parallel = 1' really means loading MCU in parallel, which
seems to fail inconsistently on around 10% of the APs.
Change-Id: I755dd302abbb58537d840852e8e290bea282a674
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49671
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The xeon_sp/cpx has a second 'rc' heap inside FSP-M that is statically
allocated at the start of CAR. This breaks FSP 2.0 specification. This
can be worked around in the linker scripts to make sure coreboot and
FSP-M don't fight over the same memory.
Tested
- on ocp/deltalake: boot and the "Smashed stack detected in
romstage!" message at the end of romstage is gone.
- qemu/i440fx: BUILD_TIMELESS=1 results in the same binary.
Change-Id: I6d02b8a46a2a8ef00f34d8f257595d43f5d3d590
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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Only amd/picasso and amd/stoneyridge have reference to
PCNT and that could be replaced with acpigen.
Remove the PCNT name from GNVS OperationRegion elsewhere.
Change-Id: I7dd45a840b3585fd24c31fd923b991c34ab4d783
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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- Return the busno based on the stack number.
- Replace pci_mmio_read_config32 with pci_io_read_config32 to get the
register value before mapping the MMIOCFG space.
- Remove the plural `s` as the function now provides one bus number.
Change-Id: I6e78e31b8ab89b1bdcfdeffae2e193e698385186
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Replace acpi_create_gnvs() under soc/ to reflect their
changed funcionality.
Change-Id: I7bdbe0d6f795252e713e9785ada2b6320e6604b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48717
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia19018685749efdd543cb09c06df117690ab9d66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48803
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds the required gpio operations struct to soc/common gpio
code and hooks them up in all socs currently using the gpio block code,
except DNV-NS, which is handled in a separate change.
Also, add the gpio device to existing chipset devicetrees.
Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with
CB:48711 and OCP DeltaLake with CB:48672.
Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6
Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48583
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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More recent platforms (Cooperlake) need bigger sizes.
Change-Id: Ia3e81d051a03b54233eef6ccdc4740c1a709be40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The CedarIsland FSP Integration recommends locking down some things.
Change-Id: I72e04b55d69a8da79485e084b39c3bd38504897f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47168
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is required for CbNT.
Change-Id: I565a95cd2e76cb1c648884be6d1954288f6e4804
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This is required for CBnT.
Change-Id: If5637eb8dd7de406b24b92100b68c5fa11c16854
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Isochronous operation negatively impacts memory performance, as
per Intel MLC (Memory Latency Checker) benchmark results. Thus,
disable isochronous operation, like analogous UEFI firmware does.
The MLC results after disabling isoch:
"--max_bandwidth"
ALL Reads : 106948.17
3:1 Reads-Writes : 101580.46
2:1 Reads-Writes : 100523.26
1:1 Reads-Writes : 99059.44
Stream-triad like : 97762.47
"--peak_injection_bandwidth"
ALL Reads : 105724.3
3:1 Reads-Writes : 100655.8
2:1 Reads-Writes : 99463
1:1 Reads-Writes : 98708
Stream-triad like : 91515
The MLC results before disabling isoch:
"--max_bandwidth"
ALL Reads : 88824.96
3:1 Reads-Writes : 94820.81
2:1 Reads-Writes : 94867.53
1:1 Reads-Writes : 92567.36
Stream-triad like : 91900.43
"--peak_injection_bandwidth"
ALL Reads : 88859.6
3:1 Reads-Writes : 94064
2:1 Reads-Writes : 94186.2
1:1 Reads-Writes : 92516.1
Stream-triad like : 85147.4
TEST=On OCP Delta Lake, verify that MLC benchmark results have
improved.
Change-Id: I08c22ee001b601e607452b3f23fad969ecb484b4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48738
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the common block ACPI to further reduce the duplicate code.
Change-Id: If28d75cbb2a88363d70e3ae6a2cace46cb6bbbab
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48248
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On SKX FSP-M does not return if this is set too early.
Tested on OCP/Tiogapass, boots.
Change-Id: Ib8ef7bab36bfd4b62988768753d10b4d7b7d567f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48657
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TESTED on ocp/tiagopass: Microcode updates are properly applied (via
FIT). Tested with out of tree patches to report the revision.
Change-Id: I05ddc64090424aa333848d9a0f54f21538faf94c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Configure DPR to span the region between cbmem_top and TSEG base.
This region was already unavailable to the OS.
Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Don't use the common block acpi.h when we aren't using the
COMMON_ACPI config. Fixes a dependency build issue in an upcoming
commit.
Change-Id: I3b80f7bbdf81e594fdde5b750c666edd8ca7268d
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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SMI handler was not installed for Xeon_sp platforms. This enables SMM
relocation and SMI handling.
TESTED:
- SMRR are correctly set
- The save state revision is correct (0x00030101)
- SMI's are properly generated and handled
- SMM MSR save state are not supported, so relocate SMM on all cores
in series
- Verified on OCP/Deltalake mainboard.
NOTE:
- Code for accessing a CPU save state is not working for SMMLOADERV2,
so some SMM features like GSMI, SMMSTORE, updating the ACPI GNVS
pointer are not supported.
- This hooks up to some soc/intel/common like TCO and ACPI GNVS. GNVS
is broken and needs to be fixed separately. It is unknown if TCO is
supported. This might require a cleanup in the future.
Change-Id: Iabee5c72f0245ab988d477ac8df3d8d655a2a506
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46231
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TCO is configured by FSP. This mostly makes it possible to report TCO
events in SMM if enabled.
Change-Id: I4f81c7888e45ed01ee68b1d6e6a9986a4d735467
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47764
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PCH IOAPIC is not PCI discoverable.
Linux checks the BDF set in DMAR against the PCI class if it is a PIC,
which 00:1F.0 for instance isn't.
The SINIT ACM on the other hand bails out with ERROR CLASS:0xA, MAJOR
3, MINOR 7 if the BUS number is 0.
Change-Id: I9b8d35a66762247fde698e459e30ce4c8a2c7eb0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Don't rely on the FSP-S setting the HPET and IOAPIC BDF. This makes
coreboot in control of these settings.
Change-Id: I937ebf05533019cb1a2be771ef3b9193a458dddf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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This is required for CBnT.
Change-Id: Idfd5c01003e0d307631e5c6895ac02e89a9aff08
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46499
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Id824324325d05b52fb2b9ced04fd3539cc37bd55
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46555
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a soc specific callback for getting the IIO IOAPIC enumeration ID.
Tested on ocp/deltalake.
Change-Id: Id504c2159066e6cddd01d30649921447bef17b12
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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All this function does is looping over IIO stacks in the FSP HOB. The
only 'SOC/FSP specific' thing is the way to detect if the stack is an
IIO stack so add a callback to determine this.
Change-Id: I4fa9c54d50279213a4174186a23c3cc156e21c9a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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The somewhat unrelated return value makes the function harder to
understand and the return type is not consistently used. Use a
different helper function to get the HOB Pci64BitResourceAllocation
data.
Change-Id: I9a03cbb0ebbb48cc052d4c082d359c0087aaeb3e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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TESTED ocp/deltalake still boots.
Change-Id: I69f336c1ff348b8e820340b84494929f2c58ce72
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47296
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move set_bios_init_completion() and helper functions from skx
and cpx soc_util.c to xeon common util.c. There are some slight
differences between skx and cpx, so used the more correct cpx
functions. Both cpx and skx platforms boot as expected.
Change-Id: Ie416b3a43ccdd14a0eb542786593c2eb4d37450f
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47172
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Continue Xeon-SP de-duplication.
Move CPU helper functions from skx/ and cpx soc_util.c to common util.c.
Functions only used by util.c are updated to be static.
The following functions are moved:
int get_threads_per_package(void);
int get_platform_thread_count(void);
const IIO_UDS *get_iio_uds(void);
unsigned int soc_get_num_cpus(void);
void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits);
void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits,
uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread);
void xeonsp_init_cpu_config(void);
Change-Id: I118a451b9468459cf2c2194f31da1055e1435ebe
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47170
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Clean up the header includes.
Change-Id: I9f61d1a82b37bc0ed803967dc64decf18f44adc9
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
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This reports where TSEG is located and will be used when setting up
SMM.
Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The CAR set up by FSP-T is at base 0xfe800000 and has a 0x200000 size.
FSP-M seems to have a very large stack usage so it would overflow
other car symbols located below the coreboot stack such as timestamps
and the pre-ram console, which are now fixed.
TEST: boot with ocp/deltalake.
Change-Id: I886f9391ad79fcfa0724109393e3781a08d954b4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46895
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix the asl to use CONFIG_MAX_CPUS to create entries for
multiple cpu uncores. Don't add the RTxx resource entries multiple
times. The function is called for each CPUs.
Change-Id: Ia4eb9716ae4bd72fb4eb98649105be629623cbef
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47060
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Separate the get_stack_for_port into soc specific functions. This
removes a #if in common code.
Change-Id: Ib38a7d66947ded9b56193a9163e5128b2523e99c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Use a common function to get the number of CPUs for each soc. This
removes a #if for different function names in the common code.
Change-Id: I3348d37fcae72247731e465ec2a65d9583a2f180
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Prepare for common ACPI. Combine cpx and skx acpi.c into a single
file in xeon_sp. This is almost the last step in using common/block
acpi.
Change-Id: I5f40eb7909bb796907682c548219c7515f2ae4d1
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46600
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move CPX and SKX read_msr_ppin() to common util.c file.
Update drivers/ocp/smbios #include to match.
Change-Id: I4c4281d2d5ce679f5444a502fa88df04de9f2cd8
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Move common CPX and SKX chip.c code to chip_common.c.
Change-Id: I158882ab15659858c2b13b4a3e02a26ef8d4ed3c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Move the macros for printing debug information to debug.h in the
common console include directory and device include file.
These are available if the platform selects DEFAULT_CONSOLE_LOGLEVEL_8.
The macros could be used by any platform.
Change-Id: Ie237bdf8cdc42c76f38a0c820fdc92e81095f47c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Keep SLEEP_BUTTON flag in ACPI FADT to indicate that no sleep button
is present on Cooperlake platform.
Change-Id: I2ce435a7bda780b2d2ed00be3f3a8a080c4434ab
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I4077b9dfeeb2a9126c35bbdd3d14c52e55a5e87c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45404
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Prepare for common ACPI. Rename cpx_generated_p_state_entries()
to the common soc_power_states_generation() function. Add
empty soc_power_states_generation() to skx.
Change-Id: Ib7e8dfd2bb602f3e6ccdb5b221bc65236f66a875
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Prepare for common ACPI code. Move uncore_inject_dsdt() to the
uncore device acpi_inject_dsdt call.
Change-Id: Ida106238690eb1af17759ba6dbe4cb94344e3a94
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Prepare for common ACPI. Move the soc ACPI function prototypes from
cpx and skx chip.h to include/soc/acpi.h.
Change-Id: Ib7037cfb58825a2f6c25c122b95f72d5992dc04e
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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De-duplicate and prepare for common ACPI. Move common
northbridge ACPI code to nb_acpi.c. There are a few
differences between the skx and cpx defined FSP hob names
and CSTACKS that are managed with #if (CONFIG(SOC_INTEL_*_SP)).
Change-Id: I47ab1df3474d18643ef5ffc8199e09ea3dd32ccf
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Prepare for common ACPI code. Make acpi_fill_fadt() match
intel/commom/block/acpi/acpi.c function. Use soc_acpi_fill_fadt()
to set cpx fadt->flags.
Change-Id: I9c04dd478aa5e0f1467e63d06da094128edd9650
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45845
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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platform_fsp_silicon_init_params_cb is called by the fsp driver and
calls mainboard_silicon_init_params which sets the mainboard
PCH GPIOs.
Change-Id: Icf401e76741a6a7484295e999ddd566fe9510898
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46309
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Bryant Ou <bryant.ou.q@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Don't use the silicon-specific struct type to get common config
options. Instead, use the generic config_t typedef. This allows
the function to be moved to common code in upcoming patches.
Change-Id: If80b678037b4d79387e0a0f722c540df4aae2416
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46057
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to document number 338846 and 336062 this should be set to 46 bits.
Change-Id: I0bbe6c962ffc7d5dc722f1cacf55bc0d0615db59
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Without skipping of DRHD generation for non-PCIe stack, the OS
kernel detects incorrect DMAR table with following messages:
[ 0.561817] Your BIOS is broken; DMAR reported at address 0
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I098605daf12a264f390613581427ec722afcddaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ib329648f77acecccb0ced1806f61be252d03f2f4
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45869
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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For now only implement for one socket and some of the fields
are hard-coded for DDR4 including memory device type, data width
and ECC support.
Change-Id: I3cb72d18027d972140828970206834ff55b72022
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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With CPX-SP FSP, PCH IOAPIC handles the first 120(0x78) GSIs. Correct
the coreboot assignment of GSIs for IO APICs.
Without this patch, there are following target OS boot messages:
[ 1.098771] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119
[ 1.099159] GSI range [24-31] for new IOAPIC conflicts with GSI[0-119]
After this patch, the boot messages are:
[ 0.399498] IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-119
[ 0.399848] IOAPIC[1]: apic_id 9, version 32, address 0xfec01000, GSI 120-127
Also without this patch, there is boot stability issue. About one in
20 reboots, the target OS fails to boot with following failure:
[ 4.325795] mce: [Hardware Error]: Machine check events logged
[ 4.326597] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 9: ee2000000003110a
[ 4.327594] mce: [Hardware Error]: TSC 0 ADDR fe9e0000 MISC 228aa040101086
[ 4.328596] mce: [Hardware Error]: PROCESSOR 0:5065b TIME 1601443875 SOCKET 0 APIC 0 microcode 700001d
The MCE error happens in bank 9. The Model specific error code
shows it is about SAD_ERR_WB_TO_MMIO error (doc 604926), which means
something goes wrong when cache write back to mmio. It is a generic
transaction type error in level 2.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I45e941591300dad6d583a6dcb41f45e984753c07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45941
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Continue preparations for common ACPI code.
Add code from skx and common/acpi to check the SCI register
instead of using a define.
Change-Id: I6b638d28775320894a6ab24ef486e67c181591eb
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45844
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Prepare for common ACPI code. Move cpx soc ACPI functions to a
separate file, soc_acpi.c
Change-Id: I4aaca660e2f94d856676681417ae6c5d8c28a1f1
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Reorder the functions to make it easier to compare with
soc/intel/common/block/acpi/acpi.c.
Move the xeon_sp specific functions to the top.
Change-Id: I9034eb774a14ee1e2f9b16c7bd7673ebad69c113
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Prepare for merging cpx and skx pci_devs.h.
Remove duplicate defines. Move defines so they match each other.
Checked TiogaPass and DeltaLake BUILD_TIMELESS.
Change-Id: I146dd9e3f7eba053977d48dcf34d927dea310059
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45833
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. Move pch_enable_ioapic() into common block code.
2. Remove redundant LPC functions from SoC directory and
refer from block/lpc directory.
TEST=Able to build and boot hatch and tglrvp platform without seeing
any functional impact.
Change-Id: I2a6afc1da50c8ee5bccda7f5671b516dc31fe023
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Move duplicate .h files to top level xeon_sp/include/soc from
silicon specific cpx/include/soc and skx/include/soc.
Change-Id: I11d8a95a4b2f9451615b236798b3bd030c724858
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45221
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move and use the common xeon_sp/cpx/acpi asl for skx/.
There were only minor whitespace differences between the directories.
Update the mainboards to build the moved files.
TiogaPass coreboot.rom checked with BUILD_TIMELESS.
Change-Id: I5058a3fe8d96075a266fb92f10707bb94308c85b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45217
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit d51449d017410fedb55e93f71fb322749ba888b5.
Reason for revert: Causing compilation issue as below
src/soc/intel/xeon_sp/cpx/acpi.c: In function 'acpi_create_rhsa':
src/soc/intel/xeon_sp/cpx/acpi.c:825:4: error: initialization
discards 'const' qualifier from pointer target type
[-Werror=discarded-qualifiers]
&hob->PlatformData.IIO_resource[socket];
^
Change-Id: I7050060f1db7b9a9b5a77b5a6245c8fda05623a4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44998
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ACPI name for CSTACK. The name is PC00 to match with ACPI table
generated.
The PCIe domain has multiple PCIe stacks. devicetree.cb at the moment
does not support multiple PCIe stacks, eg. IIO stacks. For now, assign
the name to PCIe domain. In future, the name needs to be assigned to
CSTACK.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I24a6f29734452426218419cdcf66702edde96f46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Coverity detects performance inefficiencies as IIO_RESOUCE_INSTANCE
structure (size 623 bytes) is PASS_BY_VALUE. Fix it with
PASS_BY_REFERENCE.
Found-by: Coverity CID 1432759
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I9ae9ae38fe2c13c5433aa5e1dcbb30ebd30622ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: Id93aab5630e928ee4d7e957801e15a4cc8739fae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44594
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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IIO_UDS HOB was searched several times during the creation of DMAR table.
Reduce it to only once to improve boot time.
Both DRHD and ATSR subtable creations involve addition of PCIe bridge
device entries, combine the functions with
acpi_create_dmar_ds_pci_br_for_port().
When looping through ports to create PCIe bridge device entries,
use MAX_PORTS intead of NUMBER_PORTS_PER_SOCKET to improve boot time.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I469cd8473c50e105daeda6c5607592ae7cef6032
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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CPX-SP processor supports X2APIC.
Remove DMAR_X2APIC_OPT_OUT flag from DMAR table.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I63c9feda74c7abb591eac991cb98cdcad8afc158
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45375
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I8fc4e07269175eb2f40655b828e340697a9a892a
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45219
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Before MRC code execution, FSP interrogates EMCA MSR registers and other
registers to see if there are fatal errors happened during previous boot
session. If there are, error records are saved into
FSP_PREV_BOOT_ERR_SRC_HOB.
When the value of Length field of FSP_PREV_BOOT_ERR_SRC_HOB is 2, that means
the HOB does not contain any valid error record.
TESTED=Injects MCE error through cscript, reboot into OS, check boot log:
0x75904d70, 0x00000400 bytes: HOB_TYPE_GUID_EXTENSION
5138b5c5-9369-48ec-5b9738a2f7096675: FSP_PREV_BOOT_ERR_SRC_HOB_GUID
================ PREV_BOOT_ERR_SRC HOB DATA ================
hob: 0x75904d88, Length: 0x42
MCBANK ERR INFO:
Segment: 0, Socket: 0, ApicId: 0x0
McBankNum: 0x3
McBankStatus: 0xfe00000000800400
McBankAddr: 0xf0ff
McBankMisc: 0xfffffff0
MCBANK ERR INFO:
Segment: 0, Socket: 0, ApicId: 0x0
McBankNum: 0x4
McBankStatus: 0xfe00000000800400
McBankAddr: 0xfff0
McBankMisc: 0xfffffff0
0x75904d88: 42 00 01 00 00 00 00 00 03 00 00 04 80 00 00 00 B...............
0x75904d98: 00 fe ff f0 00 00 00 00 00 00 f0 ff ff ff 00 00 ................
0x75904da8: 00 00 01 00 00 00 00 00 04 00 00 04 80 00 00 00 ................
0x75904db8: 00 fe f0 ff 00 00 00 00 00 00 f0 ff ff ff 00 00 ................
0x75904dc8: 00 00
Change-Id: Idbace4c2500440b3c1cf2628dd921ca1a989ae81
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44974
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel CPX-SP FSP ww34 release added some features:
a. change DDR frequency limit.
b. define MRC debug message verbosity level.
c. enable/disablee of PCH DCI.
In addition, there are some changes to HOB data structures.
Update UPD and HOB header files and adapt soc accordingly.
TESTED=booted on YV3 DVT to target OS command line. Also rebooted okay.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iadbf5dc850c445f988bc7f07a24165abed2298c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44685
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This will remove the warning:
"src/soc/intel/xeon_sp/cpx/Kconfig:79:warning: config symbol 'CPU_BCLK_MHZ' uses select, but is not boolean or tristate"
Change-Id: I2cfaf347b638e3847caa167e7efda89e9202960a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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Similar to commit b45ed65, the HOB structure is actually a 8 byte
address pointing to the HOB data.
Tested=Verified the values of the hob fields are the same printed by
soc_display_memmap_hob().
Change-Id: I348d3cd80a56e86d22f20fcadf0316b462b86829
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Implement ACPI P-state support to enable driver acpi_cpufreq.
This patch leverages code from the Skylake project.
Tested=On OCP Delta Lake
cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
1501000 1500000 1400000 1300000 1200000 1100000 1000000 900000 800000
Change-Id: I3bf3ad7f82fbf196a2134a8138b10176fc8be2cc
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Intel CPX-SP FSP added support for VT-d through adding UPD
parameter X2apic. Based on devicetree.cb setting, enable
VT-d programming through FSP-M.
When VT-d is enabled, add DMAR ACPI table.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ic66374af6e53fb847c1bdc324eb3f4e01c334a94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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coherency_support and ats_support are not supported by CPX-SP FSP.
Remove them from soc_intel_xeon_sp_cpx_config struct.
Remove corresponding settings from DeltaLake devicetree.cb.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ibe1c4e88817fc4be7915e95fa829f0a4c0d947f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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Add CPUID for CPX-SP A1 (also called QS) processor.
DeltaLake DVT server uses CPX-SP A1 processor.
TESTED=booted DeltaLake DVT server to target OS.
[root@localhost ~]# dmidecode -t 1
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x0001, DMI type 1, 27 bytes
System Information
Manufacturer: Wiwynn
Product Name: Delta Lake DVT
Version: YoDL03
Serial Number: BZA02200122N01A
UUID: 000A0A22-2C29-1ED6-8259-000055DA2BFF
Wake-up Type: Reserved
SKU Number: Not Specified
Family: DeltaLake
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ic8975f6bf752fd685b38b2d1f0a4da41983b57f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Tested=On OCP Delta Lake, OpenBMC sensor-util can see PCH Temp readings.
Change-Id: I39d0d0a982476f9fece51cfa19dcbd0da5dea690
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44075
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel CPX-SP ww32 release has a number of bug fixes:
a. It fixed the issue related to some PCIe ports being hidden. This
affected DeltaLake config A, made the onboard PCIe NIC device not
working. ww32 release added two UPD parameters: PEXPHIDE, HidePEXPMenu.
b. It fixed the regression related to MRC cache.
c. It fixed the issue related to VT-d support, and added X2apic UPD
paramter. A separate PR will be submitted to enable VT-d in coreboot.
d. It fixed the issue related to enabling thermal device with PCI
or ACPI mode. [CB:44075] was submitted to enable it in coreboot.
e. It fixed the issue of FSP log level change UPD parameter DebugPrintLevel
not working.
There is a change in IIO UDS Hob.
TESTED=booted YV3 config A, and rebooted it. Access the target OS
remotely.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Set HWP base feature, enable EPP, lock thermal interrupt and lock MSR
Tested=On OCP Delta Lake, rdmsr 0x1aa shows 403040
Change-Id: I6d23de4032562095db1aaf96ddfd2b70a4517faa
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44171
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Before this change, we have this problem (boot log from DeltaLake
config A server):
Jumping to boot code at 0x00040000(0x755f6000)
Stack overrun on CPU0 (address 0x7574a000 overwritten). Increase stack from current 4096 bytes
ERROR: BUG ENCOUNTERED at file 'src/lib/stack.c', line 43
Linux version 4.16.18
Configure STACK_SIZE to make it larger to fix above problem.
Now, we have this boot log:
BS: BS_PAYLOAD_LOAD exit times (exec / console): 326 / 21727 ms
Jumping to boot code at 0x00040000(0x752f2000)
CPU0: stack: 0x75746000 - 0x7574a000, lowest used address 0x7574681c, stack used: 14308 bytes
Linux version 4.16.18
TESTED=booted YV3 config A to target OS.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ia04a3ee0cd37177ecab65469855a1cf920742458
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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CPX-SP FSP is FSP 2.2, so select PLATFORM_USES_FSP2_2. SKX-SP continues
to select PLATFORM_USES_FSP2_0, as SKX-SP FSP is FSP 2.0.
Correct DCACHE_RAM_BASE. Increase FSP_TEMP_RAM_SIZE, DCACHE_BSP_STACK_SIZE,
and adjust DCACHE_RAM_SIZE accordingly. Thus the workaround of hardcoding
StackBase and StackSize FSP-M UPD parameters is removed.
Add CPX-SP soc implementation of soc_fsp_multi_phase_init_is_enable()
to indicate that FSP-S multi phase init is not enabled, since it is
not supported by CPX-SP FSP.
TESTED=booted YV3 config A to target OS.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I25e39083df1ebfe78871561b0a0e230b66524ea9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44049
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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CPX-SP processor has 2 IMC, there are 3 channels per IMC,
2 DIMMs per channel.
It supports DDR4.
Configure default values for DIMM_MAX and DIMM_SPD_SIZE accordingly.
Change-Id: I66cc512465362d5ba04dc36534360c94ca23e77a
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43982
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SystemMemoryMapHob is necessary for SMBIOS type 17 among other things.
It is a fairly large structure, so the pointer to the data instead of
the structure itself, is included in the HOB. Use pointer to
SystemMemoryMapHob structure to interpret SystemMemoryHob HOB body.
Adjust the structure definition to match with CPX-SP ww28 release.
Display more fields to ensure the structure definition is correct.
TEST=Boot DeltaLake server, and check field values of SystemMemoryMapHob
to make sure they are correct:
0x7590a090, 0x00000020 bytes: HOB_TYPE_GUID_EXTENSION
f8870015-6994-4b98-95a2bd56da91c07f: FSP_SYSTEM_MEMORYMAP_HOB_GUID
================== MEMORY MAP HOB DATA ==================
hob: 0x777f7000, structure size: 0x6c88
lowMemBase: 0x0, lowMemSize: 0x20, highMemBase: 0x40, highMemSize: 0x5d0
memSize: 0x600, memFreq: 0xb76
NumChPerMC: 3
SystemMemoryMapElement Entries: 2, entry size: 16
memory_map 0 BaseAddress: 0x0, ElementSize: 0x20, Type: 0x1
memory_map 1 BaseAddress: 0x40, ElementSize: 0x5d0, Type: 0x1
BiosFisVersion: 0x0
MmiohBase: 0x80000
0x777f7000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
...
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I271bcbd6030276b8fcd99d5b4f2c93f034dd9b52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43336
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2cf11b784299708f02fd749dcb887b6d25f86f5b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This file does not contain useful information and is not used to build
the image. The common GPIO driver from soc/intel/common uses layout in
lewisburg_pch_gpio_defs.h [1,2] file, which is correct for all chipsets
from the Lewisburg family: C621, C621A, C622, C624, C625, C626, C627,
C627A, C628, C629, C629A [3]
[1] src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h
[2] https://review.coreboot.org/c/coreboot/+/39425
[3] Intel document #547817
Change-Id: I1f3ac4afff9e628890df8cec075fd3e42a590172
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43535
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Bryant Ou <bryant.ou.q@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as
reset register in FADT. How unsurprising. We might as well use that
information to automatically fill in the FADT accordingly. So, do it.
To avoid having x86-specific code under arch-agnostic `acpi/`, create a
new optional `arch_fill_fadt` function, and override it for x86 systems.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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They are ignored if the ACPI_FADT_WBINVD flag is set, which is required
on current ACPI versions and only maintained for ACPI 1.0 compatibility.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Instead, just flip the desired bits using bitwise operations. As this is
initially zero, the resulting value is the same. This allows flags to be
set from anywhere regardless of execution order.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Icfd580a20524936cd0adac574331b09fb2aea925
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43387
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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None of the currently-supported chips has PM1b_EVT nor PM1b_CNT event
register blocks. According to the ACPI specification, version 6.3,
sections 4.8.1.1 and 4.8.1.2 (PM1 Event/Control Registers):
If the PM1b_EVT_BLK is not supported, its pointer contains a value of
zero in the FADT.
If the PM1b_CNT_BLK is not supported, its pointer contains a value of
zero in the FADT.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything with PM1b for now. So, drop unneeded writes to PM1b fields.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Iff788b2ff17ba190a8dd9b0b540f1ef059a1a0ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43380
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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None of the currently-supported chips has a GPE1 block. The ACPI spec,
version 6.3, section 4.8.1.6 (General-Purpose Event Registers) says:
If a generic register block is not supported then its respective
block pointer and block length values in the FADT table contain zeros.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything with GPE1 for now. So, drop the unneeded writes to GPE1 fields.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Iefc4bbc6e16fac12e0a9324d5a50b20aad59a6cd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43379
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested on OCP Delta Lake with lspci checking if PCIe speed is changed
are expected.
Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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