| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2020-03-26 | soc/intel/xeon_sp: Configure P2SB BAR in bootblock | Andrey Petrov | |
| In order to use early serial output we need to enable P2SB BAR0, because that allows PCR access to PCH registers. TEST=tested on OCP Tioga Pass Change-Id: I476f90b2df67b8045582f0b72dd680dea5a9a275 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> | |||
| 2020-03-26 | soc/intel/xeon_sp: Refactor code to allow for additional CPUs types | Andrey Petrov | |
| Refactor the code and split it into Xeon common and CPU-specific code. Move most Skylake-SP code into skx/ and keep common code in the current folder. This is a preparation for future work that will enable next generation server CPU. TEST=Tested on OCP Tioga Pass. There does not seem to be degradation of stability as far as I could tell. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> | |||
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