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2020-05-01soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better ↵Subrata Banik
understanding BIT 1 -> DEBUG_INTERFACE_UART_8250IO BIT 4 -> DEBUG_INTERFACE_LPSS_SERIAL_IO Change-Id: I566b9dc82b2289af42e58705ebeee51179886f1f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-01soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetreeMeera Ravindranath
This CL adds support to fill PcieRpClkReqDetect UPD from devicetree. Filling this UPD will allow FSP to enable proper clksrc gpio configuration. BUG=None BRANCH=None TEST=Build and boot tglrvp. Change-Id: Iad0ba94fea019623a5b98fff0cb4a2cd1d2a7bd7 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-05-01src: Remove unused 'include <cpu/x86/cache.h>'Elyes HAOUAS
Change-Id: I2bf1eb87bb5476dd77b5a56dfe8846e82d414523 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40666 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/intel/tigerlake: Check SPD is not NULL before printEric Lai
Check SPD is not NULL before print. This can prevent the system from hanging up. BUG=b:154445630 TEST=Check NULL SPD is not print. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Iccd9fce99eda7ae2b8fb1b4f3c2e635c2a428f04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40560 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-29soc/intel/tigerlake: Add method to look up GPIO com ID for an indexVenkata Krishna Nimmagadda
This patch adds GPID, a helper method to look up GPIO community ID for an index. This patch also includes Intel's common GPIO ASL code. CGPM method in the common code uses the GPID method introduced in this patch. BUG=b:148892882 BRANCH=none TEST="BUILD volteer and ripto" Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Id6a00fb8adef0285d6bbc35cd5a44539bd3be6b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40478 Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-28soc/intel/tigerlake: fix call to print_spd_info()Nick Vaccaro
Pointer passed to print_spd_info() from meminit.c needs to be dereferenced first, so this change dereferences it. BUG=b:154352883 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, login to kernel and execute the following cbmem command: localhost ~ # cbmem -c | grep LPDDR4X and verify it returns "SPD: module type is LPDDR4X" Change-Id: I5ff64121f0d50947c4946e9e02460dfb7319d01a Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-04-28device: Constify struct device * parameter to write_acpi_tablesFurquan Shaikh
.write_acpi_tables() should not be updating the device structure. This change makes the struct device * argument to it as const. Change-Id: I50d013e83a404e0a0e3837ca16fa75c7eaa0e14a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-04-25soc/intel/tigerlake: Fix FSP SPD index for DDR4Furquan Shaikh
For DDR4, FSP expects channel 0 to set SPD for index 0 and channel 1 to set SPD for index 4. This change adds a helper macro to translate DDR4 channel # to the index # that the FSP expects. BUG=b:154445630 TEST=Verified that memory initialization for DDR4 is successful. Change-Id: I2b6ea2433453a574970c1c33ff629fd54ff5d508 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-24soc/intel/tigerlake: Add ACPI GPIO opAlex Levin
Add acpigen methods which generate operations to get/set/clear RX/TX GPIOs. Verify it matches https://doc.coreboot.org/acpi/gpio.html. BUG=b:149588766 TEST=confirmed with touchscreen gpios. Signed-off-by: Alex Levin <levinale@chromium.org> Change-Id: Id9fe26f14a606ceedb9db02d76fe8d466d3a21af Reviewed-on: https://review.coreboot.org/c/coreboot/+/40550 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jes Klinke <jbk@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-22soc/intel/tigerlake: Configure TCSS power managementJohn Zhao
Add Type-C subsystem power management support for RTD3. BUG=b:140290596 TEST=Include "tcss.asl" in platform "dsdt.asl" for coreboot build with the firmware CM. Added acpi debug and booted to kernel. Probed devices PM_STATE transition from D0 to D3 entry/exit while system at S0. TBT PCIe root ports: 00:07.0/00:07.1/00:07.2/00:07.3, offset:0xA4, PM_STATE:D3HT. xhci:00:0d.0, offset:0x74, PM_STATE:D0D3. dma:00:0d.2/00.0d.3, offset:0x84, PM_STATE:PMST. Verified xhci/dma/pcie root ports power runtime_status to be suspended and suspended time tick through /sys/bus/pci/devices/bus:device:func/power. Change-Id: I127d3700ad426a44639ee93b4477be6638b42e1b Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-04-20soc/intel/tigerlake: Update iDisp Link UPD settingsSrinidhi N Kaushik
Remove explicit setting of iDisp Link parameters. These settings are related to configuration for the link between HD-Audio controller and Display unit for purposes of HDMI/DP Audio playback. During PO, observed that without setting these params display part was not binding. With the latest code verified that we dont need to explicitly set these parameters anymore. HDMI/DP audio playback works fine with default settings. BUG=b:151451125 BRANCH:none TEST= build and boot volteer/ripto and verify HDMI/DP audio playback Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie003d119918d363e2ff9172936b70416fd73c7f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40263 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jairaj Arava <jairaj.arava@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-20soc/intel/tigerlake: Merge the recent change from other platformsWonkyu Kim
Merge the recent change from other platform(ICL/JSL). - Update SKpMpInit setting - Update APIs for getting dev info - Update IGD related setting - Update debug interface setting BRANCH=none TEST=build and boot ripto/volteer Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ie4dd4bcef3d8afc71ae4a542dbe8e4ba385593cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/40349 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-17soc/intel/tigerlake: Remove eMMC/SD supportDuncan Laurie
Tigerlake platform does not have built in eMMC/SD support so all this code is unused and can be removed. Change-Id: I70ff983d175375171d5a649378f32f1062c0876d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40372 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14soc/intel/tigerlake: Fix TCSS TBT PCIE root ports scope typeJohn Zhao
TCSS TBT PCIE root ports scope type was mistakenly set to PCI_ENDPOINT. Fix the scope type to be PCI_SUB. BUG=b:141609884 TEST=Booted to kernel and verified no TBT PCIE root ports scope type mismatch error in kernel log. Change-Id: I844e7e9583992be496223fb51f24c5aa24fc7d21 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-04-14soc/intel/tigerlake: Implement CHIPSET_LOCKDOWNWonkyu Kim
BUG=b:151161585 BRANCH=none TEST=build and boot ripto/volteer and check FSP logs for lockdown parameters Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I63cec8a718285f424914e426d0399ed821588dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/39710 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-14soc/intel/tigerlake: Add function to dump ME firmware status informationKrishna Prasad Bhat
Add a function to dump ME Host Firmware Status registers. In tigerlake, Manufacturing mode is “No” if below conditions are satisfied, indicating end of manufacturing. Otherwise, manufacturing mode is "Yes". 1. Intel fuses are programmed (Indicated by HFSTS6[30] bit set) 2. The SPI flash descriptor region is locked. (Indicated by HFSTS1[4] cleared) BUG=None BRANCH=None TEST=Build and boot tglrvp. Change-Id: I831a51f9f482425bd3b97ef1d2404b1d06844d07 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-04-14soc/intel/{icl,tgl}: Make use of print_me_fw_version() from CSE libKrishna Prasad Bhat
Make use of print_me_fw_version() which is defined in the CSE lib to print ME firmware version information for icl,tgl. BUG=None BRANCH=None TEST=Build and boot iclrvp, tglrvp boards. Change-Id: Ief75403c490eee499a84372e54fa38ea3016cc11 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-04-14soc/intel/tigerlake: Configure RP settingWonkyu Kim
Add LTR and AER configuration to the root ports config. BUG=b:151166040 TEST= build and boot volteer and check LTR and AER value from FSP log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I668f2e5fea15019a9e5ae06fb4d55fa2aea69e8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/40262 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-13acpi: Bump FADT to revision 6Patrick Rudolph
Some of the revision 4 FADT fields were already updated to ACPI spec revision 6, but not all of them. In addition the advertised FADT revision was 3. Implement all fields as defined in version 6 and bump the advertised FADT revision to 6. Also set all used access_size fields and x_gpe0_blk to sane values as Windows 10 verifies those fields starting with FADT revision 5. Fixes: https://ticket.coreboot.org/issues/109 Tested on Windows 10. Change-Id: Ic649040025cd09ed3e490a521439ca4e681afbbf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-04-13soc/intel/tigerlake: Remove scs.aslAamir Bohra
Remove EMMC and SD card ACPI devices copied from Ice Lake. Tiger Lake does not support these controllers. BUG=b:151208782 TEST= Build volteer board Change-Id: I4b3e37f93b94757d16d775fb27bee644d9dc539e Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40228 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-11soc/intel/tigerlake: Disable MrcSafeConfigSrinidhi N Kaushik
This change disables MrcSafeConfig option during MRC training. MrcSafeConfig was enabled as part of the early testing. Now with FSP 2527, there is no need to set this config anymore. BUG=b:150357377 BRANCH=master TEST=build and boot ripto/volteer Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I4e4069d83754aaf1e4885d6912ab2a6d506c5269 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40106 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10Replace DEVICE_NOOP with noop_(set|read)_resourcesNico Huber
`.read_resources` and `.set_resources` are the only two device operations that are considered mandatory. Other function pointers can be left NULL. Having dedicated no-op implementations for the two mandatory fields should stop the leaking of no-op pointers to other fields. Change-Id: I6469a7568dc24317c95e238749d878e798b0a362 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40207 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10Drop unnecessary DEVICE_NOOP entriesNico Huber
Providing an explicit no-op function pointer is only necessary for `.read_resources` and `.set_resources`. All other device-operation pointers are optional and can be NULL. Change-Id: I3d139f7be86180558cabec04b8566873062e33be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40206 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-10soc/intel/tigerlake: Add support to initialize DDR4 MemoryVarun Joshi
Support to configure DDR4 memory variant. -Add support to read SPD data based on different memory topology. -Initialize FSP UPD's for DQ and DQS mapping. BUG=b:151702387 Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com> Change-Id: I47a5dcad3ee316871a6103b9d53ef7f6fc88d7d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39847 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-07soc/intel/tigerlake/acpi: Fix typo in HDA in commentSubrata Banik
HSA -> HDA (High Definition Audio) Change-Id: Ic0e6ad7b26105fdd6eca6cd11edcf2236e5c7123 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-04-07soc/intel/tigerlake: Allow mainboard to override DRAM part numberMarco Chen
In order to support mainboards that do not store DRAM part number in the traditional way i.e. within the CBFS SPD for soldered memory, this change provides a runtime callback to allow mainboards to provide DRAM part number from a custom location e.g. external EEPROM on volteer / dedede. For other boards it should be a NOP since the weak implementation of mainboard_get_dram_part_num does nothing. BUG=b:152019429 Change-Id: If940a76d36a7645a7441ba418aa7aec9af9f6319 Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39860 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-04-06soc/intel/tigerlake: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I482715c166ccf5d2f3cc25118d25b07dbfd6650a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-05fsp2_0: Gather Kconfig declarationsNico Huber
Move more Kconfig declarations to drivers/intel/fsp2_0/ and document them properly. This way, we don't have to repeat dependencies and have the prompts in a common place. We can also easily hide the prompt for the header path in case the FSP repository is used. SP platforms were skipped as their Kconfig is too weird but they shouldn't hold other platforms back. Change-Id: Iba5af49bcd15427e9eb9b111e6c4cc9bcb7adcae Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-05soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD.Srinidhi N Kaushik
This change updates memory configuration on Tiger Lake Platform to replace "Reserved9" with "DisableDimmCh#" UPD in init_spd_upds(). For reference https://review.coreboot.org/c/coreboot/+/39797 added "DisableDimmCh#" UPD. BUG=b:152000235 BRANCH=none TEST= build volteer and boot to kernel Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie0b5783a8bef02ec8c265fa5b47ce532a77b9675 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40061 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator`Nico Huber
These two identifiers were always very confusing. We're not filling and injecting generators. We are filling SSDTs and injecting into the DSDT. So drop the `_generator` suffix. Hopefully, this also makes ACPI look a little less scary. Change-Id: I6f0e79632c9c855f38fe24c0186388a25990c44d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39977 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: David Guckian Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-02soc/intel/tigerlake: Add macros and SPD information for DDR4Furquan Shaikh
This change adds new memory topologies (SODIMM, MIXED) that are supported by DDR4 and macros required for DDR4 support. Memory initialization support for DDR4 will be added in a follow-up change. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I4b565c3d71bbf437da64ac29597cc19e58f1b98a Reviewed-on: https://review.coreboot.org/c/coreboot/+/39866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-02soc/intel/tigerlake: Reorganize memory initialization supportFurquan Shaikh
This change reorganizes memory initialization code for LPDDR4x on TGL to allow sharing of code when adding support for other memory types. In follow-up changes, support for DDR4 will be added. 1. It adds configuration for memory topology which is currently only MEMORY_DOWN, however DDR4 requires more topologies to be supported. 2. spd_info structure is organized to allow mixed topologies as well. 3. DQ/DQS maps are organized to reflect hardware configuration. TEST=Verified that volteer still boots and memory initialization is successful. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib625f2ab30a6e1362a310d9abb3f2051f85c3013 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-04-01soc/intel/tigerlake: Remove Jasper Lake SoC referencesAamir Bohra
This implementation removes all JSL references from the TGL SoC code. Additionally, mainboard code changes are done to support build. BUG=b:150217037 TEST=build tglrvp and volteer Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-04-01soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoCAamir Bohra
Switch to using Jasper Lake SoC code from soc/intel/jasperlake and stop referring from soc/intel/tigerlake. Addtionally mainboard changes are done to support build. BUG=b:150217037 TEST=Build and boot waddledoo. Build jasperlake_rvp and volteer board. Change-Id: I39f117bd66cb610a305bcdb8ea65332fd0ff4814 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-03-30soc/intel/{icelake, tigerlake}: Remove DDI A lane programmingRonak Kanabar
For newer Intel graphics(>=11), The DDI port max lanes are set to 4 by default. And kernel driver no longer relies on coreboot to provide information via DDI_BUF_CTL_A(for DDI port A) register programming. Hence removing this code. BUG=b:150788968 BRANCH=None TEST=checked jslrvp and tglrvp compilation and boot. Change-Id: I32692501b60f48a07b8fbb9bb3a755b18f4b3ea9 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39313 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-30soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3Brandon Breitenstein
FSP UPD TcssAuxOri is used for setting the IOM_TYPEC_SW_CONFIGURATION_3. Configure TcssAuxOri to retimer enabled on the port 2 Type-C port. This setting informs the SoC that a retimer is taking care of SBU orientation therefore it does not need to do any flipping. The IOM_TYPEC_SW_CONFIGURATION_3 is a bitfield that controls the aux orientation settings for the Type-C ports. The TGL EDS describes this setting and what each bit represents. Reference section 3.6.5 in TGL EDS #575681 BUG=b:145943811 BRANCH=none TEST=Boot to OS and check Type-C port1 Display on volteer, Connecting Type-C display should work regardless of Type-C cable orientation. Change-Id: Iae356113cbdc72983f800060b1ebebe3c66b9daf Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39459 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-25soc/intel/tigerlake: Configure HyperthreadingWonkyu Kim
Configure Hyperthreading based on devicetree BUG=none TEST= Build and boot with FSP log and check Hyperthread setting Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Idc94e6b8ecd59a43be60bf60dc7dd0811ac0350b Reviewed-on: https://review.coreboot.org/c/coreboot/+/39683 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-23soc/intel/tigerlake: Update DCACHE_BSP_STACK_SIZETim Wawrzynczak
According to the latest Tigerlake Platform FSP Integration Guide, the minimum amount of stack needed for FSP-M is 256KiB. Change DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined empirically). JSL requires 192KiB. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ic9be6446c4db7f62479deab06ebeba2c7326e681 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-03-21soc/intel/tigerlake: Make PCH_DEV_UART3 macro definition properSubrata Banik
This patch makes PCH_DEV_UART3 macro referring to _PCH_DEV() rather calling _PCH_DEVFN(). Change-Id: I7bc060c3c5f1e0a0fed194704b4940db73f46985 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-20soc/intel: Enable GPIO functions in verstageBora Guvendik
Enable GPIO functionality in verstage so platforms can read a PCH GPIO in verstage to determine recovery mode. BUG=b:151102807 TEST=make build successful Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I4e3b9da307dcf59ab251d8a6a5e09c2a3cfc59fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/39501 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-20soc/intel/tigerlake: Enable ACPI support for PMC core OS driverVenkata Krishna Nimmagadda
PMC core driver in OS provides debug hooks to developers and end users to quickly figure out why their platform is not entering a deeper idle state such as S0ix. This patch adds INT33A1, a required ACPI device, to support that PMC core driver in tigerlake platform. BUG=b:146236297 BRANCH=none TEST="Build and flash volteer and verify it boots to kernel. Checked for valid files under /sys/kernel/debug/pmc_core." Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com> Change-Id: Ib7e583dc2943461a41d2a7ebde1f16a58a118975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39587 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-19soc/intel/tigerlake: add support to read SPD data from SMBusRonak Kanabar
Jasper Lake RVP has DDR4 variant which uses SMBus address to read SPD data. So, add support to read SPD data from SMBUS. BUG=None BRANCH=None TEST=Check compilation for Jasper Lake RVP and check memory training passes. Change-Id: I94f8707c731c8afa1106e387a246c000bd53a654 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39401 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-19soc/intel/tigerlake: Update header to avoid compilation issueMaulik V Vaghela
We were including stddefs.h and stdint.h but compilation fails when we use 'bool' type in file. Removing stddef.h and stdint.h and including 'types.h' which includes all data types BUG=None BRANCH=None TEST=Check if compilation passes when bool is used Change-Id: I4c9001f729f3103deba9d1fd631a8942c23276ee Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-03-18soc/intel/tigerlake: Correct number of gpio group for Jasper LakeMaulik V Vaghela
Correct number of gpio pad group for Jasper Lake SoC. BUG=None BRANCH=None Test=Code compilation for Jasper Lake RVP Change-Id: I381d0e48430e933569a3b22b66b4e6077383e9e2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-03-18soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBTBrandon Breitenstein
FSP needs to know to allow the root ports for USB4/TBT to be enabled This patch may need additional checks for each board as it might not be the right thing to turn them all on for every Tiger Lake board. BUG=b:141609883 BRANCH=NONE TEST=Built image and verified that the root ports were visible with lspci Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-17src/soc/intel/tigerlake: Fix incorrect use of Field objects in ASLRizwan Qureshi
Method RAOW is assuming that the first argument is a Field object and writing to it expecting the register to get updated. However, the callers are passing in the value of the Field object instead. This eventually is resulting the IMGCLK not getting enable/disabled on the platform. Fix this by sending the exact address of the register to be updated. Also MCCT was setting the clock frequency in both case i.e, Clock Enable and Disable. Split the MCCT method in two, MCON and MCOF to fix the sequencing like below MCON: Set frequency Enable clock MCOF: Disable clock Also, make use of MCON and MCOF methods for camera clock control in tglrvp. This is to avoid the buildbot marking the patch unstable. BUG=None BRANCH=None TEST=Build and Boot waddledoo board and verified that IMGCLKOUT for world facing camera is enabled/disabled and able to capture images. Build and Boot Tiger Lake RVP board and verified that IMGCLKOUT for world facing camera is enabled/disabled and able to capture images. Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: I8b886255d5f38819502ae1f4af0851b5a0922b22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39498 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-16soc/intel/tigerlake: Support ISHli feng
Add ACPI Object for ISH SSDT Enable/disable ISH based on devicetree BRANCH=none BUG=b:145946347 TEST=boot to OS with TGL RVP UP3 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca Reviewed-on: https://review.coreboot.org/c/coreboot/+/39480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-16src/soc/tigerlake_dev: Update PMC IPC Hardware IDJohn Zhao
Change PMC IPC HID from INT34D2 to INTC1026 along with new kernel pmc ipc driver. BUG=b:148949891 BRANCH=none TEST=Boot on Volteer and validate DP tunneling. Change-Id: I987e7bf76ad1f8ff534101c80661f7c027a60b51 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-15soc/intel/tigerlake: Match RP number with TGL EDSWonkyu Kim
Update RP number to 12 according to PCH EDS#576591 vol1 rev1.2. BUG=b:151208838 TEST=build RVP successfully Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Iabdbfd99f7154741c16da53bcd9d1c7ca4f81129 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-03-15soc/intel/tigerlake: Enable CNVi through dev_enabledSrinidhi N Kaushik
Check for dev enabled status for CNVi and update the UPD accordingly. BUG=none BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I15a03cc70f12e094badf942dd81f22bd09531051 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-03-15soc/intel/tigerlake: Update Cpu Ratio settingsSrinidhi N Kaushik
Add config to override CpuRatio or setting CpuRatio to allowed maximum processor non-turbo ratio. BUG=151175469 BRANCH=none TEST=Build and boot tglrvp and observe there is no extra reset in meminit. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I2fa883b443d0a4c77d62275faeacd1ed2c67a97c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39493 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-15soc/intel/tigerlake: Configure Vmx support using KconfigJohn Zhao
Change VmxEnable UPD value based on Kconfig ENABLE_VMX BUG=None TEST=Built image and booted to kernel. Change-Id: I725474643193223865a135813cf882fd7636d24a Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-12soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI tableJohn Zhao
Tigerlake platform supports Virtualization Technology for Directed I/O. Enable VT-d feature and generate DMAR ACPI table. BUG=None TEST=Booted to kernel and "dmesg | grep DMAR" to verify the DMAR ACPI remapping table existence. Retrieve /sys/firmware/acpi/tables/DMAR and "iasl -d DMAR" to check all entries. Change-Id: Ib89d0835385487735c63062a084794d9da19605e Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-03-12soc/intel/*/smihandler: Only compile in TCO SMI handler if neededPatrick Georgi
commit 7f9ceef disables TCO SMIs unless specifically enabled, so help the linker throw out the function that handles them in that case. Change-Id: Ia3c93b46e979fb8b99282875b188415f249d38dd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Michael Niewöhner
2020-03-12soc/intel/tigerlake: Configure L1Substates for PCH Root portsWonkyu Kim
Set value for PcieRpL1Substates according to devicetree. Chip config parameter PcieRpL1Substates uses (UPD value + 1) because UPD value of 0 for PcieRpL1Substates means disabled for FSP. In order to ensure that mainboard setting does not disable L1 substates incorrectly, chip config parameter values are offset by 1 with 0 meaning use FSP UPD default. get_l1_substate_control() ensures that the right UPD value is set in fsp_params. Chip config parameter values 0: Use FSP UPD default 1: Disable L1 substates 2: Use L1.1 3: Use L1.2 (FSP UPD default) BUG=none BRANCH=none TEST=Boot up and check FSP log for PCIe config for this values Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I66743a29ad182bd49b501ae73b79270a9eb88450 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39412 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-12soc/intel/tigerlake: Enable HDA through dev_enabledSrinidhi N Kaushik
Check for dev enabled status for HDA controller and update the UPD accordingly. BUG=151174264 BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Id5dfff275ed9906852ef7eb7461fbe89a3a115c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39441 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-11soc/intel/tigerlake: Save DIMM info by available nodesJamie Ryu
TEST=Verified that dmidecode produces output identical to private repo Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I951ea94c280b7dd5b67f320a264d13fca82a4596 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39359 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-11soc/intel/tigerlake: Correct FSP log interfaceRonak Kanabar
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART Add check for DEBUG_INTERFACE_TRACEHUB selection and set "PcdDebugInterfaceFlags" UPD accordingly. BUG=None TEST=boot jslrvp board with Debug FSP and check FSP UART log Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-03-11soc/intel/tigerlake: Fix stale device pointer usageKarthikeyan Ramasubramanian
TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I43cccd32589d75a9b0c7e60f8c82b19bbe6b69a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-03-10soc/intel: fix eist enablingMatt Delco
There was a bug like this for skylake that seems to have been copied to other SoCs. Signed-off-by: Matt Delco <delco@chromium.org> Change-Id: Ib4651eda46a064dfb59797ac8e1cb8c38bb8e38c Reviewed-on: https://review.coreboot.org/c/coreboot/+/39411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-03-10soc/intel/tigerlake: Enable Hybrid storage modeWonkyu Kim
To use Optane memory, we need to set 2x2 PCIe lane mode while we need to set 1x4 PCIe lane mode for NVMe. The mode can be selected using the FIT tool at build time. By enabling hybrid storage mode in FSP, FSP will set 2x2 PCIe lane mode if Optane memory is detected and the mode is not 2x2 and set 1x4 PCIe lane mode if Optane memory is not detected and the mode is not 1x4 during boot up. The mode is saved in SPI NOR for next boot. BUG=b:148604250 BRANCH=none TEST=Build and test booting TGLRVP from NVMe and Optane Check PCIe lane configuration. Show all the NVMe devices lspci -d ::0108 Show all the NVMe devices and be really verbose lspci -vvvd ::0108 Print PCIe lane capabilities and configurations for all the NVMe devices. lspci -vvvd ::0108 | grep -e x[124] Print all the PCIe information of the device ae:00.0 lspci -vvvs ae: Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39232 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-07soc/intel/tigerlake: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects pointer dev as FORWARD_NULL. Add sanity check for dev to prevent NULL pointer dereference if dev did not point to the audio device. BUG=CID 1420208 TEST=Built image successfully. Change-Id: I2a62da44c7044f9dc281eae0949f7f7b612ab238 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-07intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registersMichael Niewöhner
Add registers that are relevant for the case intrusion detection functionality. Intel documents: 332691-003EN, 335193-006, 341081-001, ... Change-Id: If12d21e8e6721abb877cbbfbbba8f0127a86d96b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-03-07intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selectedMichael Niewöhner
Enable TCO SMIs in common code, if selected by Kconfig. This is needed for the follow-up commits regarding INTRUDER interrupt. Tested on X11SSM-F. Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-03-06soc/intel/tigerlake: Enable CNVi ModeSrinidhi N Kaushik
Add configs to enable CNVi mode and CNViBtCore. BUG=none BRANCH=none TEST=Build and boot tglrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ic372348a1409b2594a85b71b2fc742be96b84b87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39317 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-06soc/intel/tigerlake: Avoid NULL pointer dereferenceJohn Zhao
Coverity detects pointer dev as FORWARD_NULL. Add sanity check for dev to prevent NULL pointer dereference. BUG=CID 1353148 TEST=Built and boot up to kernel. Change-Id: Ic0ad1ec79c950a3c17feccdde4f87f4a107fe8c0 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-03-04src: capitalize 'PCIe'Elyes HAOUAS
Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-03-04soc/intel/tigerlake: Update SerialIoUart settings for Tiger LakeSrinidhi N Kaushik
update SerialIoUartAutoFlow settings for Tiger Lake platform. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I5ff2c63857a868ca4ed72c6d93bf518e085b8879 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39169 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-03soc/intel/tigerlake: configure ethernetWonkyu Kim
Configure ethernet based on board config BUG=none BRANCH=none TEST= build TGLRVP and check ethernet is disabled based on devicetree Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I3286f5fefc962a5e55b5554982271ed6b885f7d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39153 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-03soc/intel/tigerlake: Add Jasper lake GPIO supportRonak Kanabar
Add gpio definition for Jasper Lake gpio controller. Also created a separate file for JSL and TGL gpio keeping common asl file. gpio_soc_defs.h must pass correct information/macro values to asl file for code to work. GPIO controller includes 4 gpio community and 10 groups. Patch adds definition for all gpio within community and groups Updated IRQ mapping for all gpios TEST=Check if jslrvp and tglrvp code is compiling Change-Id: Iae4e694ecb30658e43c5ed99e5436579fd7d2ed2 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-03-03src/soc/tigerlake: Add memory configuration support for Jasper LakeMeera Ravindranath
BUG=none BRANCH=none TEST=Build and verify boot of WaddleDoo. Change-Id: I8de502d3f05d52b9dae34e3b013c6d5b1896fa85 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-03-02soc/tigerlake: Correct FSP log interfaceWonkyu Kim
Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART. DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART BUG=None BRANCH=None TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39167 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-01soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by KconfigSubrata Banik
This change is mainly to control PlatformDebugConsent FSP UPD. PlatformDebugConsent is enabled if SOC_INTEL_<SOC>LAKE_DEBUG_CONSENT != 0. PlatformDebugConsent in FspmUpd.h has the details. TEST=Able to connect ITP/DCI with target system. Change-Id: I39fe84025cb2bff186d61b2fcad531db52e2b440 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-02-27soc/intel/tigerlake: Add display related UPD configs for Jasper LakeAamir Bohra
TEST=Build dedede board Change-Id: I942a7036bf627b3d8262756e5e2026dcb0949dd5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39131 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-27soc/intel/tigerlake: Update FSP params for Jasper LakeMaulik V Vaghela
Update FSP parameters for various configurations like: - graphics - USB - PCIe root ports - SD card - eMMC - Audio - Basic UART configuration These are the initial settings for JSL. This patch also corrects the debug_interface_flag definitions. TEST=Build dedede board Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-02-26soc/intel/tigerlake: Integrate Legacy 8254 timer supportSubrata Banik
This patch overrides required FSP-S UPDs to enable 8254 timer support for TGL if CONFIG_USE_LEGACY_8254_TIMER is selected. TEST=Required to boot TianoCore payload. Change-Id: Iaeff5c4b92691ed6ba7b71541ed4f947d5d299a8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-02-25soc/intel/common: Update Jasper Lake Device IDsMeera Ravindranath
Update Jasper Lake CPU, SA and PCH IDs. BUG=b:149185282 BRANCH=None TEST=Compilation for Jasper Lake board is working Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-02-25soc/intel/common/block: Move cse common functions into block/cseSubrata Banik
This patch cleans soc/intel/{cnl, icl, tgl} by moving common soc code into common/block/cse. Supported SoC can select existing HECI_DISABLE_USING_SMM option to select common cse code block to make heci function disable using sideband interface during SMM mode at preboot envionment. BUG=b:78109109 TEST=Able to make HECI disable in SMM mode successfully without any hang or errors in CNL, ICL and TGL platform. Change-Id: I22a4cc05d3967c7653d2abe2c829b4876516d179 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26133 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-25soc/intel/common/block: Move smihandler common functions into common codeSubrata Banik
This patch cleans soc/intel/{apl/cnl/skl/icl/tgl} by moving common soc code into common/block/smihandler.c BUG=b:78109109 TEST=Build and boot KBL/CNL/APL/ICL/TGL platform. Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-19soc/tigerlake: Add IRQ header and ACPI support for JSPMeera Ravindranath
Tigerlake irq.h and pci_irqs.asl have differences compared to Jasperlake. Hence renaming irq.h as irq_tgl.h and pci_irqs.asl as pci_irqs_tgl.asl Also adding a new file irq_jsl.h and pci_irqs_jsl.asl for Jasperlake SoC and allowing irq.h and pci_irqs.asl to choose the correct file based on SoC selected. BUG=None BRANCH=None TEST=Compilation for Jasperlake board is working Change-Id: Ia8e88f92929fe40d7be1c28947e005cb0d862fcb Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-02-17soc/intel/tigerlake: Enable Audio on TGLSrinidhi N Kaushik
Configure UPDs to support Audio enablement. Correct the upd name in jslrvp devicetree to avoid compilation issue. BUG=b:147436144 BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-02-17src/intel: Define HFSTS3 registerSridhar Siricilla
Changes: 1. Define HFSTS3 register across SoCs(apl/cnl/icl/tgl). 2. Define cse_is_hfs3_fw_sku_custom() which checks ME's Firmware SKU is Custom or not. TEST=Verified on hatch, soraka, bobba and iclrvp. Change-Id: I4188e58a4a08d87be2d84674e00ed1407fb8bf82 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-02-17src/soc/tigerlake: Accomodate JSP specific changes in iomap.hMeera Ravindranath
Updating MCH, GSPI And I2C base addresses for JSP in iomap header. BUG=None BRANCH=None TEST=Compilation for Jasper lake board is working Change-Id: Ia8e88e02989fe80d7bd1f28942e005cb0d862fcb Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38754 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17soc/tigerlake: Add Device id for Tiger Lake Dual CoreSrinidhi N Kaushik
Add device id for Tiger Lake Dual core part. BUG=b:148965583 BRANCH=none TEST="emerge-tglrvp coreboot chromeos-bootimage", flash and boot Change-Id: Ied0cef2fcc8ae6f25949f98f886c4d79f64b54cd Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-02-17soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774Wim Vervoorn
Make sure the Skylake comment refers to the correct BWG paragraph and update the text for all. BUG=N/A TEST=build Change-Id: Id383f200e079bdb91cea2240bd7a957d723a7b89 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-17soc/intel{cnl,icl,skl,tgl}/bootblock: Make sure DMI PCR 2770 is setWim Vervoorn
DMI PCR 2770 (LPC IO DECODE RANGES) should be identical to LPC PCI offset 0x80. This is specified in PCH BWG par 2.5.1.5. Add the support to make sure this PCR is always set correctly. BUG=N/A TEST=tested on facebook monolith. Change-Id: I33ff2b96dea78b5ff1c7c9416cf74f67d79f265d Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38746 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17vboot: remove VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT optionJoel Kitching
With CL:1940398, this option is no longer needed. Recovery requests are not cleared until kernel verification stage is reached. If the FSP triggers any reboots, recovery requests will be preserved. In particular: - Manual requests will be preserved via recovery switch state, whose behaviour is modified in CB:38779. - Other recovery requests will remain in nvdata across reboot. These functions now only work after verstage has run: int vboot_check_recovery_request(void) int vboot_recovery_mode_enabled(void) int vboot_developer_mode_enabled(void) BUG=b:124141368, b:35576380 TEST=make clean && make test-abuild BRANCH=none Change-Id: I52d17a3c6730be5c04c3c0ae020368d11db6ca3c Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38780 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-15soc/tigerlake: Update xhci ACPI files for JSPMeera Ravindranath
ACPI files for xhci in JSL is different from TGL. Hence, renaming xhci.asl to xhci_tgl.asl and adding a new file xhci_jsl.asl for JSL. Also, allowing xhci.asl to choose the correct file based on the SoC selected. BUG=None BRANCH=None TEST=Compilation for JasperLake board is working Change-Id: Ia8e88e02989ff80d7cd1f28941e005cb0d842fcb Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-15soc/intel/tigerlake: Update PMC Register Base and platform check for JSPUsha P
Change: 1. PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP to 0X0A00 for JSP 2. Platform check in espi.c BUG=None TEST= 1. Test for JSL RVP Boot 2. Verify PMC register values are valid for GEN_PMCON and GBLRST_CAUSE from the coreboot console logs. Change-Id: I6017a9703764b5454e7be479c1e08afe614908f1 Signed-off-by: Usha P <usha.p@intel.com> Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38704 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-15soc/intel/tigerlake: Update Kconfig related to JSLUsha P
Update Kconfig: 1. select INTEL_CAR_NEM for SOC_INTEL_JASPERLAKE 2. Update the right value of MAX_ROOT_PORTS and MAX_PCIE_CLOCKS for SOC_INTEL_JASPERLAKE Change-Id: I4aa52c80bfd6134164a0925ea548579b3cc54a55 Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-09soc/intel/tigerlake: add memory configuration supportNick Vaccaro
Move some of the common memory code that was being performed in mainboard into the soc to reduce redundant code going forward. BUG=b:145642089 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, log into kernel and verify memory size shows 8GB. Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38606 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-09soc/intel/{cnl,icl,skl,tgl,common}: Make changes to ↵Sridhar Siricilla
send_heci_reset_req_message() Below changes have been implemented in send_heci_reset_req_message(): 1. Modify return values to align with other functions in the same file. 2. Add additional logging. 3. Replace macro definitions of reset types with ENUM. 4. Make changes to caller functions to sync with new return values. 5. Rename send_heci_reset_req_message() to cse_request_global_reset(). Test=Verified on hatch board. Change-Id: I979b169a5bb3a5d4028ef030bcef2b8eeffe86e3 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37584 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoCSridhar Siricilla
Below changes are implemented: 1. Move HFSTS1 register definition to SoC since HFSTS1 register definition is specific to a SoC. Moving structure back to SoC specific to avoid unnecessay SoC specific macros in the common code. 2. Define a set of APIs in common code since CSE operation modes and working states are same across SoCs. cse_is_hfs1_com_normal(void) cse_is_hfs1_com_secover_mei_msg(void) cse_is_hfs1_com_soft_temp_disable(void) cse_is_hfs1_cws_normal(void) 3. Modify existing code to use callbacks to get data of me_hfs1 structure. TEST=Build and Boot hatch, soraka, tglrvp, bobba and iclrvp boards. Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-04soc/intel: Add get_pmbaseEugene Myers
Originally a part of security/intel/stm. Add get_pmbase to the intel platform setup code. get_pmbase is used by the coreboot STM setup functions to ensure that the pmbase is accessable by the SMI handler during runtime. The pmbase has to be accounted for in the BIOS resource list so that the SMI handler is allowed this access. Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2 Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37990 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-01soc/intel/tigerlake: Configure TCSS xHCI and xDCIWonkyu Kim
Configure xHCI, xDCI according to board design BUG=none BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38624 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-29soc/intel/tigerlake: Disable image clocksWonkyu Kim
TGL FSP does just pin mux for image clock pins by UPD and image clocks are controlled by ACPI(camera_clock_ctl.asl) under tigerlake SOC folder. Disable image clocks by UPD for bypassing FSP pin mux and do pin mux in gpio.c according to board design. BUG=none BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I5aba5b2fb6deee231e3ec34c8dbc9972b01041f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38562 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-28soc/intel/tigerlake: Enable DP ports according to board designWonkyu Kim
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ia6e9271a11a1f9e6f98923772219ccc1e7daecda Reviewed-on: https://review.coreboot.org/c/coreboot/+/38528 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-25soc/intel/tigerlake: Add IPU in ACPIWonkyu Kim
Add IPU ACPI object for Camera ACPI. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I8c1ca9c053f0c8ef8d7c027c317c7af74d5f0f8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/38469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-01-25soc/intel/tigerlake: Configure ClkReq according to mainboard designWonkyu Kim
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from NVMe Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I14997e0a7d03bf1a97d115cbf0a7ad2603ef9953 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38285 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 07:42:16 +0000