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2019-12-31soc/intel/{icl,cnl,tgl}: Always add PM1_TMR block to FADTMeera Ravindranath
Provide the PM1_TMR information in the FADT even if PmTimerDisabled is set because PM timer emulation is enabled via MSR 121h so the timer will still work and can be used by things like Tianocore and Windows. Porting from 662b6cb3ed (soc/intel/skylake: Always add PM1_TMR block to FADT). Change-Id: Ie3d592623f3a84051477ffe83a0cf0daf30dd36f Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-20soc/intel/tigerlake: Update FSP stack and heap sizeMaulik V Vaghela
Tigerlake and Jasperlake fsp requires stack size to be minimum 192 KiB and heap size to be minimum 128 KiB. Updating both Kconfig to meet size requirements. Also updated required CAR region size during boot block due to increment in stack & heap requirement by fsp Change-Id: I38e93b5986811ff3e0a8df5f4f36af35f308cb6b Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37764 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19soc/intel/tigerlake: Add required header files in pch.cAamir Bohra
Add header files to fix build issues due to missing declaration for get_pch_series and die_with_post_code functions. Change-Id: Ie8ba4970ec1b73c1e481f54bcfbf95be87d9c442 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-12-19src/soc/intel: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: I71a5a6c3748d5a3910970bfb1ec3d7ecd3184cfd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33686 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-19src: Use '#include <smp/node.h>' when appropriateElyes HAOUAS
Change-Id: Icdd6b49751763ef0edd4c57e855cc1d042dc6d4d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-16soc/intel/tigerlake: Add FSP header and Fsp.fd file path for Jasper LakeAamir Bohra
Change-Id: I66d48206a4c1c31802e85c08ab935f81f10aadbc Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-16soc/intel/tigerlake: Pick correct pmc base reg from pch typeMaulik V Vaghela
Update PMC shadow register base address for Jasperlake Correct PCH detection logic based on PCH ids and return correct base address based on PCH detected since our code supports both tgl and jsl. Change-Id: Iea3311b3dc8dc3ee5ea54db1148f386c2a5dd563 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-12-12soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.hFurquan Shaikh
gpe0_en_* seem to have been copied over from previous generations but recent SoCs don't use it. This change gets rid of these unused members. Change-Id: I165e66aeefde4efea4484f588c774795987ca461 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-11soc/intel/tigerlake: Include soc common lpss header fileAamir Bohra
Include soc common lpss header file to resolve build error due to missing soc_lpss_controllers_list declaration. Also remove console header since it is unused. Change-Id: I2b2c82fc7592120993bc483d3061803cf75c7335 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37556 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-11soc/intel/tigerlake: add soc implementation for ETR address APIAamir Bohra
Add soc_pmc_etr_addr function definition in tigerlake SOC code. The function is declared in common soc intel pmc driver. Change-Id: Icc471b16304c72a9341abdd9797ba3f8d0d3d1bc Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37555 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-10soc/intel/common: Add Jasperlake Device IDsrkanabar
Add Jasperlake SA and PCH IDs Change-Id: I2c9ec1ee4236184b986d99250f263172c80f7117 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-12-02soc/intel/tigerlake: Change compilation based on TIGERLAKE_BASEMaulik V Vaghela
since we support JSL and TGL soc under tigerlake folder, we need to make sure all soc related files get compiled based on CONFIG_SOC_INTEL_TIGERLAKE_BASE and not only for Tigerlake. We can control soc specific file compilation through Kconfig of individual soc. Change-Id: I1a663555d0bdf7588c4e12363375e7c90629f7d9 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-11-28soc/intel/tigerlake: select correct chipset based on soc KconfigMaulik V Vaghela
Since we accomodate both Tigerlake and Jasperlake soc in single folder, we need to select IFD chipset correctly based on soc. Change-Id: I73cfe4f583da3a28c3b29d29a93ff62097130e27 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-11-27soc/intel/tigerlake: Fix smm_relocation_paramsKyösti Mälkki
Platform is not yet build-tested, this should have gone in with commit f5c0d61 intel/smm: Provide common smm_relocation_params. Change-Id: Iba667972e361d3ed463258357ab6bbde26ef1e06 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-25soc/intel/tigerlake: Add Jasperlake soc KconfigMaulik V Vaghela
Add Kconfig option for Jasperlake soc and make tigerlake as a base soc. This will allow us to differentiate between soc features. Change-Id: Id5001dc498a7d7d5c7903dc3a3762da740fc9c8e Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2019-11-25Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbolArthur Heymans
The romcc bootblock will be deprecated soon and most platforms use C_ENVIRONMENT_BOOTBLOCK already. This patch drops the CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK where needed. Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-11-22intel/smm: Provide common smm_relocation_paramsKyösti Mälkki
Pull in all copies of smm_relocation_params structs defined for intel platforms. Pull in all the inlined MSR accessors to the header file. Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-15soc/intel/{icl,tgl}: Rename pch_early_init() to pch_init()Subrata Banik
This patch renames pch_early_init() function as per review feedback CB:36550 Change-Id: I9f638e738d1a910b688cc3e51795230b2e542f82 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-11-14soc/intel/tigerlake: Include few more Tigerlake device IDsSubrata Banik
This patch performs below operations 1. Add few more MCH, ESPI and IGD IDs 2. Remove TGL-H IDs 3. Rename existing as per applicable names 4. Remove TODO from report_platform.c file 5. Include TGL IDs into report_platform.c file Change-Id: I7bb3334d0fe8ba72e394d1a63b3a73840b4eaf2f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2019-11-12soc/intel/tigerlake: Remove FSP-T option in KconfigArthur Heymans
This code lacks the temp_ram_init_params sybols so the FSP-T option so it would fail to build. Change-Id: Ie7d75943d89a964d0189f921fc433e4b9adfb0c5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner
2019-11-12soc/intel/tigerlake: Remove deprecated ↵Subrata Banik
CONFIG_SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM CB:36620 moves common cbmem_top_chipset to fsp driver hence no need to have dedicated kconfig as in SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM Change-Id: I3914993754ba409867399e903e5d13e929a92e1d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-11soc/intel/tigerlake: Fix cbmem_topArthur Heymans
EBDA support was dropped. Change-Id: I83d838b79e2653d4e3764cfc7deaca9bb241deab Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36718 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09soc/intel/tigerlake/acpi: Copy acpi directory from icelakeSubrata Banik
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Removed Descriptor Name for Memory mapped SPI flash and local APIC in northbridge.asl 2. Rearranged code in gpio.asl to move RBUF object under _CRS and made the file use ASL2.0 syntax. 3. Make use of absolute path for scs.asl 4. Remove unused smbus.asl 5. Rearranged code in nothbridge.asl to move MCRS object under _CRS, use absolute variable path and added TODO for further clean up. 6. Refer absolute variable path in scs.asl Change-Id: If967cb5904f543ce21eb6e89421df0e5673d2238 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-11-09soc/intel/tigerlake: Do initial SoC commit till ramstageSubrata Banik
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 5.c Remove dGPU over PCIE enable Kconfig option 6. Add CPU/PCH/SA EDS document number and chapter number 7. Remove unnecessary headers from .c files based on review Tiger Lake specific changes will follow in subsequent patches. 1. Include GPIO controller delta over ICL 2. FSP-S related UPD overrides as applicable Change-Id: Id95e2fa9b7a7c6b3b9233d2c438b25a6c4904bbb Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36087 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09soc/intel/tigerlake/romstage: Do initial SoC commit till romstageSubrata Banik
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Remove and clean below files 5.a Clean up upd override in fsp_params.c, will be added once FSP available. 5.b Remove __weak functions from fsp_params.c 6. Add CPU/PCH/SA EDS document number and chapter number 7. Add required headers into include/soc/ from ICL directory Change-Id: I24980c196efb2c5569996ca4fb315c256cf9de87 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36552 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-09soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblockSubrata Banik
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Add CPU/PCH/SA EDS document number and chapter number 6. Add required headers into include/soc/ from ICL directory Tiger Lake specific changes will follow in subsequent patches. 1. Add Tigerlake specific device IDs (CPU/PCH/SA) Change-Id: Id7a05f4b183028550d805f02a8078ab69862a62e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
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