| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-03-12 | soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table | John Zhao |
| 2019-11-09 | soc/intel/tigerlake: Do initial SoC commit till ramstage | Subrata Banik |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |