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path: root/src/soc/intel/tigerlake/spd
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2020-10-12util: Add DDR4 generic SPD for H5ANAG6NCJR-XNCNick Vaccaro
Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC. BUG=b:161772961 TEST=none Change-Id: I71e4de9a28f78bbf8c7de1fcafa3596276a5f2f9 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-06templates: add an empty SPD to SPD_SOURCESPaul Fagerburg
Add an empty SPD in SPD_SOURCES when creating a new variant of hatch, volteer, waddledee, or waddledoo, so that coreboot can build successfully. For variants that use spd_tools, add an empty mem_parts_used.txt so that the developer can add the supported memory parts and regenerate the Makefile.inc with the correct SPD references. Add an empty SPD for LPDDR4x for waddledee and waddledoo to use. BUG=b:169422833 TEST=create a new variant of hatch, volteer, waddledee, and waddledoo. Observe that each one succeeds. Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: I06dfb6103701bf8949180595f1e98fac48bcc585 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45746 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-28util: Add new memory part for zork boardsAmanda Huang
Add memory part H5ANAG6NDMR-XNC. Attributes are derived from data sheets. BUG=b:165611994 TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: Ifdcc7536441e9f0b94543c6f06fe466596f752dc Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-08-28soc/intel/tigerlake: add ddr4-spd-empty.hexAaron Durbin
In generating the potential spds the ddr4-spd-empty.hex was accidentally omitted. Generated from: go run util/spd_tools/ddr4/gen_spd.go src/soc/intel/tigerlake/spd/ \ util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt TGL Change-Id: Ic8b9449830fb5405ebf138ebd54f41b0f76ba584 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44908 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28util: Add memory parts needed by zork boardsRob Barnes
Add memory parts needed by zork boards. Attributes are derived from data sheets. BUG=b:162939176 TEST=Compared generated SPDs with data sheets and checked in SPDs Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I67f205f9af24bbc5c12656be1f363a15fe975955 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44447 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28util/gen_spd: translate DeviceBusWidth to die bus widthNick Vaccaro
If a memory part is a x16 part that has two dies and only a single rank, then the x16 describes the part width (since this solution will need to be a stacked solution) and as such, we must translate the DeviceBusWidth to the "die bus width" instead. Change DeviceBusWidth variable name to PackageBusWidth to be more descriptive BUG=b:166645306, b:160157545 TEST=run gen_spd and verify that spds for parts matching description above changed appropriately. Change-Id: Ia6f3ca109d344b7a015da28125a94ce10d2bdfb8 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-28util: rename lp4x spds to include "lp4x-" in nameNick Vaccaro
Change lp4x spd names to include lp4x memory type (eg. lp4x-spd-1.hex). BUG=b:160157545 TEST=run gen_part_id for volteer variants and verify that it changed spd names to prepend the "lp4x-" to the filename.. Change-Id: I0c59da7eb78f34640aad2e852ca725d3e8571a8e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44784 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28util: volteer/dedede: move generic SPDs to common locationNick Vaccaro
Now that generic SPD files have the memory type prepended to the filename, they can be stored in the same location. This CL moves the generic SPDs to the new location. Change the ddr4 gen_part_id.go and gen_spd.go tools to use "ddr4_spd_manifest.generated" instead of "spd_manifest.generated". Change the lpddr4x gen_part_id.go and gen_spd.go tools to use "lp4x_spd_manifest.generated" instead of "spd_manifest.generated". Move TGL DDR4 and LPDDR4x generic SPDs into a common location. Move JSL DDR4 and LPDDR4x generic SPDs into a common location. Change the volteer/spd/Makefile.inc to use the new path for the spds. Change the dedede/spd/Makefile.inc to use the new path for the spds. BUG=b:165854055 TEST="emerge-volteer coreboot" and verify all variants build correctly. Change-Id: I83b088cb718d15ffd3012c84a12b5231ae84a3e4 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44648 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-25util: Add spd_tools to generate DDR4 SPDs for TGL boardsNick Vaccaro
Serial Presence Detect (SPD) data for memory modules is used by Memory Reference Code (MRC) for training the memory. This SPD data is typically obtained from part vendors but has to be massaged to format it correctly as per JEDEC and MRC expectations. There have been numerous times in the past where the SPD data used is not always correct. In order to reduce the manual effort of creating SPDs and generating DRAM IDs, this change adds tools for generating SPD files for DDR4 memory used in memory down configurations on Intel Tiger Lake (TGL) based platforms. These tools generate SPDs following JESD79-4C and Jedec "4.1.2.L-5 R29 v103" specification. Two tools are provided: * gen_spd.go: Generates de-duplicated SPD files using a global memory part list provided by the mainboard in JSON format. Additionally, generates a SPD manifest file (in CSV format) with information about what memory part from the global list uses which of the generated SPD files. * gen_part_id.go: Allocates DRAM strap IDs for different DDR4 memory parts used by the board. Takes as input list of memory parts used by the board (with one memory part on each line) and the SPD manifest file generated by gen_spd.go. Generates Makefile.inc for integrating the generated SPD files in the coreboot build. BUG=b:160157545 Change-Id: I263f936b332520753a6791c8d892fc148cb6f103 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-07lp4x: Add new memory parts and generate SPDsDavid Wu
This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for TGL: 1. MT53E512M64D4NW-046 WT:E 2. MT53E1G64D8NW-046 WT:E BUG=b:159195585,b:152936481,b:156435028 TEST=build. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If69087e5e189b3e0f70e5f1afbfe3f884173d3b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-06-08spd/lp4x: Set manufacturer part name to blank (0x20)Furquan Shaikh
As per JEDEC spec, manufacturer part name should be set to blank (0x20). This change updates gen_spd.go to set bytes 329-348 as 0x20 and regenerates SPDs for TGL and JSL. Change-Id: I6af18d89afd7264cec7e54b38e95df83d55aa058 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42023 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06lp4x: Add new memory parts and generate SPDsFurquan Shaikh
This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for TGL and JSL: 1. MT53E512M32D2NP-046 WT:E 2. K4U6E3S4AA-MGCR 3. H9HCNNNCPMMLXR-NEE 4. K4UBE3D4AA-MGCR BUG=b:157862308, b:157732528 Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41989 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-06soc/intel/tigerlake: Generate LP4x SPD files using gen_spd.goFurquan Shaikh
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to generate SPD files for currently known LP4x memory parts that can be used with TGL-based mainboards. Following files are added: 1. spd-*.hex: SPD files auto-generated by gen_spd.go 2. spd_manifest.generated.txt: Manifest file auto-generated by gen_spd.go Mainboards can use the SPD files from SoC directly when creating SPD binary to add to CBFS. BUG=b:147321551,b:155239397 Change-Id: Ic3935e4f6d106cbdf496fdfa28a0991e2d238fd9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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