coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2021-01-25	soc/intel/tigerlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGD	Bora Guvendik
2020-12-14	soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage	Sridhar Siricilla
2020-10-05	soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num()	Nick Vaccaro
2020-10-05	mb, soc: change mainboard_get_dram_part_num() prototype	Nick Vaccaro
2020-09-30	soc/intel/tigerlake: Set TME upd param based on config	Pratik Prajapati
2020-09-21	soc/intel: rename get_prmrr_size	Michael Niewöhner
2020-09-08	soc/intel/tigerlake: Skip GPIO configuration from FSP	Srinidhi N Kaushik
2020-08-26	soc/intel/tigerlake: Rename pch_init() code	Alexey Buyanov
2020-08-24	soc/intel/tigerlake: Fix IPU and Vtd config	Ravi Sarawadi
2020-07-28	soc/intel/tigerlake: Simplify is-device-enabled checks	Felix Singer
2020-07-26	soc/intel/tigerlake: Disable CPU PCIe in FSP	Shaunak Saha
2020-07-26	soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platform	John Zhao
2020-07-12	soc/intel/tigerlake: Move tco_configure to bootblock	Tim Wawrzynczak
2020-07-09	mainboard/intel/tglrvp: Remove unused PrmrrSize chip config	Subrata Banik
2020-06-30	soc/intel/tigerlake: Add CpuReplacementCheck to chip options	Jamie Ryu
2020-06-22	soc/intel/tigerlake: Add CmdMirror option in chip.h	David Wu
2020-05-30	soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En	John Zhao
2020-05-18	soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En	John Zhao
2020-05-18	soc/intel/tigerlake: Add PchHdaIDispCodecDisconnect override	Eric Lai
2020-05-18	src: Remove leading blank lines from SPDX header	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-09	src/: Replace GPL boilerplate with SPDX headers	Patrick Georgi
2020-05-04	src/soc/tigerlake: Update SerialIoDebugMode UPD in FSP-M	Srinidhi N Kaushik
2020-05-01	soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understa...	Subrata Banik
2020-04-20	soc/intel/tigerlake: Update iDisp Link UPD settings	Srinidhi N Kaushik
2020-04-20	soc/intel/tigerlake: Merge the recent change from other platforms	Wonkyu Kim
2020-04-07	soc/intel/tigerlake: Allow mainboard to override DRAM part number	Marco Chen
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-04-01	soc/intel/tigerlake: Remove Jasper Lake SoC references	Aamir Bohra
2020-03-25	soc/intel/tigerlake: Configure Hyperthreading	Wonkyu Kim
2020-03-18	soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT	Brandon Breitenstein
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-16	soc/intel/tigerlake: Support ISH	li feng
2020-03-15	soc/intel/tigerlake: Update Cpu Ratio settings	Srinidhi N Kaushik
2020-03-15	soc/intel/tigerlake: Configure Vmx support using Kconfig	John Zhao
2020-03-12	soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI table	John Zhao
2020-03-12	soc/intel/tigerlake: Enable HDA through dev_enabled	Srinidhi N Kaushik
2020-03-11	soc/intel/tigerlake: Save DIMM info by available nodes	Jamie Ryu
2020-03-11	soc/intel/tigerlake: Correct FSP log interface	Ronak Kanabar
2020-03-07	soc/intel/tigerlake: Avoid NULL pointer dereference	John Zhao
2020-03-02	soc/tigerlake: Correct FSP log interface	Wonkyu Kim
2020-03-01	soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig	Subrata Banik
2020-02-27	soc/intel/tigerlake: Add display related UPD configs for Jasper Lake	Aamir Bohra
2020-02-27	soc/intel/tigerlake: Update FSP params for Jasper Lake	Maulik V Vaghela
2020-02-17	soc/intel/tigerlake: Enable Audio on TGL	Srinidhi N Kaushik
2020-02-01	soc/intel/tigerlake: Configure TCSS xHCI and xDCI	Wonkyu Kim
2020-01-29	soc/intel/tigerlake: Disable image clocks	Wonkyu Kim
2020-01-28	soc/intel/tigerlake: Enable DP ports according to board design	Wonkyu Kim
2020-01-25	soc/intel/tigerlake: Configure ClkReq according to mainboard design	Wonkyu Kim
2020-01-22	soc/intel/tigerlake: Update fsp_params for TGL	Srinidhi N Kaushik
2020-01-13	soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig	Maulik V Vaghela
2019-11-09	soc/intel/tigerlake/romstage: Do initial SoC commit till romstage	Subrata Banik