Age | Commit message (Expand) | Author |
---|---|---|
2020-02-01 | soc/intel/tigerlake: Configure TCSS xHCI and xDCI | Wonkyu Kim |
2020-01-29 | soc/intel/tigerlake: Disable image clocks | Wonkyu Kim |
2020-01-28 | soc/intel/tigerlake: Enable DP ports according to board design | Wonkyu Kim |
2020-01-25 | soc/intel/tigerlake: Configure ClkReq according to mainboard design | Wonkyu Kim |
2020-01-22 | soc/intel/tigerlake: Update fsp_params for TGL | Srinidhi N Kaushik |
2020-01-13 | soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig | Maulik V Vaghela |
2019-11-09 | soc/intel/tigerlake/romstage: Do initial SoC commit till romstage | Subrata Banik |