coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-12-14	soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage	Sridhar Siricilla
2020-10-05	soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num()	Nick Vaccaro
2020-10-05	mb, soc: change mainboard_get_dram_part_num() prototype	Nick Vaccaro
2020-08-26	soc/intel/tigerlake: Rename pch_init() code	Alexey Buyanov
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-07	soc/intel/tigerlake: Allow mainboard to override DRAM part number	Marco Chen
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-11	soc/intel/tigerlake: Save DIMM info by available nodes	Jamie Ryu
2019-11-09	soc/intel/tigerlake/romstage: Do initial SoC commit till romstage	Subrata Banik