coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-03-02	mb, soc: Add the SPD_CACHE_ENABLE	Zhuohao Lee
2021-06-10	soc/intel/tigerlake: Hook up FSP repository	Felix Singer
2021-01-25	soc/intel/tgl and tgl mb/google,intel: Use the newly added meminit block driver	Furquan Shaikh
2020-10-19	soc/intel/tigerlake: Reflow long lines	Sridhar Siricilla
2020-08-06	soc/intel/tigerlake: add common routine for DDR init	Nick Vaccaro
2020-07-26	src: Remove extra lines in license header	Elyes HAOUAS
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-29	soc/intel/tigerlake: Check SPD is not NULL before print	Eric Lai
2020-04-28	soc/intel/tigerlake: fix call to print_spd_info()	Nick Vaccaro
2020-04-25	soc/intel/tigerlake: Fix FSP SPD index for DDR4	Furquan Shaikh
2020-04-11	soc/intel/tigerlake: Disable MrcSafeConfig	Srinidhi N Kaushik
2020-04-10	soc/intel/tigerlake: Add support to initialize DDR4 Memory	Varun Joshi
2020-04-05	soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD.	Srinidhi N Kaushik
2020-04-02	soc/intel/tigerlake: Reorganize memory initialization support	Furquan Shaikh
2020-04-01	soc/intel/tigerlake: Remove Jasper Lake SoC references	Aamir Bohra