| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-04-25 | soc/intel/tigerlake: Fix FSP SPD index for DDR4 | Furquan Shaikh |
| 2020-04-11 | soc/intel/tigerlake: Disable MrcSafeConfig | Srinidhi N Kaushik |
| 2020-04-10 | soc/intel/tigerlake: Add support to initialize DDR4 Memory | Varun Joshi |
| 2020-04-05 | soc/intel/tigerlake: Replace Reserved9 usage with DisableDimmCh# UPD. | Srinidhi N Kaushik |
| 2020-04-02 | soc/intel/tigerlake: Reorganize memory initialization support | Furquan Shaikh |
| 2020-04-01 | soc/intel/tigerlake: Remove Jasper Lake SoC references | Aamir Bohra |
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |