coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-03-30	soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3	Brandon Breitenstein
2020-03-18	soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT	Brandon Breitenstein
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-15	soc/intel/tigerlake: Enable CNVi through dev_enabled	Srinidhi N Kaushik
2020-03-12	soc/intel/tigerlake: Configure L1Substates for PCH Root ports	Wonkyu Kim
2020-03-10	soc/intel/tigerlake: Enable Hybrid storage mode	Wonkyu Kim
2020-03-06	soc/intel/tigerlake: Enable CNVi Mode	Srinidhi N Kaushik
2020-03-06	soc/intel/tigerlake: Avoid NULL pointer dereference	John Zhao
2020-03-04	soc/intel/tigerlake: Update SerialIoUart settings for Tiger Lake	Srinidhi N Kaushik
2020-03-03	soc/intel/tigerlake: configure ethernet	Wonkyu Kim
2020-02-26	soc/intel/tigerlake: Integrate Legacy 8254 timer support	Subrata Banik
2020-01-24	soc/intel/tigerlake: Enable SATA	Wonkyu Kim
2020-01-22	soc/intel/tigerlake: Update fsp_params for TGL	Srinidhi N Kaushik
2020-01-13	soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig	Maulik V Vaghela