coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-06-12	soc/intel/tigerlake: Add devicetree support to change PCH VR settings	Venkata Krishna Nimmagadda
2020-06-09	soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMs	John Zhao
2020-05-28	soc/intel/tigerlake: Configure THC	Wonkyu Kim
2020-05-26	soc/intel/tigerlake: Disable VMD	Wonkyu Kim
2020-05-26	soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnable	John Zhao
2020-05-20	tigerlake: enable DPTF functionality for volteer	Sumeet R Pawnikar
2020-05-20	soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfg	Brandon Breitenstein
2020-05-12	soc/intel/tigerlake: Control SATA and DMI power optimization	Shaunak Saha
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-01	soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree	Meera Ravindranath
2020-04-20	soc/intel/tigerlake: Merge the recent change from other platforms	Wonkyu Kim
2020-04-14	soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN	Wonkyu Kim
2020-04-14	soc/intel/tigerlake: Configure RP setting	Wonkyu Kim
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-04-01	soc/intel/tigerlake: Remove Jasper Lake SoC references	Aamir Bohra
2020-01-13	soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig	Maulik V Vaghela
2019-12-11	soc/intel/tigerlake: Include soc common lpss header file	Aamir Bohra
2019-11-09	soc/intel/tigerlake: Do initial SoC commit till ramstage	Subrata Banik