coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-09-23	soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widths	Jamie Ryu
2020-09-14	soc/intel/{cnl,icl,jsl,tgl}: Clean up chip.h	Subrata Banik
2020-08-17	soc/intel/tigerlake: Allow fine grained control of S0iX states	Jes Klinke
2020-07-29	soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold	John Zhao
2020-07-26	src/soc/intel: Add include <types.h>	Elyes HAOUAS
2020-07-25	soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU	Sumeet R Pawnikar
2020-07-15	soc/intel/tigerlake: Hook up SATA Port Enable DITO UPDs	Shaunak Saha
2020-07-09	mainboard/intel/tglrvp: Remove unused PrmrrSize chip config	Subrata Banik
2020-06-30	soc/intel/tigerlake: Add CpuReplacementCheck to chip options	Jamie Ryu
2020-06-22	soc/intel/tigerlake: Add CmdMirror option in chip.h	David Wu
2020-06-22	mb/google/volteer: Override power limits with SKU-specific limits	Tim Wawrzynczak
2020-06-17	soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPD	Wonkyu Kim
2020-06-12	soc/intel/tigerlake: Add devicetree support to change PCH VR settings	Venkata Krishna Nimmagadda
2020-06-09	soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMs	John Zhao
2020-05-30	soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En	John Zhao
2020-05-26	soc/intel/tigerlake: Remove MIPI clock setting from devicetree	Srinidhi N Kaushik
2020-05-26	soc/intel/tigerlake: Delete unused configuration	Wonkyu Kim
2020-05-26	soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnable	John Zhao
2020-05-20	tigerlake: update processor power limits configuration	Sumeet R Pawnikar
2020-05-20	soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfg	Brandon Breitenstein
2020-05-18	soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1En	John Zhao
2020-05-18	soc/intel/tigerlake: Add PchHdaIDispCodecDisconnect override	Eric Lai
2020-05-12	soc/intel/tigerlake: Control SATA and DMI power optimization	Shaunak Saha
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-01	soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understa...	Subrata Banik
2020-05-01	soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree	Meera Ravindranath
2020-04-20	soc/intel/tigerlake: Update iDisp Link UPD settings	Srinidhi N Kaushik
2020-04-17	soc/intel/tigerlake: Remove eMMC/SD support	Duncan Laurie
2020-04-14	soc/intel/tigerlake: Configure RP setting	Wonkyu Kim
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-03-30	soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3	Brandon Breitenstein
2020-03-25	soc/intel/tigerlake: Configure Hyperthreading	Wonkyu Kim
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-03-15	soc/intel/tigerlake: Enable CNVi through dev_enabled	Srinidhi N Kaushik
2020-03-15	soc/intel/tigerlake: Update Cpu Ratio settings	Srinidhi N Kaushik
2020-03-12	soc/intel/tigerlake: Configure L1Substates for PCH Root ports	Wonkyu Kim
2020-03-11	soc/intel/tigerlake: Correct FSP log interface	Ronak Kanabar
2020-03-10	soc/intel/tigerlake: Enable Hybrid storage mode	Wonkyu Kim
2020-03-06	soc/intel/tigerlake: Enable CNVi Mode	Srinidhi N Kaushik
2020-03-04	src: capitalize 'PCIe'	Elyes HAOUAS
2020-03-03	soc/intel/tigerlake: Add Jasper lake GPIO support	Ronak Kanabar
2020-03-01	soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig	Subrata Banik
2020-02-27	soc/intel/tigerlake: Update FSP params for Jasper Lake	Maulik V Vaghela
2020-02-17	soc/intel/tigerlake: Enable Audio on TGL	Srinidhi N Kaushik
2020-02-01	soc/intel/tigerlake: Configure TCSS xHCI and xDCI	Wonkyu Kim
2020-01-28	soc/intel/tigerlake: Enable DP ports according to board design	Wonkyu Kim
2020-01-18	soc/intel/tigerlake: Update chip files	Ravi Sarawadi
2019-12-12	soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h	Furquan Shaikh
2019-11-09	soc/intel/tigerlake: Do initial SoC commit till ramstage	Subrata Banik