Age | Commit message (Expand) | Author |
2020-04-06 | soc/intel/tigerlake: Use SPDX for GPL-2.0-only files | Angel Pons |
2020-03-30 | soc/intel/tigerlake: Configure IOM_TYPEC_SW_CONFIGURATION_3 | Brandon Breitenstein |
2020-03-25 | soc/intel/tigerlake: Configure Hyperthreading | Wonkyu Kim |
2020-03-18 | soc: Remove copyright notices | Patrick Georgi |
2020-03-15 | soc/intel/tigerlake: Enable CNVi through dev_enabled | Srinidhi N Kaushik |
2020-03-15 | soc/intel/tigerlake: Update Cpu Ratio settings | Srinidhi N Kaushik |
2020-03-12 | soc/intel/tigerlake: Configure L1Substates for PCH Root ports | Wonkyu Kim |
2020-03-11 | soc/intel/tigerlake: Correct FSP log interface | Ronak Kanabar |
2020-03-10 | soc/intel/tigerlake: Enable Hybrid storage mode | Wonkyu Kim |
2020-03-06 | soc/intel/tigerlake: Enable CNVi Mode | Srinidhi N Kaushik |
2020-03-04 | src: capitalize 'PCIe' | Elyes HAOUAS |
2020-03-03 | soc/intel/tigerlake: Add Jasper lake GPIO support | Ronak Kanabar |
2020-03-01 | soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by Kconfig | Subrata Banik |
2020-02-27 | soc/intel/tigerlake: Update FSP params for Jasper Lake | Maulik V Vaghela |
2020-02-17 | soc/intel/tigerlake: Enable Audio on TGL | Srinidhi N Kaushik |
2020-02-01 | soc/intel/tigerlake: Configure TCSS xHCI and xDCI | Wonkyu Kim |
2020-01-28 | soc/intel/tigerlake: Enable DP ports according to board design | Wonkyu Kim |
2020-01-18 | soc/intel/tigerlake: Update chip files | Ravi Sarawadi |
2019-12-12 | soc/intel/{cnl,icl,skl,tgl}: Remove unused gpe0_en_* from chip.h | Furquan Shaikh |
2019-11-09 | soc/intel/tigerlake: Do initial SoC commit till ramstage | Subrata Banik |