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2024-03-05soc/intel: Add definition of D0 stepping for TigerLake HaloAlicja Michalska
Change-Id: Ic080ffe7912ad71c77af09d2f3d1d9b08d9ffac8 Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2022-11-26src/soc/intel: Remove unnecessary space after castsElyes Haouas
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-04soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
Also sort includes. Change-Id: I7da9c672ee230dfaebd943247639b78d675957e4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-10-25soc/intel/tigerlake: Clean up includesElyes Haouas
Change-Id: I9c75e900d05d16de830c750f074df84bb17f64dc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-04-20soc/intel: clean up dmi driver codeWonkyu Kim
1. Remove dmi.h as it's migrated as gpmr.header 2. Remove unused gpmr definitions 3. For old platforms, define DMI defintions in c code for less code changes. TEST=Build Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ib340ff1ab7fd88b1e7b3860ffec055a75e562de7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-07src: Make PCI ID define names shorterFelix Singer
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with PCI_{DID,VID}_ using the commands below, which also take care of some spacing issues. An additional clean up of pci_ids.h is done in CB:61531. Used commands: * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g' * find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g' Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-10-01soc/tigerlake: Make IO decode / enable register configurableSean Rhodes
This allows the one 32bit register to be configured in the devicetree in the same way that Skylake can be. i.e. register "lpc_ioe". Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib1a7f2707e565a5651ebe438320de9597f5742c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-08-24soc/intel/tgl: Add PCR_PSF3_T0_SHDW_PMC_REG_BASE for PCH-HJeremy Soller
Change-Id: Id5b0cfeed35d1be0dc6ca03cb0c7a2fca4277676 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-24soc/intel: Add TGL-H CPUIDJeremy Soller
Change-Id: I5a76bcbd6661648a9284d683eb360ec956a9f9a6 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56942 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-19soc/intel/common: Add TGL-H PCI IDsJeremy Soller
Add TGL-H PCI IDs from the Processor and PCH EDS docs. Reference: - Intel doc 615985 - Intel doc 575683 Change-Id: I751d0d59aff9e93e2aa92546db78775bd1e6ef22 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-04Move post_codes.h to commonlib/console/Ricardo Quesada
Move post_codes.h from include/console to commonlib/include/commonlib/console. This is because post_codes.h is needed by code from util/ (util/ code in different commit). Also, it sorts the #include statements in the files that were modified. BUG=b:172210863 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Change-Id: Ie48c4b1d01474237d007c47832613cf1d4a86ae1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56403 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-17soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h'Subrata Banik
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated cpu_ids.h file in SoC directory. Change-Id: I773114a703d62bf469aa74b128c697cc0924cc3d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-01soc/intel: Drop `bootblock_cpu_init()` functionAngel Pons
Just call `fast_spi_cache_bios_region()` directly instead. Change-Id: I99f6ed4cf1a5c49b078cfd05e357c2d4c26ade45 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50952 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-31soc/intel/*: drop incomplete and unneeded check for DMI SRLOCKMichael Niewöhner
Before enabling IO decode ranges, current code checks if the DMI SRLOCK is set to prevent inconsistencies between LPC PCI cfg registers and LPC DMI registers, when the latter are locked. DMI SRLOCK only applies to PCHs with on-package DMI, but not to PCH-H, PCH-S and others with discrete PCH packages. So this check is at least incomplete. Further, the lock gets applied by FSP and gets reset on a warm reset. Thus, there is no case where the lock would be already set at the places where the DMI registers get written currently. Drop the checks for the reasons mentioned above. Change-Id: I59554ce96bce7f7d1a4ba9b098be9e8466c68eac Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49885 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-25soc/intel/{skl,cnl,xsp,icl,tgl,ehl,adl,jsl}: use common LPC mirroringMichael Niewöhner
Drop the old, redundant code for mirroring LPC registers to DMI and make use of the new common code. Select the new Kconfig option for LPC DMI mirroring by the option SOC_INTEL_COMMON_PCH_BASE, which is selected by platforms starting with SPT, except APL and Xeon-SP. For Xeon-SP, select DMI and the new Kconfig directly. APL, even though it's younger than SPT, does not need mirroring. Test: Set LGMR address by calling `lpc_open_mmio_window` and check that both the PCI cfg and DMI LGMR register get written correctly. Tested successfully on clevo/cml-u. Change-Id: Ibd834f1474d986646bcebb754a17db97831a651f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-09soc/intel/common/dmi: Move DMI defines into DMI driver headerSrinidhi N Kaushik
Move definitions of DMI control register and Secure Register Lock (SRL) bit into common/block/dmi driver header file. BUG=b:171534504 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Iefee818f58f399d4a127662a300b6e132494bad0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48257 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-29soc/intel: Configure P2SB before other PCH controllersFurquan Shaikh
This change updates bootblock_pch_early_init() to perform P2SB configuration before any other PCH controllers are initialized. This is done because the other controllers might perform PCR settings which requires the PCR base address to be configured. As the PCR base address configuration happens during P2SB initialization, this change moves the p2sb init calls before any other PCH controller initialization. BUG=b:171534504 Change-Id: I485556be003ff5338b4e2046768fe4f6d8a619a3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47885 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-26soc/intel/tigerlake: Rename pch_init() codeAlexey Buyanov
Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=successfully built and booted TGLRVP Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com> Change-Id: Ib7450fcdc3024dfb5e375a54f9bdcdca9bc373d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-08-07soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASESubrata Banik
In 'bootblock/pch.c', clear PCI_COMMAND_MASTER (BIT 2) prior to programming PWRMBASE and enable BIT 2 after programming PWRMBASE along with PCI_COMMAND_MEMORY (BIT 1). Also perform below operations 1. Use pci_and_config16 instead of pci read and write 2. Use setbits32 instead of mmio read and write Change-Id: I7a148c718d7d2b618ad6e33d6cec11bd0bce0937 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-05{nb,soc}/intel: Use get_current_microcode_rev() for ucode versionSubrata Banik
This patch removes all redundant read microcode version implementation from SoC directory and refer from cpu/intel/microcode/microcode.c file. TEST=Able to get correct microcode version. Change-Id: Icb905b18d85f1c5b68fac6905f3c65e95bffa2da Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44175 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-25soc/intel/tigerlake: Update Tiger Lake SA IDsDerek Huang
This patch updates Tiger Lake SA DID and report platform. According to doc #613584, remove PCI_DEVICE_ID_INTEL_TGL_ID_U_1 and add below definitions of SA ID for TGL-UP4 skus: TGL-UP4(Y) (4+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2 0x9A12h TGL-UP4(Y) (2+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2 0x9A02h Change-Id: Id9d9c9ac3bf39582b0da610e6ef912031939c763 Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43061 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12soc/intel/tigerlake: Move tco_configure to bootblockTim Wawrzynczak
On ChromeOS systems with a serial-enabled BIOS and vboot writing a new firmware image to the Chrome EC, it was possible for the TCO watchdog timer to trip 2 times before tco_configure() was called in romstage. This caused an extra reboot of the system (at a rather inopportune time) and because the EC didn't perform a full reset, the system boots into recovery mode. This patch moves the call to tco_configure() for Tiger Lake from romstage to bootblock, in order to make sure the TCO watchdog timer is halted before vboot_sync_ec() runs in romstage. It should be harmless to configure the TCO device earlier in the boot flow. BUG=b:160272400 TEST=boot Volteer (to a non-recovery kernel!) with a freshly imaged EC Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iefdc2c861ab8b5fde7f736c04149be7de7b3ae0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/43313 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12soc/intel/tigerlake: Add new IGD deviceRavi Sarawadi
Add new IGD device ID for new Tigerlake SKU support. BUG=b:160394260 Branch=None TEST=build, boot and check IGD device is reported. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I1903d513b61655d0e939f80b0fd0108091fdd7e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-07-04soc/intel/tigerlake: Remove unused EHL DID from TGL SoCSubrata Banik
TEST=Able to build and boot TGLRVP. Change-Id: I7be3cb0bd63778e34c810d69e68b584691225f7a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-06soc/intel/tigerlake: Add CPU ID for TGL B0Jamie Ryu
Reference: - TGL User Guide #613584 Rev 2.2 - TGL User Guide #605534 Rev 1.0 BRANCH=none BUG=none TEST=build and boot tglrvp Change-Id: I5da80fd4ad321b1ded369c2b6c039b73fcb3773e Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41516 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-03soc/tigerlake: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS
Change-Id: I1731313798a4aadcbc17808bfe02b50bf8bd41db Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-06-02{icelake,jasperlake,skylake,tigerlake}/bootblock.c: Clean up includesElyes HAOUAS
Drop unused includes and add missing <intelblocks/systemagent.h>. Change-Id: I06c8b2bf65283c3c1fcd25fdaae298b82fc0e09c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06soc/intel/tigerlake: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I482715c166ccf5d2f3cc25118d25b07dbfd6650a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-04-01soc/intel/tigerlake: Remove Jasper Lake SoC referencesAamir Bohra
This implementation removes all JSL references from the TGL SoC code. Additionally, mainboard code changes are done to support build. BUG=b:150217037 TEST=build tglrvp and volteer Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-03-18soc: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-02-25soc/intel/common: Update Jasper Lake Device IDsMeera Ravindranath
Update Jasper Lake CPU, SA and PCH IDs. BUG=b:149185282 BRANCH=None TEST=Compilation for Jasper Lake board is working Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-02-17soc/tigerlake: Add Device id for Tiger Lake Dual CoreSrinidhi N Kaushik
Add device id for Tiger Lake Dual core part. BUG=b:148965583 BRANCH=none TEST="emerge-tglrvp coreboot chromeos-bootimage", flash and boot Change-Id: Ied0cef2fcc8ae6f25949f98f886c4d79f64b54cd Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-02-17soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774Wim Vervoorn
Make sure the Skylake comment refers to the correct BWG paragraph and update the text for all. BUG=N/A TEST=build Change-Id: Id383f200e079bdb91cea2240bd7a957d723a7b89 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-17soc/intel{cnl,icl,skl,tgl}/bootblock: Make sure DMI PCR 2770 is setWim Vervoorn
DMI PCR 2770 (LPC IO DECODE RANGES) should be identical to LPC PCI offset 0x80. This is specified in PCH BWG par 2.5.1.5. Add the support to make sure this PCR is always set correctly. BUG=N/A TEST=tested on facebook monolith. Change-Id: I33ff2b96dea78b5ff1c7c9416cf74f67d79f265d Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38746 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-15soc/intel/tigerlake: Update PMC Register Base and platform check for JSPUsha P
Change: 1. PCR_PSF3_TO_SHDW_PMC_REG_BASE_JSP to 0X0A00 for JSP 2. Platform check in espi.c BUG=None TEST= 1. Test for JSL RVP Boot 2. Verify PMC register values are valid for GEN_PMCON and GBLRST_CAUSE from the coreboot console logs. Change-Id: I6017a9703764b5454e7be479c1e08afe614908f1 Signed-off-by: Usha P <usha.p@intel.com> Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38704 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-22soc/intel/common: Add Elkhartlake Device IDsTan, Lean Sheng
Add Elkhartlake CPU, SA and PCH IDs. EHL PCH is code named as MCC. Also add a MCH ID (JSL_EHL) which is shared by both JSL and EHL SKUs. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I03f15832143bcc3095a3936c65fbc30a95e7f0f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38489 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08soc/intel/tigerlake: Fix PMC configRavi Sarawadi
Fix PMC base address for tigerlake. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Id13222eb5498a5704c11d6b4d1e83212bd8b2723 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-12-19soc/intel/tigerlake: Add required header files in pch.cAamir Bohra
Add header files to fix build issues due to missing declaration for get_pch_series and die_with_post_code functions. Change-Id: Ie8ba4970ec1b73c1e481f54bcfbf95be87d9c442 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-12-16soc/intel/tigerlake: Pick correct pmc base reg from pch typeMaulik V Vaghela
Update PMC shadow register base address for Jasperlake Correct PCH detection logic based on PCH ids and return correct base address based on PCH detected since our code supports both tgl and jsl. Change-Id: Iea3311b3dc8dc3ee5ea54db1148f386c2a5dd563 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2019-12-10soc/intel/common: Add Jasperlake Device IDsrkanabar
Add Jasperlake SA and PCH IDs Change-Id: I2c9ec1ee4236184b986d99250f263172c80f7117 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-11-15soc/intel/{icl,tgl}: Rename pch_early_init() to pch_init()Subrata Banik
This patch renames pch_early_init() function as per review feedback CB:36550 Change-Id: I9f638e738d1a910b688cc3e51795230b2e542f82 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-11-14soc/intel/tigerlake: Include few more Tigerlake device IDsSubrata Banik
This patch performs below operations 1. Add few more MCH, ESPI and IGD IDs 2. Remove TGL-H IDs 3. Rename existing as per applicable names 4. Remove TODO from report_platform.c file 5. Include TGL IDs into report_platform.c file Change-Id: I7bb3334d0fe8ba72e394d1a63b3a73840b4eaf2f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2019-11-09soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblockSubrata Banik
Clone entirely from Icelake List of changes on top off initial icelake clone 1. Replace "Icelake" with "Tigerlake" 2. Replace "icl" with "tgl" 3. Replace "icp" with "tgp" 4. Rename structure based on Icelake with Tigerlake 5. Add CPU/PCH/SA EDS document number and chapter number 6. Add required headers into include/soc/ from ICL directory Tiger Lake specific changes will follow in subsequent patches. 1. Add Tigerlake specific device IDs (CPU/PCH/SA) Change-Id: Id7a05f4b183028550d805f02a8078ab69862a62e Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-17 07:24:44 +0000