coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2020-08-05	{nb,soc}/intel: Use get_current_microcode_rev() for ucode version	Subrata Banik
2020-07-25	soc/intel/tigerlake: Update Tiger Lake SA IDs	Derek Huang
2020-07-12	soc/intel/tigerlake: Add new IGD device	Ravi Sarawadi
2020-07-04	soc/intel/tigerlake: Remove unused EHL DID from TGL SoC	Subrata Banik
2020-06-06	soc/intel/tigerlake: Add CPU ID for TGL B0	Jamie Ryu
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-04-01	soc/intel/tigerlake: Remove Jasper Lake SoC references	Aamir Bohra
2020-03-18	soc: Remove copyright notices	Patrick Georgi
2020-02-25	soc/intel/common: Update Jasper Lake Device IDs	Meera Ravindranath
2020-02-17	soc/tigerlake: Add Device id for Tiger Lake Dual Core	Srinidhi N Kaushik
2020-01-22	soc/intel/common: Add Elkhartlake Device IDs	Tan, Lean Sheng
2019-12-10	soc/intel/common: Add Jasperlake Device IDs	rkanabar
2019-11-14	soc/intel/tigerlake: Include few more Tigerlake device IDs	Subrata Banik
2019-11-09	soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblock	Subrata Banik