| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-12-31 | soc/intel/{icl,cnl,tgl}: Always add PM1_TMR block to FADT | Meera Ravindranath |
| 2019-11-09 | soc/intel/tigerlake: Do initial SoC commit till ramstage | Subrata Banik |
 |
index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |