index
:
coreboot.git
macbookair5_2
macbookpro10_1
main
master
mbp101_medisable
mbp101_medisable_1
mbp82
x230
my copy of coreboot
gitea
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
soc
/
intel
/
tigerlake
/
Makefile.inc
Age
Commit message (
Expand
)
Author
2020-11-03
soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix
Furquan Shaikh
2020-05-27
soc/intel/gma: Implement fsp_soc_get_igd_bar() in common code
Nico Huber
2020-05-22
soc/intel/tigerlake: Provide SoundWire controller properties
Duncan Laurie
2020-05-20
soc/intel/tigerlake: Move pmc_soc_set_afterg3_en to pmutil
Tim Wawrzynczak
2020-04-17
soc/intel/tigerlake: Remove eMMC/SD support
Duncan Laurie
2020-04-14
soc/intel/{icl,tgl}: Make use of print_me_fw_version() from CSE lib
Krishna Prasad Bhat
2020-04-01
soc/intel/tigerlake: Remove Jasper Lake SoC references
Aamir Bohra
2020-04-01
soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
Aamir Bohra
2020-03-20
soc/intel: Enable GPIO functions in verstage
Bora Guvendik
2020-03-03
soc/intel/tigerlake: Add Jasper lake GPIO support
Ronak Kanabar
2020-03-03
src/soc/tigerlake: Add memory configuration support for Jasper Lake
Meera Ravindranath
2020-02-09
soc/intel/tigerlake: add memory configuration support
Nick Vaccaro
2020-01-13
soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig
Maulik V Vaghela
2019-12-02
soc/intel/tigerlake: Change compilation based on TIGERLAKE_BASE
Maulik V Vaghela
2019-11-09
soc/intel/tigerlake: Do initial SoC commit till ramstage
Subrata Banik