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2018-08-13soc/intel/skylake: use unique _uidMatt Delco
There's two cases of 1 being used. This changes the eighth instance to use 8. Change-Id: I7057a4345dadcc6f8fb43093844d27007444f481 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/27603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-10drivers/i2c: Add i2c TPM support for different stagesPhilipp Deppenwiese
Change-Id: Ib0839933f8b59f0c87cdda4e5374828bd6f1099f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/23759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-08-10src: Fix typoElyes HAOUAS
Change-Id: I689c5663ef59861f79b68220abd146144f7618de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-09src/soc: Fix typoElyes HAOUAS
Change-Id: I8053d0f0863aa4d93692487f1ca802195c2d475f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-06src/soc/intel: Add AML IGD in platform reportingGaggery Tsai
This patch revises IGD naming and adds AML IGD in platform reporting. BUG=None BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage & Ensure AML IGD is shown in platform reporting. Change-Id: Id8f8379703abdaa5b14a4337a4fca04b370f3a2a Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-06soc/intel/skl: Add AML IccMax and remove unused infoGaggery Tsai
This patch adds AML IccMax for VR configuration. From doc #594883, the IccMax for Core was changed to 28A, we need this patch to accommodate the changes. Besides, removes unused sku information from sku_icc_max_mapping structure. BUG=b:110890675 BRANCH=None TEST=Remove icc_max from DT & emerge-atlas coreboot chromeos-bootimage & Tested with AML-Y and KBL-Y SKUs. Change-Id: Ic22bae162b58b06b9519f1b708be55bde5e4641e Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/27610 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-24cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSxArthur Heymans
This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures Software Developer’s Manual. The purpose is to differentiate with MSR_SMRR_PHYSx. Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-12soc/intel/skylake: add a space in printing ME FPF statusPratik Prajapati
This is cosmetic change Before: ME: Power Management Event : Clean global reset ME: Progress Phase State : Unknown phase: 0x08 state: 0x10 ME: Power Down Mitigation : NO ME: FPF status : fused After: ME: Power Management Event : Clean Moff->Mx wake ME: Progress Phase State : Unknown phase: 0x08 state: 0x10 ME: Power Down Mitigation : NO ME: FPF status : fused Change-Id: I15c02045d0f94fdb3f4a028585cad488d4ac9aa6 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/27246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-11skylake: Remove "IshEnable"li feng
Remove "IshEnable" from soc_intel_skylake_config since it's not used anymore. Enable/disable ISH by checking if ISH device is turned on or not. Refer to https://review.coreboot.org/#/c/coreboot/+/26485/. BUG=b:79244403 BRANCH=none TEST=Built. Change-Id: I4d2889af118659852431c87cb516fd19b577efc5 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-09src/soc: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: I21680354f33916b7b4d913f51a842b5d6c2ecef3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-09soc/intel/skylake: config ISH in SOC sideli feng
Config ISH in SOC side by checking if ISH device is turned on. "IshEnable" is not needed anymore since ISH device on/off will tell if ISH should be enabled or not. "IshEnable" will be removed from chip.h in separate CL. Atlas board specific ISH setting is needed, which is committed in separate CL. BUG=b:79244403 BRANCH=none TEST=Verified on Atlas board with ISH rework. ISH log showed on console. Change-Id: I3fc8648b3e6551497617ef1ebd2889245cdd31c3 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-30soc/intel/skylake: Generate ACPI RMRR tableMatt DeVillier
An ACPI RMRR table is requried for IOMMU to work properly with an iGPU (without using passthrough mode), so create one along with the DRHD DMAR table if the iGPU is present and enabled. Test: build/boot google/chell and purism/librem13v2 with kernel parameter 'intel_iommu=on' but without 'iommu=pt;' observe integrated graphics functional without corruption. Change-Id: I202fb3eb8618f99d41f3d1c5bbb83b2ec982aca4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2018-06-30arch/x86/acpi: Add DMAR RMRR helper functionsMatt DeVillier
Add DMAR RMRR table entry and helper functions, using the existing DRHD functions as a model. As the DRHD device scope (DS) functions aren't DRHD-specific, genericize them to be used with RMRR tables as well. Correct DRHD bar size to match table entry in creator function, as noted in comments from patchset below. Adapted from/supersedes https://review.coreboot.org/25445 Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27269 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28soc/intel/skylake: clear MCA before booting to OSPratik Prajapati
mca_configure needs to be called for each core before booting to OS, else OS would keep dumping MCEs Change-Id: I95ca46fda7be65d74714bdb344e339922cbb6305 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/26392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-06-28intel/common: change mca_configure API's defPratik Prajapati
add an unused param so that mca_configure can be called by mp_run_on_all_cpus to run it on all cores. Change-Id: I2395ee7fbedc829f040959b0021967f800693eeb Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/26391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-06-28soc/intel/common/block: Move p2sb common functions into block/p2sbSubrata Banik
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/p2sb. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: Ie9fd933d155b3fcd0d616b41cdf042cefe2c649a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-25intel/skylake: nhlt: Add capture config for echo ref stream for Max98373 CodecSathyanarayana Nujella
During Speaker playback, quad Channel I/V feedback data is captured from SSP0 Rx. Out of these 4-channels, Stereo V-Sense data needs to be given as echo ref stream. So, adding stereo capture config to max98373_capture_formats. BUG=b:110074225 TEST='Audio playback and Capture Stereo echo ref data' Change-Id: I6fe619ece94d5011caffe37ef10b48f956938db9 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/27182 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-22soc/intel/common/block/cpu: Add option to skip coreboot AP initSubrata Banik
SoC users from IOTG team is looking forward for a solution to skip coreboot AP initialization flow and make use of FSPS-UPD to perform AP reset. TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs out of reset. Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21soc/intel/{skl,kbl}: ensure C1E is disabled after S3 resumeCole Nelson
C1E is disabled by the kernel driver intel_idle at boot. This does not address the S3 resume case, so we lose state and C1E is enabled after S3 resume. Disable C1E for SKL and KBL. This gives a coherent state before and after S3 resume. TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3 resume with bit [1] set to zero (0x20005d). Change-Id: I1343f343bfac9b787f13c15b812c0a201dcccb38 Signed-off-by: Cole Nelson <colex.nelson@intel.com> Reviewed-on: https://review.coreboot.org/27125 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-14src: Get rid of device_tElyes HAOUAS
Use of device_t is deprecated. Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-12drivers/intel/gma: Unify VBT related Kconfig namesNico Huber
Shuffle words and drop the _DATA_FILE suffix. Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-08soc/intel/skylake: Enable low power S0Idle capabilityHaridhar Kalvala
This patch sets the ACPI FADT flag ACPI_FADT_LOW_POWER_S0 if S0ix is enabled for the platform. BUG=b:79559085 TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0 flag is set in FACP table - FADT.Flags[21] bit. Change-Id: I0b8a86118232a66e7466d5b8116eff6087b51210 Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Reviewed-on: https://review.coreboot.org/26940 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-06-07soc/intel/common/pch: Add pch lockdown codeSubrata Banik
pch lockdown functionality can be used by supported PCH. Right now pch lockdown functionality is applied for SPT (Skylake SOC) and CNP(Cannon Lake SOC) PCH. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL and CNL platform. Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
No need to provide an option to try disable this. Also remove explicit ´select RELOCATABLE_MODULES' lines from platform Kconfigs. Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-06soc/intel/common/block: Move i2c common functions into block/i2cSubrata Banik
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/i2c. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: I88f2f836eee4f80b79486dd8644d1bb3826c5af1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06soc/intel/common/block: Move gspi common functions into block/gspiSubrata Banik
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving common soc code into common/block/gspi. BUG=b:78109109 BRANCH=none TEST=Build and boot KBL/CNL/APL platform. Change-Id: I877c7c48af928ca1e0399ec794d9400bc52edfcb Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-06soc/intel/common/block: Add common chip config blockSubrata Banik
Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06soc/intel/{cannonlake, skylake}: Select Gen-6 PCH binding for SKL/CNLSubrata Banik
This patch creates a glue layer between SOC and common block IPs in terms of PCH. All common IP blocks now can be selected based on SOC_INTEL_COMMON_PCH_BASE config option. BUG=none BRANCH=b:78109109 TEST=Build and boot Cannonlake RVP and EVE. Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85d99 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-05soc/intel/skylake: Add option to skip coreboot MP initSubrata Banik
This patch provides option for mainboard to skip coreboot MP initialization if required based on use_fsp_mp_init. Option for mainboard to skip coreboot MP initialization * 0 = Make use of coreboot MP Init * 1 = Make use of FSP MP Init Default coreboot does MP initialization. Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-05soc/intel/skylake: Swap PCI devfn resides in same PCI deviceGaggery Tsai
After FSP-S, a device on PCI function n will be function swapped to function 0 if there is no device presnet on function 0. It needs some modification for DT and causes mismatches between software configuration and hardware schematic. This patch is from d779605, which swaps the devfn of the first enabled device in DT and function 0 resides in a PCI device. BUG=b:80105785 BRANCH=None TEST=Make sure the device is still enabled after coalescence with device on bus 0 and w/o device on bus 0. Test with suspend and resume and ensure it's consistent. Change-Id: Ibbc5d6e979977011f5904c8bd4b2f1be16bd23dc Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/26479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-04src/soc: Get rid of whitespace before tabElyes HAOUAS
Change-Id: Ia024fb418f02d90c38b9a35ff819c607b9ac4965 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04soc/{amd,intel}: Use postcar_frame_add_romcache()Nico Huber
Change-Id: Iee816628ac3c33633f5f45798562a4ce49493a65 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-06-04soc/intel/skylake: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: Idf00c029331aba30c8bfca71546cad62ff6bb0a7 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26541 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)Nico Huber
Boards could choose a high ROM_SIZE that would result in an MTRR config that conflicts with other resources. Thus, always use the filtered CACHE_ROM_SIZE. Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26575 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31soc/intel/skylake: Select common P2SB codeSubrata Banik
This patch select CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB to include common p2sb code block. BUG=b:78109109 BRANCH=none TEST=Build and boot EVE. Change-Id: I3f6aa6398e409a05a35766fb7aeb3aa221dd3970 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26165 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-28intel/skylake: nhlt: Update Max98373's capture formatSathyanarayana Nujella
Max98373's NHLT capture configuration is used for IV feedback for DSM algorithm. Feedback is 4-channel data. Without this configuration below error is seen in dmesg: [ 315.784250] snd_soc_skl 0000:00:1f.3: Blob NULL for id 0 type 3 dirn 1 [ 315.784263] snd_soc_skl 0000:00:1f.3: PCM: ch 4, freq 48000, fmt 32 So, update nhlt configuration accordingly. BUG=b:79362472 TEST=Audio playback works with IV feedback enabled Change-Id: I75434a63fe030ed9bb963c6d300d833a8e7d2d66 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/26384 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-22src: Remove non-ascii charactersMartin Roth
Change-Id: Iedb78e24a286a51830c85724af0179995ed553be Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/26434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-22bootblock: Allow more timestamps in bootblock_main_with_timestamp()Julius Werner
This patch adds more parameters to bootblock_main_with_timestamp() to give callers the opportunity to add additional timestamps that were recorded in the platform-specific initialization phase. Change-Id: Idf3a0fcf5aee88a33747afc69e055b95bd38750c Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/26339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-18soc/intel: Add support for USB ACPI code generationDuncan Laurie
To support generating USB devices in ACPI the platform needs to know how to determine a device name for each USB port, and for any root hubs that may be present. Recent Intel platforms route all ports to an XHCI controller through a root hub. This is supported by considering the root hub to be USB port type 0, the USB 2.0 ports to be type 2, and the USB 3.0 ports to be type 3. This was tested with a Kaby Lake platform by adding entries to the devicetree and checking the resulting SSDT. Change-Id: I527a63bdc64f9243fe57487363ee6d5f60be84ca Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/26174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-17soc/intel/skylake: Fix AP timeout issue while executing sgx_configureSubrata Banik
Increase AP timeout limit for sgx_configure function. As per debug log sgx_configure was not successful on all cores with given timeout value. TEST=Ensures no timeout error in AP function execution. Change-Id: Ia83f7a7eb6cd6c4808d55febfebe32724a633173 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@google.com>
2018-05-15soc/intel/skylake: check DPTF_TSR1_ACTIVE_AC* in _ACx methodsJohn Su
Because thermal table is not included the values of DPTF_TSR1_ACTIVE_AC from internal nami/vayne thermal team. Add conditional compilation in _ACx methods if DPTF_ENABLE_FAN_CONTROL is defined in the dptf.asl. BUG=b:72974136 TEST=Match the result. Change-Id: I4b593118ca460a59aa49786cb99df417d135112a Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/26210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-14cpu/x86: Add support to run function with argument over APsSubrata Banik
This patch ensures that user can pass a function with given argument list to execute over APs. BUG=b:74436746 BRANCH=none TEST=Able to run functions over APs with argument. Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/25725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-08soc/intel/skylake: Support PCH UART 0 and 1 for consoleDuncan Laurie
The current PCH UART support for console is limited to UART2. This change adds support for specifying UART0 or UART1 to be used instead by changing CONFIG_UART_FOR_CONSOLE in the board level Kconfig. The default is still 2. This is tested with a board that uses UART0 for debug output. Change-Id: I91323ed3298f9b2558764aa4b54173833c021a7b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/26140 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-08{mb,nb,soc}: Remove references to pci_bus_default_ops()Nico Huber
pci_bus_default_ops() is the default anyway. Change-Id: I5306d3feea3fc583171d8c865abbe0864b6d9cc6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-04soc/intel: unify VBT fetching APIPatrick Georgi
Skylake used the inner function, wrapping it in the same set of tests as the common code does, but expressed differently. Change-Id: Ifa6912255e7874a6e80301d49128adda6f624209 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/26037 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-01chromeec platforms: Update ACPI thermal event handler callMartin Roth
Currently the thermal event handler method TEVT is defined as an extern, then defined again in platforms with thermal event handling. In newer versions of IASL, this generates an error, as the method is defined in two places. Simply removing the extern causes the call to it to fail on platforms where it isn't actually defined, so add a preprocessor define where it's implemented, and only call the method on those platforms. Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25916 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-20pci: Move inline PCI functions to pci_ops.hPatrick Rudolph
Move inline function where they belong to. Fixes compilation on non x86 platforms. Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25720 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17soc/intel/skylake: check DPTF_TSR0_ACTIVE_AC* in _ACx methodsFrank Wu
Because thermal table is not included the values of DPTF_TSR0_ACTIVE_AC5 and DPTF_TSR0_ACTIVE_AC6 from internal nami/vayne thermal team. Add conditional compilation in _ACx methods if DPTF_ENABLE_FAN_CONTROL is defined in the dptf.asl. BUG=b:72974136 BRANCH=poppy TEST=emerge-nami coreboot and booted on nami board. Change-Id: I3e36ce94f714ff13f8ccee65992d7a9c7e0bb5b2 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25614 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-16soc/intel/skylake: Hook up libgfxinitNico Huber
Also base the FSP/GOP related bail-out on the correct Kconfig option to allow adding a VBT along with libgfxinit. Most things should work, what doesn't is backlight control because coreboot misses the settings (moved to FSP and need backporting). Also, Kaby Lake is still unsupported. TEST=Booted yet to be upstreamed Skylake-S port (Kontron/bSL6) both with text and linear framebuffer mode and viewed a FILO menu. Change-Id: I79fbfed7732cf02d054530ea7ec0d34de32836ba Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-04-11soc/intel: Remove superfluous pointers variablesArthur Heymans
Change-Id: I639be58df358129c1f420cf8d1540edd408859a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-10soc/intel/common: prepare for lpss clock splitAaron Durbin
Apparently Intel had decided to use different clock speeds for some of its IP blocks in some of its designs. The i2c designware driver has already been moved into common code allowing for its own Kconfig value. That currently leaves SPI (UART isn't using the clock currently). Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock speeds present in the system for the various IP blocks. BUG=b:75306520 Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25608 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-05soc/intel/skylake: Generate ACPI DMAR tableNico Huber
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the GFXVTBAR is only generated if the IGD is enabled. Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2018-04-05soc/intel/skylake: Enable VT-d and X2APICNico Huber
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX IOMMU and the general IOMMU respectively. These addresses have to be configured in MCHBAR registers (maybe, who knows, the blob is undocu- mented), advertised to FSP and reserved from the OS. The new devicetree option `ignore_vtd` allows to retain the old beha- viour (do whatever pre-set UPD values suggest). We also let FSP set up distinct BDFs for messages originating from the I/O-APIC and the HPET. Change-Id: I77f87c385736615c127143760bbd144f97986b37 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2018-03-30soc/intel/skylake: Save/restore GMA OpRegion addressMatt DeVillier
Add global/ACPI nvs variables required for IGD OpRegion. Add functions necessary to save the ACPI OpRegion table address in ASLB, and restore table address upon S3 resume. Implementation modeled on existing Baytrail code. Test: boot Windows 10 on google/chell with Tianocore payload and GOP display init, observe display driver loaded and functional, display not black screen when resuming from S3 suspend. Change-Id: Icd6b514e531eec6e49dbb03eb765144f41c1e31b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/25198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-03-30soc/intel/common/opregion: Get rid of opregion.cPatrick Rudolph
Get rid of custom opregion implementation and use drivers/intel/gma/opregion implementation instead. Test: boot Windows 10 on google/chell and google/edgar using Tianocore payload with GOP init, observe Intel graphics driver loaded and functional. Change-Id: I5f78e9030df12da5369d142dda5c59e576ebcef7 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21703 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-30soc/intel/skylake: Protect me_progress_rom_values array boundaryKane Chen
me_progress_rom_values array provides detailed information maps to ME HFSTS2 register value. There is a chance that ME status value might be over the size of me_progress_rom_values. This commit adds a check before access the array. BUG=b:77247550 Change-Id: I5de569c62b94b0595d3d3ea254f50e312e8c11a4 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/25425 Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28soc/intel/skylake: Limit xDCI feature when VBOOT is enabledDuncan Laurie
Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb and the mainboards that had defined it were adjusted accordingly. This was tested on an Eve board with xDCI enabled in devicetree.cb to ensure the xDCI device is enabled in developer mode and disabled in normal mode. Change-Id: Ic3c84beac87452f17490de32082030880834501d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28soc/intel/skylake: enable VMX supportMatt DeVillier
Use soc/common VMX block to enable VMX on supported devices. Change-Id: Iaa1a6201b431783d709c0509715fa8e8b1ce349a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/25332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2018-03-27soc/intel/skylake: Add NHLT config for max98373 codecDuncan Laurie
Add the NHLT configuration for the max98373 codec to skylake, taken directly from cannonlake. This will allow skylake/kabylake boards to use this codec. Change-Id: Ifb6bf2d31fda25b18d9b1ce2bb721255335d55e4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/25367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HARSHAPRIYA N <harshapriya.n@intel.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2018-03-27soc/intel/skylake: Do a heci_reset before reading ME firmware versionFurquan Shaikh
This change adds a call to heci_reset before attempting to read ME firmware version. This is important to ensure that both ME and BIOS are in sync. BUG=b:76167737 BRANCH=poppy TEST=Verfied that ME firmware version read does not fail on first boot after power failure (i.e. removing battery and AC power). Change-Id: Ib6b39c398d2e1177b087352a4acb8bcf5a9897d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-26soc/intel: Add KBL-S MCH and some KBL PCH supportGaggery Tsai
This patch adds the support for KBL-S MCH and Z270, H270, B250 and Q250 PCH chips. BUG=None BRANCH=None TEST=Boot with KBL-S CPU and B250/H270 PCHs. Change-Id: If03abb215f225d648505e05274e2f08ff02cebdc Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/25305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-03-26soc/skylake/cpu: Fix Intel SpeedStep enable/disableMatt DeVillier
In an attempt at consolidation, commit 0a203d1 [1] introduced an additional read/write of the MISC_ENABLE msr, as well a bug which nullified the setting of Intel SpeedStep by inserting said read/write calls in between another set of read/write calls to the same msr. Fix by reverting to previous (simpler) implementation. [1] soc/intel/skylake: Use CPU common library code https://review.coreboot.org/19566 Test: boot Linux on Librem13v2, read MISC_ENABLE msr and verify SpeedStep bit correctly set based on devicetree setting. Change-Id: Id2ac660bf8ea56d45e8c3f631a586b74106a6cc9 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/25330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-22soc/intel/skylake: Define IFD_CHIPSETFurquan Shaikh
This change defines IFD_CHIPSET as sklkbl to allow ifdtool to set the right access control bits for SKL/KBL platforms. BUG=b:76098647 BRANCH=poppy TEST=Verified that the access control bits on KBL platforms are set correctly. Change-Id: I7b2131caa06d6a975e703262931ec0ea519a86aa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25307 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-09soc/intel/skylake: Move PCR DMI programming into bootblockSubrata Banik
As per PCH BWG 2.5.16, set up LPC IO Enables PCR[DMI] + 2774h bit [15:0] to the same value program in LPC PCI offset 82h. Also this cycle decoding is only allowed to set when SRLOCK is not set. Hence move the required programming from lpc.c to pch.c. Also only enable COM port ranges if CONFIG_DRIVERS_UART_8250IO Kconfig is selected. Change-Id: Ie706735492a450baa653d8a8bb74c6e42f5150b8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-06soc/intel/skylake: Remove MCFG constantsDuncan Laurie
The MMCONF base address and length are set in Kconfig so it does not need to be redefined by the SOC as the code can just use the Kconfig variable directly. Tested on a fizz board to ensure MCFG is still created properly. Change-Id: I5fd472b1afc8264823a2b9db0f296fbfb6b1ecc0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/24975 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-06soc/intel: Fix MCFG end bus numberDuncan Laurie
The ACPI MCFG table is generated with a static end bus number of 255, which expects that the reserved range in E820 is 256MB. However the actual MCFG range is configurable with Kconfig, so these two values may not match when the OS tries to determine the range: PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) PCI: MMCONFIG 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) (size reduced!) acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge Instead of forcing the end bus number to be 255 use the Kconfig value to set it based on the current configuration. Tested on a fizz device to ensure that the kernel no longer complains: PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) Change-Id: I999ea9b72b9deba5f27dd692faa0408427a0bf89 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/24974 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-28skylake: Fix unwanted disablement of ACPI UPWEKane Chen
In PORTSC, Port Enabled/Disabled(PED) is RW1CS. When there is a USB device attached on system, current UPWE method will set 1 to PED, this will cause port disabled as it's RW1CS. This change is inspired by xhci_port_state_to_neutral in linux driver. It will mask all RO and RWS bits and set WDE and WCE. BUG=b:70777816 TEST=System won't be awakend from s3 automatically when usb devices is attached. Also system can be awakend by hotplugging usb devices under S3. Change-Id: Ifd4c2d6640fea538e0ac71d7c5e73ab529e94f42 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-28soc/intel/skylake: Add support to print ME versionFurquan Shaikh
This change adds a boot state callback to print ME version after DEV_ENABLE is complete. Information is printed only if UART_DEBUG is enabled because talking to ME to get the firmware version adds ~1 second to boot time. TEST=Verified on Soraka that ME version printed is correct. Change-Id: I360d5d7420950d5aa255df08be6d7123621b87a8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/23857 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22skylake: remove legacy devices from ACPIPatrick Georgi
Once the FADT reports that they don't exist it makes no sense to have them in ACPI's device tree. Change-Id: Ice82f0de592b6ca955148479fecc8506a7cdcddc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reported-by: dhaval.v.sharma@intel.com Reviewed-on: https://review.coreboot.org/23835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-22soc/intel/skylake: Do not set ACPI_FADT_LEGACY_DEVICESFurquan Shaikh
SKL/KBL PCH does not support legacy devices. This change removes the setting of ACPI_FADT_LEGACY_DEVICES flag in FADT for SKL/KBL. It helps Linux kernel to disable controllers required to support legacy devices only e.g. i8237 DMA controller. BUG=b:72679357 Change-Id: Ie2a85a719997157f52b0eab7254689f5a56ba05b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.corp-partner.google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-20src/soc: Fix various typosJonathan Neuschäfer
These typos were found through manual review and grep. Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/23706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-02-16soc/intel/common/block/gpio: Change group offset calculationBora Guvendik
Add group information for each gpio community and use it to calculate offset of a pad within its group. Original implementation assumed that the number of gpios in each group is same but that lead to a bug for cnl since numbers differ for each group. BUG=b:69616750 TEST=Need to test again on SKL,CNL,APL,GLK Change-Id: I02ab1d878bc83d32222be074bd2db5e23adaf580 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/22571 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-16soc/intel/skylake: Switch to common PCR ASLLijian Zhao
Using common PCR asl for skylake/kabylake platform. BUG=None TEST=None Change-Id: I99ec7c878adaea439108553c0fac9d5abe1bc248 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-02-08soc/intel/skylake: Clean up SMBIOS Table Type 17 creationSubrata Banik
* Add Memory Channel Status Enum for Channel detection. * Align > 80 characters per line. * Add hob_size == 0 check. Change-Id: I6ad99de53e280a3db431f706310e6cb22b8b3953 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-07soc/intel/skylake: Add Kabylake PCH H device ID'sV Sowmya
Add PCH,MCH,IGD,I2C,PMC,SMBUS,XCHI and UART IDs for PCH H. Change-Id: I52b38457bc727735ceb5003cbccda6d7ba3340a2 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/23382 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-06soc/intel/skylake: sort CPU_SPECIFIC_OPTIONS and drop duplicateVadim Bendebury
ACPI_NHLT happens to be selected twice. BRANCH=none BUG=none TEST=generated fizz .config does not change Change-Id: Ic525ee07015deb88fff4c15cad9dbbeada8a4479 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/23601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-06soc/intel/skylake: Add devicetree variable for PCIe HotPlugDuncan Laurie
Add a variable to fill out the FSP UPD variable for PCIe HotPlug, which allows a mainboard to enable HotPlug on individual root ports. BUG=b:72417777 TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in linux that it is identified as a HotPlug capable root port. Change-Id: I6b1f525e41909a3f81984806c4ef20239032c8d6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23511 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-02-06soc/intel/skylake: Set PsysPmax valueGaggery Tsai
According to doc #543977 Power Architecture Guide, PsysPmax is the maximum platform power. It maps to the full-scale of Psys signal. This patch adds a "psys_pmax" member in chip information which allows boards to set up maximum platform power. BUG=b:71594855 BRANCH=None TEST=Set "psys_pmax" in device tree & "USE=fw_debug emerge-fizz chromeos-mrc coreboot chromeos-bootimage" & ensure correct PsysPmax value is passed to FSP-S through UPD. Verfied on KBL-R and KBL-U SKUs. Change-Id: I44f2e2917a8eb9ce3bb69d9c15899d4c7c5b2883 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-02-05soc/intel/skylake: Set PsysPl3 and Pl4Shelley Chen
If given a value for PsysPl3 and/or Pl4, set the appropriate MSR. BUG=b:71594855 BRANCH=None TEST=boot up and check MSRs in OS to make sure values are set as expected. Test on Fizz, which will set these values in mainboard. Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/23527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
2018-01-31soc/intel/skylake: Always add PM1_TMR block to FADTDuncan Laurie
Provide the PM1_TMR information in the FADT even if PmTimerDisabled is set because PM timer emulation is enabled via MSR 121h so the timer will still work and can be used by things like Tianocore and Windows. Change-Id: I78e435c34dd4e6241d345c4d07470621ea051fb8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-01-31soc/intel/skylake: Fix common timer frequencyDuncan Laurie
The calculation to set up the PM timer emulation is using an incorrect common timer clock value that was copied from Apollolake. According to the PDG Skylake and Kabylake clocks are derived from a 24MHz XTAL, not 19.2MHz like Apollolake. Fixing this value results in the proper "correction value" to be programmed into the PM timer emulation MSR that matches the raw value that would be programmed by FSP. (if it were doing MpInit) Old PM timer correction value: 0x2fba2e25 New PM timer correction value: 0x262e8b51 Change-Id: Ib2bb3cb1938ae34cfa7aef177bef6fc24da73335 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/23509 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-31drivers/intel/fsp2_0: Unbind UDK2015 Kconfig from FSP2.0 driverSubrata Banik
Now SOC code can select the require UDK support package for any platform going forward with FSP2.0 model. Change-Id: Ie6d1b9133892c59210a659ef0ad4b59ebf9f1e45 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-30soc/intel/skylake: Add support for mode-aware DPTFFurquan Shaikh
This change adds support for: 1. Handling thermal trip points change event handler based on device mode. 2. Returning thermal trip point temperatures based on the device mode. BUG=b:72554519 Change-Id: Ife48af76ceb7a39abd1fac8ef1f77db7e65ab43e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-01-29intel: Prepare registers so Windows drivers are happierPatrick Georgi
Change-Id: I12ebed30de4df9814ccb62341c7715fc62c7f5b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/23431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-01-25drivers/i2c/designware: reduce API complication for bus configAaron Durbin
Right now dw_i2c_get_soc_cfg() is expecting the SoC to implement that callback for obtaining the bus config. However, we're currently forcing another parameter of struct device so one can do the lookup. This works for Intel-based systems since the struct device was needed to program the BAR, etc. However, from an API standpoint, it just complicates matters by needing to obtain the struct device. The SoC already has knowlege of its own devices so it can get the config itself by bus number. Therefore, remove that contraint from the API. BUG=b:70232394 Change-Id: Id8558f5deedda0963a46a532a7bf984e168fb270 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23420 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-25soc/intel/skylake: Clean up the skylake PCH H device ID macrosV Sowmya
Rename the device ID macros as per the skylake PCH H external design specification. Change-Id: I4e80d41380dc1973d02bc69ac32aad5c4741a976 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/23381 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25soc/intel/skylake: Send correct ddr_type to SMBIOS TableBarnali Sarkar
The FSP 2.0 Memory_Info_HOB for KBL is not sending "MemoryType" value as what is required for SMBIOS Table according to SMBIOS Spec. Thus, converting the value retrieved from FSP HOB to the correct value. This change will not be required for upcoming SOCs since FSP have fixed this issue in its next platforms and thus it will take care and send the correct value in "MemoryType" field based on SMBIOS spec. Thus this conversion from coreboot will not be required in the next platfoms. "MemoryType" value can be directly passed to dimm_info_fill() function. BUG=none BRANCH=none TEST=Tested in Soraka, and getting the value as 0x1D for LPDDR3 memory. dmidecode (latest version 3.1) Command Type 17 will also show correct information. Currently, it was showing "Unknown". Change-Id: I75d6cca464680a88bf836e25bf5440a9cdbc738e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/23384 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-24drivers/i2c/designware: namespace soc functionsAaron Durbin
Rename the following functions to ensure it's clear that the designware i2c host controller driver is the one that these functions are associated with: i2c_get_soc_cfg() -> dw_i2c_get_soc_cfg() i2c_get_soc_early_base() -> dw_i2c_get_soc_early_base() i2c_soc_devfn_to_bus() -> dw_i2c_soc_devfn_to_bus() i2c_soc_bus_to_devfn() -> dw_i2c_soc_bus_to_devfn() BUG=b:72121803 Change-Id: Idb7633b45a0bb7cb7433ef5f6b154e28474a7b6d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23371 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-17soc/intel/common: Add option to pass SoC IO resourceSubrata Banik
This patch ensures common block has option to reserve IO resources based on SOC requirements. Also add pch_lpc_ prefix to maintain same function nomenclature across all intel common block. Change-Id: Ic00af688104bcea1aff06be6cbb20208a60e5f1d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-17soc/intel/cannonlake: Add option to select FSP_CARSubrata Banik
This patch provides an option for non-chrome devices to make use of FSP-T for performing cache-as-ram initialization. Majority of IOTG users are using FSP-T for CAR implementation and aren't able to select FSP_CAR Kconfig from SoC without conflicting with existing CAR config. TEST=Ensure that both the Chrome platform and non Chrome OS platform can select either CAR implementation based on Kconfig options FSP_CAR or CAR_NEM_ENHANCED. By default Chrome platform choose CAR_NEM_ENHANCED Kconfig and non Chrome platforms choose FSP_CAR by default. Change-Id: If565b649fe1c2abdbcf0a740c15db7253c084ae7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-12soc/intel/skylake: Override KBL IccMax settingsGaggery Tsai
According to Intel document #559100 KBL EDS v2.8, section 7.2 DC specifications, the IccMax setting for KBL-U, KBL-U42 and Celeron/Pentium are different. This patch overrides the IccMax settings for KBL-U/R/Y since device tree could not handle all KBL-U/R combinations when multiple SKUs are adopted in a project. Besides, it is inefficient to maintain the same code for all variants. Hence, place it in the common code so that all variants could leverage the benefits. +----------------+-------------+---------------+------+-----+ | Domain/Setting | SA | IA | GTUS | GTS | +----------------+-------------+---------------+------+-----+ | IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A | | | 4.5A(Others)| 29A(Celeron) | | | | | | 32A(i3/i5) | | | +----------------+-------------+---------------+------+-----+ | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | +----------------+-------------+---------------+------+-----+ BUG=b:71369428 BRANCH=None TEST=Remove icc_max setting from devicetree & emerge-fizz coreboot chromeos-bootimage & Ensure the KBL-U42, KBL-U22 and Celeron SKUs are identified correctly and IccMax settings are passed to FSPS correctly. Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/23060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-02soc/intel/skylake: Add device setting for sata power optimizationKane Chen
This change provides option in devicetree and feeds the option to FSP SataPwrOptEnable UPD for power saving purpose BUG=b:70491485 Change-Id: I9099c5c97765a118bdee64da303cb3ba6ceb951b Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/23018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-23soc/intel/{apollolake, cannonlake, common, skylake}: Add _soc_ prefix in ↵Subrata Banik
weak function This patch ensures all soc function name is having _soc_ prefix in it. TEST=Able to compile SMM common code for all supported SOC. Change-Id: Iab1b2f51eaad87906e35dbb9e90272590974e145 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-22soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion supportDivya Chellap
New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source number of PCIe root ports. This UPD array is set to clock source number(0-6) for all the enabled PCIe root ports, invalid(0x1F) is set for disabled PCIe root ports. BUG=b:70252901 BRANCH=None TEST= Perform the following 1. Build and boot soraka 2. Verify PCIe devices list using lspci command 3. Perform Basic Assurance Test(BAT) on soraka Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Signed-off-by: Divya Chellap <divya.chellappa@intel.com> Reviewed-on: https://review.coreboot.org/22947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-22ic2/designware: Move Intel i2c logic to shared driverChris Ching
BUG=b:70232394 BRANCH=none TEST=emerge-reef coreboot emerge-glados Change-Id: Idb453a4d2411163e6b4a8422310bf272eac5d379 Signed-off-by: Chris Ching <chingcodes@chromium.org> Reviewed-on: https://review.coreboot.org/22822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-22soc/intel/skylake: Make use of common SMM code for SKLSubrata Banik
This patch ensures skylake soc is using common SMM code from intel common block. TEST=Build and boot soraka/eve Change-Id: I8163dc7e18bb417e8c18a12628988959c128b3df Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/22826 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-21soc/intel/skylake: Move Enable power button SMI code from smi.c to pmc.cSubrata Banik
Original commit hash aeb2d64c85ca2c3a77f50d57e3a92f6fc0a5c2d3 (soc/intel/skylake: Enable power button SMI when jumping to payload) Change-Id: Ia4fe2694006baf24ed475c85aaffa6a0d2a6031d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22868 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-21soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDSSubrata Banik
TEST=KBL_RVP is able to power on after reconnecting power supply. Change-Id: Ic707164a576ffb25418eb6553843cd8edc608800 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-16soc/intel/common/fast_spi: implement spi_flash_ctrlr_protect_region()Aaron Durbin
In the fast spi support implement the callback for flash_protect(). This removes the need for having SOC_INTEL_COMMON_SPI_FLASH_PROTECT Kconfig option as well spi_flash_get_fpr_info() and separate spi_flash.[ch]. BUG=b:69614064 Change-Id: Iaf3b599a13a756262d3f36bae60de4f7fd00e7dc Signed-off-by: Aaron Durbn <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 21:55:09 +0000