| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-07-21 | Skylake: Initialize GPIOs for UART2 | rsatapat |
| 2015-07-21 | Skylake: Only support UART2 as debug port, clean up the rest | Naveen Krishna Chatradhi |
| 2015-07-21 | intel fsp: remove CHIPSET_RESERVED_MEM_BYTES | Aaron Durbin |
| 2015-07-21 | skylake: re-enable PCIe L1 sub states | Aaron Durbin |
| 2015-07-21 | skylake: honor pcie root port settings already in chip.h | Aaron Durbin |
| 2015-07-21 | skylake: Show SPI controller if enabled in devicetree.cb | Duncan Laurie |
| 2015-07-17 | soc/intel: Remove microcode terminators | Stefan Reinauer |
| 2015-07-17 | skylake: remove whitespace from ASL files | Stefan Reinauer |
| 2015-07-16 | soc/intel: Add Skylake SOC support | Lee Leahy |
| 2015-07-16 | soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC | Lee Leahy |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |