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2017-09-22soc/intel/skylake: Calculate soc reserved memory sizeSubrata Banik
This patch implements soc override function to calculate reserve memory size (PRMRR, TraceHub, PTT etc). System memory should reserve those memory ranges. BRANCH=none BUG=b:63974384 TEST=Ensures DRAM based resource allocation has taken care of intel soc reserved ranges. Change-Id: I19583f7d18ca11c3a58eb61c927e5c3c3b65d2ec Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21540 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-22soc/intel/skylake: Use EBDA area to store cbmem_top addressSubrata Banik
This patch uses BIOS EBDA area to store relevent details like cbmem top during romstage after MRC init is done. Also provide provision to use the same EBDA data across various stages without reexecuting memory map algorithm. BRANCH=none BUG=b:63974384 TEST=Ensures HW based memmap algorithm is executing once in romstage and store required data into EBDA for other stage to avoid redundant calculation and get cbmem_top start from EBDA area. Change-Id: Ib1a674efa5ab3a4fc076fc93236edd911d28b398 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22soc/intel/skylake: Refactor memory layout calculationSubrata Banik
This patch split entire memory layout calculation into two parts. 1. Generic memory layout 2. SoC specific reserve memory layout. usable memory start = TOLUD - Generic memory size - - soc specific reserve memory size. Change-Id: I510d286ce5e0d8509ec31a65e971d5f19450364f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-22soc/intel/skylake: add Kabylake Celeron base SKUGaggery Tsai
This patch adds the support for Kabylake Celeron base SKU with PCH ID 0x9d50. BRANCH=none BUG=b:65709679 TEST=Ensure coreboot could recognize the Kabylake Celeron base SKU and boot into OS. Change-Id: I9c6f7bf643e0dbeb132fb677fcff461244101a55 Signed-off-by: Tsai, Gaggery <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/21617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Wu <david_wu@quantatw.com> Reviewed-by: T.H. Lin <T.H_Lin@quantatw.com>
2017-09-21soc/intel/skylake: Add config for enabling LTR for PCIe Root portRizwan Qureshi
There are a lot errors reported by AER driver for root port 0. The erors are being caused by an unsupported request from the device to the upstream port. Enabling LTR on the root port stops these errors, it is because LTR is enabled on the device side but not on the root port and hence root port was logging the LTR messages from the device as unsupported. The PCIe base spec (v3.1a) section 6.18 also states that: LTR support is discovered and enabled through reporting and control registers described in Chapter 7. Software must not enable LTR in an Endpoint unless the Root Complex and all intermediate Switches indicate support for LTR. Note that it is not required that all Endpoints support LTR to permit enabling LTR in those Endpoints that do support it. When enabling the LTR mechanism in a hierarchy, devices closest to the Root Port must be enabled first. If an LTR Message is received at a Downstream Port that does not support LTR or if LTR is not enabled, the Message must be treated as an Unsupported Request. FSP has a UPD for enabling/disabling LTR on root port, use the same for configuring LTR on PCIe root ports. BUG=b:65570878 TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported by AER driver for root port 0. Change-Id: Ica97faa78fcd991dad63ae54d2ada82194b4202a Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-20vboot: reset vbnv in cmos when cmos failure occursAaron Durbin
There's an occasional issue on machines which use CMOS for their vbnv storage. The machine that just powers up from complete G3 would have had their RTC rail not held up. The contents of vbnv in CMOS could pass the crc8 though the values could be bad. In order to fix this introduce two functions: 1. vbnv_init_cmos() 2. vbnv_cmos_failed() At the start of vboot the CMOS is queried for failure. If there is a failure indicated then the vbnv data is restored from flash backup or reset to known values when there is no flash backup. BUG=b:63054105 Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-20soc/intel/skylake: refactor rtc failure checkingAaron Durbin
In order to prepare for checking RTC failure in the early boot paths move the rtc failure calculation to pmutil.c and add a helper function to determine if failure occurred. BUG=b:63054105 Change-Id: I88bf9bdba8c1f3a11bc8301869e3da9f033ec381 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21554 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-20vboot: remove init_vbnv_cmos()Aaron Durbin
Instead of having each potential caller deal with the differences of cmos_init() and init_vbnv_cmos() when VBOOT is enabled put the correct logic within the callee, cmos_init(), for handling the vbnv in CMOS. The internal __cmos_init() routine returns when the CMOS area was cleared. BUG=b:63054105 Change-Id: Ia124bcd61d3ac03e899a4ecf3645fc4b7a558f03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21549 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-15soc/intel/skylake: Move UNCORE PRMRR base and mask defines.Pratik Prajapati
UNCORE PRMRR BASE and MASK MSRs are not common, so move to SOC specific header file and rename the #define to start with MSR_* Change-Id: I799c43f0b7a9eec5b3b69ab0f5100935c7f3f170 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-15soc/intel/common/sgx: Define and use soc_fill_sgx_param()Pratik Prajapati
To remove chip.h dependency from SGX common code - Create API soc_fill_sgx_param() and use it in sgx.c - Implement same API for skylake/kabylake - define sgx_param structure Also include intelblocks/sgx.h instead of soc/msr.h Change-Id: I358f0817bec5dd6cd147a645675b5688969a04e0 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14soc/intel/skylake: Implement UNCORE PRMRR get base and mask APIPratik Prajapati
Implement soc_get_uncore_prmmr_base_and_mask() API for SKL/KBL Change-Id: I880d3d88138809cdf030507877079cbea52a0d97 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21245 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-14device: acpi_name() should take a const struct deviceAaron Durbin
There's no reason to mutate the struct device when determining the ACPI name for a device. Adjust the function pointer signature and the respective implementations to use const struct device. Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-11soc/intel/skylake: Fix SPI WP disable status checkRavi Sarawadi
Use SPI write protect disable bit from BIOS_CONTROL register to check write protect status. Change-Id: Ie79fb4e3e92a4ae777c5d501abbb44a732a9862a Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/21449 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-11cpu/x86/mp_init: remove adjust_cpu_apic_entry()Aaron Durbin
The original purpose of adjust_cpu_apic_entry() was to set up an APIC map. That map was effectively only used for mapping *default* APIC id to CPU number in the SMM handler. The normal AP startup path didn't need this mapping because it was whoever won the race got the next cpu number. Instead of statically calculating (and wrong) just initialize the default APIC id map when the APs come online. Once the APs are online the SMM handler is loaded and the mapping is utilized. Change-Id: Idff3b8cfc17aef0729d3193b4499116a013b7930 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21452 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-08soc/intel/skylake: Create acpi_get_sleep_type() to get previous sleep stateSubrata Banik
This patch implements soc function to get previous sleep state using chipset_power_state global structure. acpi_get_sleep_type is needed in PRE_RAM stage when soc selects CONFIG_EARLY_EBDA_INIT kconfig option. Change-Id: I79acbfc09c8d255fbf9d73e49e8c7764f3f3fac6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-06soc/intel/skylake: Add config for enabling PCIe AERRizwan Qureshi
Add a config for enabling/disabling Advanced Error Reporting feature for PCIe root ports. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: Ieb74c3566ded2276e549c98f78813c4f5d4d310a Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-06soc/intel/{cannonlake,skylake}: Fix null pointer dereference in klocworkSubrata Banik
This patch fixes klocwork bug due to recent memmap.c implementation where “Pointer 'dev' returned from call to function 'dev_find_slot' at line 144 may be NULL.” Change-Id: I4c74ca410d1a0ba48634ec9928a0d9d1cc20e27a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-05intel/skylake: nhlt: Add capture configuration format for IV feedback from ↵Harsha Priya
max98927 This changelist adds the capture format to be set for max98927. The nhlt blob is the same but the format params for capture are different from the render. BUG=b:36724448 TEST=IV feedback data is of good quality Change-Id: I135cf4479e89cd2046ff46027f94c0f71aed650e Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/21340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-04Kconfig: Move and rename ADD_VBT_DATA_FILEPatrick Rudolph
Move ADD_VBT_DATA_FILE to "Devices" menu and rename it to INTEL_GMA_ADD_VBT_DATA_FILE. Depend on Intel platforms to avoid confusing users of non-Intel platforms. The Intel GMA driver will use the vbt.bin, if present, to fill the ACPI OpRegion. Change-Id: I688bac339c32e9c856642a0f4bd5929beef06409 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-02soc/intel/skylake: Use common mca_configure() APIPratik Prajapati
Use mca_configure() API from cpulib to configure Intel Machine Check Architecture (MCA) Change-Id: Ia96cb82fff3def46dbecb09dee94de86f179abe6 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-01soc/intel/skylake: Use SA library to get smm region informationSubrata Banik
This patch uses system agent common library to know tseg region start and size. Unable to remove smm_region() function from soc code as SMM common library is not yet available for skylake use. BRANCH=none BUG=b:63974384 TEST=Build and boot eve successfully. Change-Id: If98b65805753db2c30d6fea29e401a17cef39799 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-30soc/intel/{cannonlake,skylake}: Add active default value for UART_FOR_CONSOLESubrata Banik
This patch to avoid build bot hang issue due to no active default value for UART_FOR_CONSOLE kconfig option. Change-Id: I70ca5dc6c4bde6a119ad59d8c58955c96c042198 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21287 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-28soc/intel/skylake: Fix FSP1.1 booting issue with HW based dram top calculationSubrata Banik
This patch ensures skylake device using FSP1.1 can use HW based DRAM top calculation which was broken due to skylake fsp1.1 not honoring any UPD to know PRMMR size and default reserving 1MB for PRMRR size. This WA is not needed for FSP2.0 implementation due to PrmrrSize UPD is available and considering into hw based dram top calculation. BRANCH=none BUG=b:63974384 TEST=Build and boot lars which is using skylake 1.1 fsp. Change-Id: Iade0d2cb2a290fc4c9f0e6b1eaadc8afff2fa581 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-08-26soc/intel/skylake: Move SPI lock down config after resource allocationBarnali Sarkar
This patch to ensures that coreboot is performing SPI registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence SPI lock down programming has been moved right after pci resource allocation is donei, so that SPI registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure SPIBAR+HSFSTS(0x04) register FLOCKDN bit and WRSDIS bit is set. Also, Bits 8-12 of SPIBAR+DLOCK(0x0C) register is set. Change-Id: I8f5a952656e51d3bf365917b90d3056b46f899c5 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/21064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-26soc/intel/skylake: Move DMI lock down config after resource allocationSubrata Banik
This patch to ensures that coreboot is performing DMI registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence BIOS Interface lock down through Sideband access has been moved right after pci resource allocation is done, so that BILD lock down is getting executed along with LPC and SPI BIOS interface lockdown settings before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure DMI register offset 0x274c bit 0 is set. Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/skylake: Remove TCO lock down programmingSubrata Banik
FSP is doing TCO lock inside Post PCI bus enumeration NotifyPhase(). Hence remove TCO Lock down programming from coreboot. TEST= Ensure TCO_LOCK offset 8 bit 12 is set. Change-Id: Iec9e3075df01862f8558b303a458126c68202bff Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/skylake: Move PMC lock down config after resource allocationSubrata Banik
This patch to ensures that coreboot is performing PMC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence PMC register lock down has been moved right after pci resource allocation is done, so that PMC registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure PMC MMIO register 0xC4 bit 31 is set. Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/skylake: Remove ABASE lock down programmingSubrata Banik
FSP is doing PMC ABASE lock inside Post PCI bus enumeration NotifyPhase(). Hence remove ABASE Lock down programming from coreboot. TEST= Ensure GEN_PMCON_B offset 0xA4 bit 17, 18 is set. Change-Id: I800e654c7d8dc55cc0e8299501c1f85c57882e9d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/skylake: Move LPC lock down config after resource allocationSubrata Banik
This patch to ensures that coreboot is performing LPC registers lockdown after PCI enumeration is done. This requirements are intended to support platform security guideline where all required chipset registers are expected to be in lock down stage before launching any 3rd party code as in option rom etc. coreboot has to change its execution order to meet those requirements. Hence lpc register lock down has been moved right after pci resource allocation is done, so that lpc registers can be lock down before calling post pci enumeration FSP NotifyPhase() API which is targeted to be done in BS_DEV_ENABLE-BS_ON_ENTRY. TEST=Ensure LPC register 0xDC bit 1 and 7 is set. Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25soc/intel/skylake: Add LPC and SPI lock down config optionSubrata Banik
This patch to provide new config options to perform LPC and SPI lock down either by FSP or coreboot. Remove EISS bit programming as well. TEST=Build and boot Eve and Poppy. Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-23soc/intel/skylake: Usable dram top calculation based on HW registersSubrata Banik
This patch ensures that entire system memory calculation is done based on host bridge registers. BRANCH=none BUG=b:63974384 TEST=Build and boot eve and poppy successfully with below configurations 1. Booting to OS with no UPD change 2. Enable ProbelessTrace UPD and boot to OS. 3. Enable PRMRR with size 1MB and boot to OS. 4. Enable PRMRR with size 32MB and boot to OS. 5. Enable PRMRR with size 2MB and unable to boot to OS due to unsupported PRMRR size. Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/21150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-22soc/intel/skylake: Lock sideband access in coreboot and not in FSPBarnali Sarkar
The Sideband Acces locking code is skipped from FSP by setting an FSP-S UPD called PchSbAccessUnlock. This locking is being done in coreboot during finalize.c. This is done because coreboot was failing to disable HECI1 device using Sideband interface during finalize.c if FSP already locks the Sideband access mechanism before that. So, as a solution, coreboot passes an UPD to skip the locking in FSP, and in finalize.c, after disabling HECI, it removes the Sideband access. BUG=b:63877089 BRANCH=none TEST=Build and boot poppy to check lspci not showing Intel ME controller in the PCI device list. Change-Id: I8dba4c97480200507969b0f2873337f97bd2ff6a Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-21soc/intel/skylake: Fix SGX init sequencePratik Prajapati
Configure core PRMRR first on all the cores and then follow the SGX init sequence. Second microcode load would run the MCHECK. To pass MCHECK, PRMRR on all cores needs to be configured first. Hence, PRMRR configuration would be called from soc_core_init while MP init for each core and then from soc_init_cpus, BSP would call sgx_configure for each core (including for itself). This code flow satisfies the MCHECK passing pre-conditions; and apparently this patch fixes the behavior of calling configure_sgx() “again” for BSP. (So removed the TODO comment also). Change-Id: I88f330eb9757cdc3dbfc7609729c6ceb7d58a0e1 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21007 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-21intel/common/mp_init: Refactor MP Init code to get rid of microcode paramPratik Prajapati
Remove passing microcode patch pointer as param while calling - soc_core_init() - soc_init_cpus() Also change callbacks in apollolake/geminilake and skylake/kabylake common code to reflect the same function signature. Change-Id: Ib03bb4a3063d243d97b132e0dc288ef3868a5a7b Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21010 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-21intel/common/sgx: Use intel_mp_current_microcode() to get microcode pointerPratik Prajapati
Get microcode patch pointer from intel_mp_current_microcode() api of mp_init and change sgx_configure function signature to drop microcode_patch param. Change-Id: I9196c30ec7ea52d7184a96b33835def197e2c799 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21009 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-21soc/intel/skylake: Add support for all UART port indexSubrata Banik
Select LPSS UART Base address based on LPSS UART port index. Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21soc/intel/skylake: Add Kconfig option to select UART indexSubrata Banik
Skylake/Kabylake SOC has two possible ways to make serial console functional. 1. Legacy IO based access using Port 0x3F8. 2. LPSS UART PCI based access. This patch to provide option to select index for LPSS UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 PCI based LPSS UART2 is by default enabled for Chrome Design. Change-Id: I9647820fe59b5d1a1001a611b9ae3580946da0ae Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-19soc/intel/skylake: Enable power button SMI when jumping to payloadFurquan Shaikh
Instead of enabling power button SMI unconditionally, add a boot state handler to enable power button SMI just before jumping to payload. This ensures that: 1. We do not respond to power button SMI until we know that coreboot is done. 2. On resume, there is no need to enable power button SMI. This avoids any power button presses during resume path from triggering a shutdown. BUG=b:64811381 Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-08-18include/device: Split i2c.h into threeNico Huber
Split `i2c.h` into three pieces to ease reuse of the generic defi- nitions. No code is changed. * `i2c.h` - keeps the generic definitions * `i2c_simple.h` - holds the current, limited to one controller driver per board, devicetree independent I2C interface * `i2c_bus.h` - will become the devicetree compatible interface for native I2C (e.g. non-SMBus) controllers Change-Id: I382d45c70f9314588663e1284f264f877469c74d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-17soc/intel/skylake: Configure FSP to skip ME MBP stepDuncan Laurie
We do not need or use the Management Engine MBP HOB so that step can be skipped when FSP initializes the ME. BUG=b:64479422 TEST=boot with FSP debug enabled binary and ensure that the output indicates this step is being skipped: Skipping MBP data due to SkipMbpHob set! Change-Id: I5ea22ec4b8b47fa17b1cf2bf562337bfaad5ec0d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/20951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-08-16soc/intel/skylake: Add proper support to enable UART2 in 16550 modeSubrata Banik
Need to perform a dummy read in order to activate LPSS UART's 16550 8-bit compatibility mode. TEST=Able to get serial log in both 32 bit and 8 bit mode through LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and CONFIG_DRIVERS_UART_8250MEM selection. Change-Id: I5f23fef4522743efd49167afb04d56032e16e417 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-15soc/intel/{cannonlake,skylake}: fix PCH_P2SB_EPMASK macroAaron Durbin
The PCH_P2SB_EPMASK macro takes a parameter. Ensure parenthesis are put around the parameter expansion. Change-Id: I978e9397036ea3630434982fe4ecd698877fe0d6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-10soc/intel/skylake: Enable UART debug controller on S3 resumeFurquan Shaikh
1. Add a new variable to GNVS to store information during S3 suspend whether UART debug port controller is enabled. 2. On resume, read stored GNVS variable to decide if UART debug port controller needs to be initialized. 3. Provide helpers functions required by intel/common UART driver for enabling controller on S3 resume. BUG=b:64030366 TEST=Verified behavior with different combinations: 1. Serial console enabled in coreboot: No change in behavior. 2. Serial console enabled only in kernel: coreboot initializes debug controller on S3 resume. 3. Serial console not enabled in coreboot and kernel: coreboot skips initialization of debug controller on S3 resume. Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20886 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-10soc/intel/common/uart: Refactor uart_common_initFurquan Shaikh
1. Create a new function uart_lpss_init which takes the UART LPSS controller out of reset and initializes and enables clock. 2. Instead of passing in m/n clock divider values as parameters to uart_common_init, introduce Kconfig variables so that uart_lpss_init can use the values directly without having to query the SoC. BUG=b:64030366 TEST=Verified that UART still works on APL and KBL boards. Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-08soc/intel: Remove ACPI notification for fan speed changeSumeet Pawnikar
In _FSL ACPI notification 0x83 was incorrectly being sent to DPTF. When there should be no notification on fan speed change. Change-Id: I66efa7a7feb911a458829a54dbd0afefabd42394 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/20875 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-08soc/intel/skylake: Log wakes caused by PME on internal bus and PCIE RPNaresh G Solanki
Internal PME is detected when bit PME_B0_STS is set. Following devices causes internal PME. - Integrated LAN - HD Audio/Audio DSP - SATA - XHCI ('USB3') - ME Maskable Host Wake In SPT, PCIEXPWAK_STS bit isn't getting set due to known bug. So scan all PCIe RP for PME status bit & update event log accordingly. BUG=b:36992859 TEST=Build for Soraka, Verify resume due to PME on root port is logged in elog. Change-Id: I879a7c332e62ab598942b29d31bad84619b35ea7 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03soc/intel/skylake: Skip disabled IGD deviceSubrata Banik
If IGD PCI device is disabled: 1. BAR for the device will be 0. 2. There is no need to allocate framebuffer for this device. Some early SOCs don't have GFX model fuse by default hence we need to add a check to ensure PCI device is enable. This code to avoid die inside coreboot for missing resources. Change-Id: Ic31d3e57ba730f6b569bf2cc3bdc54cb369b8caf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-28soc/intel/skylake: Remove incorrect ME PG-status printBarnali Sarkar
As per discussion with CSME team, ME is NOT using PCI Config Space register HFSTS2 Bit 10 to update ME power-gated status. ME goes to CM0-PG state after ME device becomes idle after Bit 2 of MMIO register offset 0x800 (D0i3 Control - HECI1_D0I3C) is being set. And to retrieve the PG status of ME, one should read from the PWRMBASE+offset 0x590 (which should give the value 0xF9) and PWRMBASE+offset 0x594 (which should give the value 0xFF). But, also it needs some time for the ME FW to go to idle state and reflect these values in PWRMBASE registers after D0i3 bit is being set. This does not happen instantly. So, in coreboot, if we read the ME PG state in finalize.c, which happens just after FSP Notify phase, where actually ME D0i3 bit is set, we do not read the correct PG state values (i.e, 0xF9 and 0xFF). But, once it boots to Kernel, if we read those same registers through iotool mmio_read32 command, we get correct values. So, removing the ME PG state prints from coreboot, since it is actually showing wrong information, although ME Power Gating is successful. Change-Id: Idd31a9803b4c9db7d4bb8bbec5374583a8df0c41 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27soc/intel/skylake/igd.c: check return value of init_igd_opregionMartin Kepplinger
init_igd_opregion itself is supposed to return cb_err so this adds error handling, just like other implentations of write_acpi_tables do it. this had been found by coverity: *** CID 1378270: Error handling issues (CHECKED_RETURN) /src/soc/intel/skylake/igd.c: 147 in write_acpi_igd_opregion() 141 /* If IGD is disabled, exit here */ 142 if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF) 143 return current; 144 145 printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); 146 opregion = (igd_opregion_t *)current; CID 1378270: Error handling issues (CHECKED_RETURN) Calling "init_igd_opregion" without checking return value (as is done elsewhere 5 out of 6 times). 147 init_igd_opregion(opregion); 148 update_igd_opregion(opregion); 149 current += sizeof(igd_opregion_t); 150 current = acpi_align_current(current); TEST=Built Change-Id: If6f5d53037f093607d89cfe8faf193d55de7f6c4 Found-by: Coverity (CID 1378270: Error handling issues (CHECKED_RETURN)) Signed-off-by: Martin Kepplinger <martink@posteo.de> Reviewed-on: https://review.coreboot.org/20766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-07-26soc/intel/skylake/chip.h: Provide enum values for SataModeNico Huber
The values were verified to be correct with the KabylakeFsp0001 from github. Skylake FSP documentation disagrees so YMMV. Change-Id: I1ee04dbbed48d5376dbc24ae70753b059f2646eb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20765 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-25soc/intel/skylake: Add IGD id for mobile Xeon with GT2Nico Huber
Change-Id: I2cd210dd0443b854294ce7ee8e267594e3ea1780 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20651 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-07-25soc/intel/skylake: soc/intel/skylake: Initialize struct member to 0Subrata Banik
As per GCC 7.1 compiler struct reset_reply is considered as uninitialized inside send_heci_reset_message function. Change-Id: Ide53a9267dfba1a00263ada1d7016a48ecb9aad8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-25soc/intel/skylake: Skip Spi Flash Lockdown from FSPBarnali Sarkar
coreboot was setting SPI FPR register to protect the mrc_cache data range stored in flash. This programming was being done after FSP Notify 1. But, FSP was locking the SPI by setting FLOCKDN Bit during Notify phase 1, due to which coreboot was unable to protect that range. As solution, FSP introduced a new UPD SpiFlashCfgLockDown to skip the lockdown of flash on interest of bootloader. Set that UPD to 0 to skip the lockdown of FAST_SPI flash from FSP. The same is being done from coreboot after end of Post at finalize.c file. BUG=b:63049493 BRANCH=none TEST=FPR can be set properly to protect the mrc_cache range. The issue reported in the bug doesn't come when both software and hardware WP is enabled with this patch. Change-Id: I3ffca2f1b05ab2e4ef631275ef7c3a6e23e393aa Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-24soc/intel/skylake: Use common opregion implementationPatrick Rudolph
Enable SOC_INTEL_COMMON_GFX_OPREGION for all FSP versions. Allows to get rid of opregion.c, as it's no longer needed. Change-Id: I39190488e12917a09dbf7ee3947a33940ebc290b Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-07-21soc/intel/skylake: Perform LPC offset read after lockdown operationSubrata Banik
This patch is to provide an additional read LPC pci offset register BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is successful. Change-Id: I308c0622d348fc96c410a04ab4081bb6af98e874 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-21soc/intel/skylake: Rectify LPC Lock Enable (LE) bit definitionSubrata Banik
LPC pci config register BIOS Control (BC) - offset 0xDC bit 1 is for Lock Down. Change-Id: I838dd946b8cdb7114f58ccc5d02159f241f0bad0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20soc/intel/skylake: Remove dead `CONFIG_PRE_GRAPHICS_DELAY`Nico Huber
`CONFIG_PRE_GRAPHICS_DELAY` was only applied on a dead code path in `igd.c` that is guarded by always selected `CONFIG_ADD_VBT_DATA_FILE`. Nobody missed it for nearly a year, plus, it's not applied on the GOP path, let's drop it. Change-Id: I0b70cce3a3f2b50cb4e72c4d927b35510ff362a2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20soc/intel/skylake/igd: Remove dead quirk from dead code pathNico Huber
This quirk was superseded a view lines above. Also the whole path is guarded by `CONFIG_ADD_VBT_DATA_FILE` which is always selected for nearly a year now. Change-Id: I7fc5184d6e81e4588616e0302dee410e74bdab5a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-07-20soc/intel/skylake: Fix broken memory info HOB scanningNico Huber
It looks like this code was written with completely different semantics in mind. Controllers, channels and DIMMs are all presented in their phy- sical order (i.e. gaps are not closed). So we have to look at the whole structure and not only the first n respective entries. Change-Id: I8a9039f73f1befdd09c1fc8e17cd3f6e08e0cd47 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20650 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-18vboot: Remove get_sw_write_protect_state callbackJulius Werner
We've just decided to remove the only known use of the VBSD_SW_WP flag in vboot (https://chromium-review.googlesource.com/c/575389), since it was unused and never reliable on all platforms anyway. Therefore, we can now also remove the coreboot infrastructure that supported it. It doesn't really hurt anyone, but removing it saves a small bit of effort for future platforms. Change-Id: I6706eba2761a73482e03f3bf46343cf1d84f154b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/20628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-18soc/intel/skylake: Enable SMBus based on mainboard configNaresh G Solanki
Enable SMBus controller based on config in mainboard devicetree.cb BUG=None TEST= Build for Soraka, Verify that SMBus is enabled or disabled (run lspci in OS) based on board devicetree.cb config 'SmbusEnable'. Change-Id: I04c8bc30c03fd8dc7cc8ae239885e740b09e9bc1 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-07-18soc/intel/skylake: Remove Heci2 and Heci3 from wake resource listSubrata Banik
HECI2 and HECI3 devices are “function disable” during FSP Silicon Init phase. Device will not be visible over PCI bus hence removing these devices from wake source list. Change-Id: I0de665e039d74e49e5a22db9714bc9fee734e681 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-17soc/intel/skylake: remove top_of_32bit_ram() declarationAaron Durbin
It should never be globally exposed. Remove the global symbol and make it static. Change-Id: I3b85f3bbf6a73d480cdefdcdec26e137e3a3f75f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-07-14soc/intel/skylake: Set PsysPL2 MSRShelley Chen
BUG=b:7473486, b:35775024 BRANCH=None TEST=On bootup make sure PL2 and PsysPL2 values set properly (through debug output) Change-Id: I847a8458382e7db1689b426f32ff2dcbc5a0899c Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/20418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-13Rename __attribute__((packed)) --> __packedStefan Reinauer
Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13soc/intel/skylake: reduce postcar stack usage for fsp 2.0Aaron Durbin
The FSP 2.0 path uses postcar to decompress ramstage. Since postcar is entirely RAM based there's no need to have an excessively large stack for the lzma decompression buffer. Therefore, reduce the stack required to 1 KiB like apollolake. Change-Id: I45e5c283f8ae87e701c94d6a123463dddde3f221 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-12soc/intel/skylake: Remove “disable SaGv” in recovery mode flowSubrata Banik
This reverts commit 5535cead (intel/skylake: Disable SaGv in recovery mode). Commit 5535cead disables SaGv in recovery mode to save few seconds booting time as we were doing memory training on every recovery flow. Now we don't need to perform MRC training on every recovery boot due to RECOVERY_MRC_CACHE implementation in place. Hence we don't need to define different SaGv policy between Normal (developer) mode and recovery mode to save few seconds. Using different SaGv parameters between recovery and all other mode has some significent drawbacks over warm reboot cycle. We are seeing a MRC traning hang in eve/soraka/poppy devices with below use case. Step 1: Boot system in developer mode (first time RW_MRC training) Step 2: Set recovery_request=1 (using crossystem) and issue “reboot” from OS Step 3: System will perform recovery mode MRC training and boot to OS (first time RECOVERY_MRC training) Step 4: Issue “reboot” from OS console. Step 5: System wil boot in developer mode (using RW_MRC cache) Step 6: Set recovery_request=1 (using crossystem) and issue “reboot” from OS Step 7: System will pick RECOVERY_MRC_CACHE and will hang during MRC training. This patch fixes issue mentioned above and ensures system boot to OS without any hang if we change mode (dev<->recovery) over warm reset. BUG=b:63515071 BRANCH=none TEST=manual stress testing of dev<->recovery mode over warm boot. No MRC hang with this fix on eve/soraka/poppy devices. Change-Id: I8d094a8b6d78ea3bf8f929870a4a179495c29c78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-12Revert "soc/intel/skylake: storage: Add 2ms delay before exiting D3"Subrata Banik
Don't need this additional 2ms delay as PCR read after sideband write help to fix original hard hang issue. This reverts commit d4b6ac19b0a6619ebe645875282643cc50cf7a3e. Change-Id: I4232cba5b92e17f728795f7c282af6161e385e9b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-12soc/intel/skylake: Perform PCR read after all PCR writeSubrata Banik
BIOS must ensure to read same PCR offset after PCR write operation is done. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<->D3 transition on eve failing unit. No hard hang with this fix. Change-Id: Id3d567aab517b16ff99a526fc29c2d71bf4042d0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-11soc/intel/skylake: Fix PMC address range setup for PCH-HNico Huber
The PMC of PCH-H requires a different destination id. TEST=Run on kontron/bsl6 and observed that PM registers are correctly dumped at start of romstage. Change-Id: I862e4df986f1cdea34f8fa45d016fb6b51f29122 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-11soc/intel/skylake: Set generic I/O decode ranges earlyNico Huber
Move the generic I/O decode range setup before the console init. TEST=Run on kontron/bsl6 which requires 0xa80/0xa81 decoded to initialize serial ports. Serial console works from boot- block on. Change-Id: I9829f188c80eb73f6cd91b0c22e1c07da5745ad6 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20478 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-10sgx: Move SGX code to intel/common/blockPratik Prajapati
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX controls building. The SGX feature is still enabled from devicetree.cb. As of now this SGX init supports only KBL (SKL not tested). Support of SGX for new SOCs would be added incrementally in this common code base. Change-Id: I0fbba364b7342e686a2287ea1a910ef9a4eed595 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/20173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-01soc/intel/skylake: Remove unnecessary P-State and Flex Ratio assignmentBarnali Sarkar
This patch basically does two things - 1) Remove unnecessary setting of flex_ratio to TDP nominal: Factory configured (default) Max Non-TURBO ratio(P1) is already cofigured in MSR_PLATFORM_INFO(0xCE). If this Maximum Non-TURBO Ratio(P1) needs to be modified, it should be done using MSR_FLEX_RATIO (0x194). Here, in this code, the FLEX_RATIO is being modified by the TDP Nominal Ratio, reading the MSR_CONFIG_TDP_NOMINAL(0x648). But this value is actually less than the factory configured Maximum Non TURBO Ratio (P1). So, this code is actually not required. Also, the Bit 12 in PCH Soft Strap Register is already set in descriptor. This Bit implies Processor Boot Max Frequency - 0 = Disable Boot Max Frequency 1 = Enable Boot Max Frequency (Default) This setting determines if the processor will operate at maximum frequency at power-on and boot. Thus this patch will avoid one extra platform warm reset now onwards. 2) Remove wrongly setting Max Frequency in Bootblock phase: In the function set_max_frequency(), the P-State max ratio was set to TDP Nominal ratio if C-TDP was enabled, else it was set to Max Non Trbo ratio. But, when the cpu gets reset, it will operate with the Max-Non Turbo ratio only, which is greater than the TDP Nominal ratio. So, no need to set back the ratio to TDP Nominal which is lower than the currently operating frequency. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: I24bfc86ddf0f038d85da938e41e950382fe2a6c3 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-29soc/intel/skylake/Kconfig: Drop useless FSP1.1/2.0 promptsNico Huber
There is no choice, if not leaving it with the default the build will fail. Change-Id: Id91e3ce87f8ced3001fcd2125f8f6781b270f5bc Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20402 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-27soc/intel/common/opregion: Use enum cb_err as return valuePatrick Rudolph
Return CB_SUCCESS and CB_ERR instead of some integer. Preparation to merge intel/soc and intel/nb opregion implementations. Change-Id: Ib99fcfe347b98736979fc82ab3de48bfc6fc7dcd Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/20220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/intel/skylake: storage: Use word access for power state registersDuncan Laurie
In the D0 and D3 ACPI methods use word access to the PME status and control register. This brings the code inline with the Intel reference code and matches how the kernel handles access to this register. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<>D3 transition across multiple devices Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20364 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-27soc/intel/skylake: storage: Add 2ms delay before exiting D3Duncan Laurie
For the skylake/kabylake generation of PCH there is an ACPI workaround for emmc/sd power state that involves disabling and re-enabling dynamic clock gating after enabling power to the controller, before setting the power state to D0. Under certain conditions we have observed that the controller is not powered and ready by the time the kernel attempts to read the PME control and status register and so the system will hang while attempting to read PCI config register 0x84. To ensure that the controller is ready add a 2ms delay after re-enabling dynamic clock gating and before setting the power state to D0. This issue has been observed on eMMC, but the same workaround exists for the SD card interface so the same delay is added there. BUG=b:35587084 BRANCH=eve TEST=manual stress testing of D0<>D3 transition across many devices shows no hard hang after 2 days. Change-Id: If0f0323cf5437c54c907c332937b5de9dda2d8f6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-23soc/intel/skylake: Remove post SMM Relocation uCode loadingBarnali Sarkar
As per latest BWG, ucode reloading should be done at the end of Mp Init, i.e., after PRMRR and other features are enabled. No reloading specifically after SMM Relocation is required. As, in the Common CPU MP Init code, we are already doing a uCode load at the end of MP Init Feature Programming, hence, the uCode loading after SMM relocation can be removed. Change-Id: Ib1957c5fe5a8c83bb20b978a9841670b0c3e8846 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-23soc/intel/skylake: Use CPU MP Init Common codeBarnali Sarkar
This patch uses the common CPU Mp Init code. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: Ieb2f8ae25a31e86e9251fe97859678745fe610f5 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-16soc/intel/skylake: Use SCS common codeBora Guvendik
This patch uses common SCS library to setup sd card. Change-Id: I06898e30a9b39f169b35f581a3ee09238f0f40c4 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/20217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-16soc/intel/skylake: Don't allow user to change DCACHE base and sizeArthur Heymans
Change-Id: Ic1656311ecc670dc0436995f0ec8199d270da4d1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-06-14soc/intel/skylake: Add missing PCH_DEV_* definitionsFurquan Shaikh
Change-Id: Ib7aa495ccfd405d6ffc968388c28dc540da2f525 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20203 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-14soc/intel/skylake: Add USB port number information to wake sourceFurquan Shaikh
USB port status register can be used to decide if a particular port was responsible for generating PME# resulting in device wake: 1. CSC bit is set and port is capable of waking on connect/disconnect 2. PLC bit is set and port is in resume state BUG=b:37088992 TEST=Verified with wake on USB2.0 port 3, mosys shows: 19 | 2017-06-08 15:43:30 | Wake Source | PME - XHCI (USB 2.0 port) | 3 Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-13Consolidate reset API, add generic reset_prepare mechanismJulius Werner
There are many good reasons why we may want to run some sort of generic callback before we're executing a reset. Unfortunateley, that is really hard right now: code that wants to reset simply calls the hard_reset() function (or one of its ill-differentiated cousins) which is directly implemented by a myriad of different mainboards, northbridges, SoCs, etc. More recent x86 SoCs have tried to solve the problem in their own little corner of soc/intel/common, but it's really something that would benefit all of coreboot. This patch expands the concept onto all boards: hard_reset() and friends get implemented in a generic location where they can run hooks before calling the platform-specific implementation that is now called do_hard_reset(). The existing Intel reset_prepare() gets generalized as soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now easily be added later if necessary). We will also use this central point to ensure all platforms flush their cache before reset, which is generally useful for all cases where we're trying to persist information in RAM across reboots (like the new persistent CBMEM console does). Also remove cpu_reset() completely since it's not used anywhere and doesn't seem very useful compared to the others. Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19789 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-09soc/intel/skylake: Enable ACPI PM timer emulation on all CPUsSubrata Banik
This patch enables ACPI timer emulation on all the logical cpus. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Verify MSR 0x121 gets programmed on all logical cpus during coreboot MP Init. Change-Id: I2246cdfe1f60fd359b0a0eda89b4a45b5554dc4a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18288 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09soc/intel/skylake: Use CPU common library codeBarnali Sarkar
This patch makes SOC files to use common/block/cpu/cpulib.c file's helper functions. Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/19566 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-09soc/intel/skylake: Move update microcode from cbfs to mp_ops callbacksBarnali Sarkar
FIT is already loading microcode before CPU Reset. So, we need not update the microcode again in RO FW in bootblock. But we need to update in RW FW if there is any new ucode version. So, added the update microcode function in get_microcode_info callback before MP Init to make sure BSP is using the microcode from cbfs. BUG=none BRANCH=none TEST=Build and Boot poppy Change-Id: I5606563726c00974f00285acfa435cadc90a085e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20051 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-06-09soc/intel/skylake: Cache the MMIO BIOS regionAaron Durbin
If the boot media is memory mapped temporarily mark it as write protect MTRR type so that memory-mapped accesses are faster. Depthcharge payload loading was sped up by 75ms using this. Change-Id: Ice217561bb01a43ba520ce51e03d81979f317343 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-09soc/intel/skylake: Use common systemagent codeSubrata Banik
This patch perform resource mapping for PCI, fixed MMIO, DRAM and IMR's based on inputs given by SoC. TEST=Ensure PCI root bridge 0:0:0 memory resource allocation remains same between previous implementation and current implementation. Change-Id: I93567a79b2d12dd5d6363957e55ce2cb86ff83a7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/19796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09soc/skylake: add ACPI method to generate USB port infoMatt DeVillier
Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: I14ba3cea821e103208426e9fcaa0833d84157ff8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-08fsp/gop: Add running the GOP to the choice of gfx initNico Huber
The new config choice is called RUN_FSP_GOP. Some things had to happen on the road: * Drop confusing config GOP_SUPPORT, * Add HAVE_FSP_GOP to chipsets that support it, * Make running the GOP an option for FSP2.0 by returning 0 in random VBT getters. Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-07src: change coreboot to lowercaseMartin Roth
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-06soc/intel/skylake: Use PCI IDs from device/pci_ids.hSubrata Banik
Remove PCI IDs inclusion from soc header rather referring those from device/pci_ids.h. Change-Id: I490da3e336fb6f8194d5fba800132f550ed5ab37 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-06soc/intel/skylake/chip.h: Reorder declarationsNico Huber
Place `tdp_pl2_override` above the FSP options as it's not an FSP option. Change-Id: Idff2b628d19ce1a80294b28c55c05ba4157d07e0 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-06soc/intel/skylake/chip.h: Provide some enumsNico Huber
Provide some enums instead of unreadable comments that are usually copied all over. Change-Id: Iff551565647f28ecb226e1df633b4deec0ab0a7f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-05soc/intel/skylake: Use Intel timer common codeAamir Bohra
Use timer code from soc/intel/common. This code removes monotonic timer refrence w.r.t MSR 24Mhz counter(0x637) and use tsc timer. Change-Id: I7fad620b11c9e5db128f646639c79ea58a0a574f Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-05soc/intel/skylake: Add config for cpu base clock frequencyAamir Bohra
Add config for cpu base clock frequency(Mhz) and replace current refrence from soc/cpu.h with config option. Change-Id: Idf8e85f7ae6d965fa987a4f5c4905503ee354d69 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/20016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-05soc/intel/common/block: add bios caching to fast spi moduleAaron Durbin
Add fast_spi_cache_bios_region() that sets up a variable MTRR as write-protect covering the fast spi BIOS region. Change-Id: I282c5173cc655004daf16ea2e85423aaded3648d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-06-03soc/intel/skylake: Add macro for setting GPIO interrupt trigger mode.Kane Chen
Currently, there is no macro to set GPIO interrupt trigger mode. The purpose is to make coreboot set same trigger mode as GpioInt BUG=b:62067569 TEST=checked unused interrupt on SD_CD does not happen after s3 resume Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/19992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-27soc/intel/skylake: Add detailed information about PME wake sourcesFurquan Shaikh
Add more fine-grained details about what device caused the PME wake event. This requires checking the PME status bit (bit 15) in PCI PM control and status register for the PCI device. BUG=b:37088992 TEST=Verifed that XHCI wake source was identified correctly: 135 | 2017-05-25 15:28:17 | ACPI Enter | S3 136 | 2017-05-25 15:28:26 | ACPI Wake | S3 137 | 2017-05-25 15:28:26 | Wake Source | PME - XHCI | 0 Change-Id: I6fc6284cd04db311f1f86b8a86d0bb708392e5d5 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19925 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-18 17:18:51 +0000