coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2015-07-29	skylake: remove the redundant fspNotify in chip final.	robbie zhang
2015-07-29	skylake: Rework microcode include path	Duncan Laurie
2015-07-24	skylake: Fix building without serial console	Duncan Laurie
2015-07-23	skylake: sanitize pcr header for ACPI and assembler	Aaron Durbin
2015-07-23	skylake: provide more clarity for PCR access	Aaron Durbin
2015-07-21	skylake: add global reset cause registers to power state	Aaron Durbin
2015-07-21	skylake: take into account deep s3 in power failure check	Aaron Durbin
2015-07-21	skylake: read out and report full width of gen_pmcon registers	Aaron Durbin
2015-07-21	Glados: Update Serial IO modes in devicetree	Naveen Krishna Chatradhi
2015-07-21	intel/skylake: support 32bit uart8250_mem driver in romstage	Naveen Krishna Chatradhi
2015-07-21	Skylake: Initialize GPIOs for UART2	rsatapat
2015-07-21	Skylake: Only support UART2 as debug port, clean up the rest	Naveen Krishna Chatradhi
2015-07-21	intel fsp: remove CHIPSET_RESERVED_MEM_BYTES	Aaron Durbin
2015-07-21	skylake: re-enable PCIe L1 sub states	Aaron Durbin
2015-07-21	skylake: honor pcie root port settings already in chip.h	Aaron Durbin
2015-07-21	skylake: Show SPI controller if enabled in devicetree.cb	Duncan Laurie
2015-07-17	soc/intel: Remove microcode terminators	Stefan Reinauer
2015-07-17	skylake: remove whitespace from ASL files	Stefan Reinauer
2015-07-16	soc/intel: Add Skylake SOC support	Lee Leahy
2015-07-16	soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC	Lee Leahy