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path: root/src/soc/intel/skylake/xhci.c
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2019-07-19soc/intel/common: Add SOC specific function to get XHCI USB infoKarthikeyan Ramasubramanian
It feels appropriate to define SoC specific XHCI USB info in SoC specific XHCI source file and an API to get that information instead of defining it in elog source file. This will help in other situations where the information is required. BUG=None BRANCH=None TEST=Boot to ChromeOS. Change-Id: Ie63a29a7096bfcaab87baaae947b786ab2345ed1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34290 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-03-06soc/intel/skylake: Use intel/common/xhci driverSubrata Banik
Change-Id: I7bd83d293fcc1848f6f64526d8f38d010c1f69a3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18223 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-06soc/intel/skylake: Clean up XHCI codeSubrata Banik
Don't need "skylake/include/soc/xhci.h", hence removed. Change-Id: I35df2003f311b557b622ce1d7a1c2e832693c2fc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/18508 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-16soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL ↵Sooi, Li Cheng
HALO SOC Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC Change-Id: I6a44d55d1588d2620bd1179ea7dc327922f49fd7 Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com> Reviewed-on: https://review.coreboot.org/18028 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-07-16soc/intel: Add Skylake SOC supportLee Leahy
Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16soc/intel/skylake: Use Broadwell as comparision base for Skylake SOCLee Leahy
Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>