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Clean up and move UART related code under a single uart.c file.
Change-Id: I7ed03fc5fe79e38350d7edc70ad55d54db780fed
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Select LPSS UART Base address based on LPSS UART port index.
Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Add a new variable to GNVS to store information during S3 suspend
whether UART debug port controller is enabled.
2. On resume, read stored GNVS variable to decide if UART debug port
controller needs to be initialized.
3. Provide helpers functions required by intel/common UART driver for
enabling controller on S3 resume.
BUG=b:64030366
TEST=Verified behavior with different combinations:
1. Serial console enabled in coreboot: No change in behavior.
2. Serial console enabled only in kernel: coreboot initializes debug
controller on S3 resume.
3. Serial console not enabled in coreboot and kernel: coreboot skips
initialization of debug controller on S3 resume.
Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20886
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I53ed687dc49524e001889f091825b2cc530546a3
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/19492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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HALO SOC
Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO SOC
Change-Id: I6a44d55d1588d2620bd1179ea7dc327922f49fd7
Signed-off-by: Sooi, Li Cheng <li.cheng.sooi@intel.com>
Reviewed-on: https://review.coreboot.org/18028
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Many Kconfig options changed in coreboot.org since
skylake was first started. Fix Kconfig option name
changes, and also provide a common option, UART_DEBUG
that can be selected to select all the necessary
options.
Note: It's still a requirement to manually unset the
8250IO option because that's unconditionally set.
BUG=chrome-os-partner:43419
BUG=chrome-os-partner:43463
BRANCH=None
TEST=Built glados. Booted into kernel. Kernel reboots somewhere.
Original-Change-Id: I9e6549ea0f1d6b9ffe64a73856ec87b5bc7b7091
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289951
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I0e6b492d7279cc35d4fb3ac17fd727177adce39d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11172
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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In order to build without CONFIG_CONSOLE_SERIAL the Skylake
SOC Kconfig should not be enabling serial console by default.
Also fix other compile issues when serial console is disabled.
BUG=chrome-os-partner:40857
BRANCH=none
TEST=build glados without serial console enabled
Change-Id: I2b20d9d9cd66e79587525f7bb458782eeeac4a95
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f40fbea8d5dade560c08e4abf15a2a1cc28b9e55
Original-Change-Id: I6c5da8a5eee4090c89deb8feba676479cd834292
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/287438
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11043
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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On Skylake, only UART2 is supported as debug port and the macros
INTEL_PCH_UART_CONSOLE_NUMBER, INTEL_PCH_UART_CONSOLE and the partial
code for UART0, 1 are cleaned up for Skylake and Sklrvp, Kunimitsu and
Glados boards.
BRANCH=none
BUG=chrome-os-partner:40857
TEST=Built for kunimitsu, checked the coreboot logs on LPSS UART2
Change-Id: I2fbcfb1d1ca6f59309a77c67d022cf4f5da7f7c0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e714c18d462bc7bdd7068309fb6be77da6973642
Original-Change-Id: I9343abd90ce685ea2d676047dccbefad7457b69f
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285793
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/10994
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add the files to support the Skylake SOC.
Matches chromium tree at 927026db
BRANCH=none
BUG=None
TEST=Build and run on a Skylake platform
Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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