coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2015-08-29	intel/skylake: Implement HW Sequence based WP status read functionality	Barnali Sarkar
2015-08-29	intel/skylake: Fix RMT disable of saved training data	Duncan Laurie
2015-08-29	intel/skylake: Force full memory train if RMT is enabled	Duncan Laurie
2015-08-29	fsp raminit: Add romstage_params to soc_memory_init_params	Duncan Laurie
2015-08-19	skylake: Update Memory and Silicon Init params	Rizwan Qureshi
2015-08-14	skylake: pass IED_REGION_SIZE Kconfig to FSP	Aaron Durbin
2015-08-14	skylake: use native gpio configuration for uart	Aaron Durbin
2015-08-13	skylake: fix serial port with new code base	Aaron Durbin
2015-07-24	skylake: Fix building without serial console	Duncan Laurie
2015-07-21	skylake: add global reset cause registers to power state	Aaron Durbin
2015-07-21	skylake: take into account deep s3 in power failure check	Aaron Durbin
2015-07-21	skylake: read out and report full width of gen_pmcon registers	Aaron Durbin
2015-07-21	intel/skylake: support 32bit uart8250_mem driver in romstage	Naveen Krishna Chatradhi
2015-07-21	Skylake: Initialize GPIOs for UART2	rsatapat
2015-07-21	Skylake: Only support UART2 as debug port, clean up the rest	Naveen Krishna Chatradhi
2015-07-21	skylake: honor pcie root port settings already in chip.h	Aaron Durbin
2015-07-21	skylake: Show SPI controller if enabled in devicetree.cb	Duncan Laurie
2015-07-16	soc/intel: Add Skylake SOC support	Lee Leahy
2015-07-16	soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC	Lee Leahy