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* Add Memory Channel Status Enum for Channel detection.
* Align > 80 characters per line.
* Add hob_size == 0 check.
Change-Id: I6ad99de53e280a3db431f706310e6cb22b8b3953
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The FSP 2.0 Memory_Info_HOB for KBL is not sending
"MemoryType" value as what is required for SMBIOS Table
according to SMBIOS Spec. Thus, converting the value
retrieved from FSP HOB to the correct value.
This change will not be required for upcoming SOCs since
FSP have fixed this issue in its next platforms and thus it
will take care and send the correct value in "MemoryType"
field based on SMBIOS spec. Thus this conversion from coreboot
will not be required in the next platfoms. "MemoryType" value
can be directly passed to dimm_info_fill() function.
BUG=none
BRANCH=none
TEST=Tested in Soraka, and getting the value as 0x1D for
LPDDR3 memory. dmidecode (latest version 3.1) Command Type 17
will also show correct information. Currently, it was showing
"Unknown".
Change-Id: I75d6cca464680a88bf836e25bf5440a9cdbc738e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/23384
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SoC needs to select specific macros to compile commom PMC code.
TEST=Build and boot KBL (soraka/eve), APL (reef)
Change-Id: Iacc8da986c01e9ac7516643dafc6d932ebe0ee5e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This commit just moves the vboot sources into
the security directory and fixes kconfig/makefile paths.
Fix vboot2 headers
Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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This change moves soc_fill_power_state and soc_prev_sleep_state to
pmutil.c. It allows the functions to be used across romstage and smm.
BUG=b:67874513
Change-Id: I375ac029520c2cdd52926f3ab3c2d5559936dd8c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22085
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change d3476809 (soc/intel/skylake: Add support in SKL for PMC common
code) changed the logic for obtaining previous sleep state by
unconditionally checking for PWR_FLR and SUS_PWR_FLR. In case of deep
S3, SUS_PWR_FLR is set in gen_pmcon_b (just like resume from deep
S5/G3) and hence the check for power failure should be done only when
WAK_STS bit is not set. This is necessary to differentiate wakes from
deep S3 and G3.
This change restores the original logic by performing power failure
check only in cases where WAK_STS bit is not set.
BUG=b:67617726
TEST=Verified following:
1. When WAK_STS bit is not set and SUS_PWR_FLR is set, coreboot
correctly identifies that the system prev sleep state was S5.
2. When WAK_STS bit is set and SUS_PWR_FLR is set, coreboot correctly
identifies that the system prev sleep state was S3.
Change-Id: Ic97bbc9911ba34aa21f4728c77fc20c5bb08f6f9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/20499
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update FSP header files to version 2.7.2.
New UPDs added
FspmUpd.h:
*CleanMemory
FspsUpd.h:
*IslVrCmd
*ThreeStrikeCounterDisable
Structure member names used to specify memory configuration
to MRC have been updated, SoC side romstage code is updated
to handle this change.
CQ-DEPEND=CL:*460573,CL:*460612,CL:*460592
BUG=b:65499724
BRANCH=None
TEST= Build and boot soraka, basic sanity check and suspend resume checks.
Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch implements soc function to get previous sleep state
using chipset_power_state global structure.
acpi_get_sleep_type is needed in PRE_RAM stage when soc selects
CONFIG_EARLY_EBDA_INIT kconfig option.
Change-Id: I79acbfc09c8d255fbf9d73e49e8c7764f3f3fac6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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We do not need or use the Management Engine MBP HOB so that
step can be skipped when FSP initializes the ME.
BUG=b:64479422
TEST=boot with FSP debug enabled binary and ensure that the
output indicates this step is being skipped:
Skipping MBP data due to SkipMbpHob set!
Change-Id: I5ea22ec4b8b47fa17b1cf2bf562337bfaad5ec0d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/20951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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It looks like this code was written with completely different semantics
in mind. Controllers, channels and DIMMs are all presented in their phy-
sical order (i.e. gaps are not closed). So we have to look at the whole
structure and not only the first n respective entries.
Change-Id: I8a9039f73f1befdd09c1fc8e17cd3f6e08e0cd47
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20650
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We've just decided to remove the only known use of the VBSD_SW_WP flag
in vboot (https://chromium-review.googlesource.com/c/575389), since it
was unused and never reliable on all platforms anyway. Therefore, we can
now also remove the coreboot infrastructure that supported it. It
doesn't really hurt anyone, but removing it saves a small bit of effort
for future platforms.
Change-Id: I6706eba2761a73482e03f3bf46343cf1d84f154b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable SMBus controller based on config in mainboard devicetree.cb
BUG=None
TEST= Build for Soraka, Verify that SMBus is enabled or disabled (run
lspci in OS) based on board devicetree.cb config 'SmbusEnable'.
Change-Id: I04c8bc30c03fd8dc7cc8ae239885e740b09e9bc1
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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The FSP 2.0 path uses postcar to decompress ramstage. Since postcar
is entirely RAM based there's no need to have an excessively large
stack for the lzma decompression buffer. Therefore, reduce the stack
required to 1 KiB like apollolake.
Change-Id: I45e5c283f8ae87e701c94d6a123463dddde3f221
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This reverts commit 5535cead (intel/skylake: Disable SaGv in
recovery mode).
Commit 5535cead disables SaGv in recovery mode to save few seconds
booting time as we were doing memory training on every recovery flow.
Now we don't need to perform MRC training on every recovery boot
due to RECOVERY_MRC_CACHE implementation in place. Hence we don't
need to define different SaGv policy between Normal (developer) mode
and recovery mode to save few seconds.
Using different SaGv parameters between recovery and all other mode
has some significent drawbacks over warm reboot cycle. We are seeing
a MRC traning hang in eve/soraka/poppy devices with below use case.
Step 1: Boot system in developer mode (first time RW_MRC training)
Step 2: Set recovery_request=1 (using crossystem) and issue “reboot”
from OS
Step 3: System will perform recovery mode MRC training and boot to
OS (first time RECOVERY_MRC training)
Step 4: Issue “reboot” from OS console.
Step 5: System wil boot in developer mode (using RW_MRC cache)
Step 6: Set recovery_request=1 (using crossystem) and issue “reboot”
from OS
Step 7: System will pick RECOVERY_MRC_CACHE and will hang during
MRC training.
This patch fixes issue mentioned above and ensures system boot to
OS without any hang if we change mode (dev<->recovery) over warm
reset.
BUG=b:63515071
BRANCH=none
TEST=manual stress testing of dev<->recovery mode over warm boot.
No MRC hang with this fix on eve/soraka/poppy devices.
Change-Id: I8d094a8b6d78ea3bf8f929870a4a179495c29c78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This patch perform resource mapping for PCI,
fixed MMIO, DRAM and IMR's based on inputs given by SoC.
TEST=Ensure PCI root bridge 0:0:0 memory resource allocation
remains same between previous implementation and current
implementation.
Change-Id: I93567a79b2d12dd5d6363957e55ce2cb86ff83a7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch currently contains the following -
1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code.
2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library.
3. Use common FAST_SPI header file.
Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/19055
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Utilize the postcar stage for tearing down CAR and initializing
the MTRRs once ram is up. This flow is consistent with apollolake
and allows CAR_GLOBAL variables to be directly accessed and no
need for migrating CAR_GLOBAL variables as romstage doesn't
run with and without CAR being available.
Change-Id: I76de447710ae1d405886eb9420dc4064aa26eccc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19335
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Create sample model for common car init and teardown programming.
TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED
and CAR_NEM configs till post code 0x2a.
Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18381
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add configs for enabling Intel TraceHub and DCI for aid in debugging.
Change-Id: Ic40f9499c0125070049856e242e89024ca5a1c4e
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18791
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Extract SMBIOS memory information from FSP SMBIOS_MEM_INFO_HOB
and save it in CBMEM.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS Table from Kernel command "dmidecode".
Change-Id: I593d4ccb0d4866e99913a73c49b2f000b51827d1
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18275
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Prmrr configuration is supported by Kabylake FSP-M with UPD provided.
It is required as one of the SGX initialization steps in BIOS.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified uncore PRMRR MSRs get programmed to set
size and boot.
Change-Id: I2b3dc7c92487505165ee429bd1a37bd60ceac8f3
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: https://review.coreboot.org/18361
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Currently car_stage_entry is defined only in romstage_after_verstage and
as a result when SEPARATE_VERSTAGE is not selected, there is no
entry point into romstage and romstage will not be started at all.
The solution is move out romstage_after_verstage.S from fsp1.1 driver
to skylake/romstage. And add CONFIG_PLATFORM_USES_FSP1_1 to fix the
build and boot issue with this change.
Besides that, rename the romstage_after_verstage to romstage_c_entry
in more appropriate naming convention after this fix.
Tested on SkyLake Saddle Brook (FSP 1.1) and KabyLake Rvp11 (FSP 2.0),
romstage can be started successfully.
Change-Id: I1cd2cf5655fdff6e23b7b76c3974e7dfd3835efd
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/17976
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Cosmetic changes to rename car_stage.S to car_stage_fsp20.S,
so that it is associated with FSP driver version that is being used.
Tested on Kabylake Rvp11.
Change-Id: I869df6eb746e3982e5912c272255eab6cb008838
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/18083
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Define controller for fast SPI.
2. Separate out functions that are specific to SPI and flash
controller in different files.
BUG=chrome-os-partner:59832
BRANCh=None
TEST=Compiles successfully for chell and eve.
Change-Id: I2fe0ef937297297339d4ea19dc37d3061caaa80c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17933
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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- Separate mma code for fsp1.1 and fsp2.0
and restructuring the code
- common code is placed in mma.c and mma.h
- mma_fsp<ver>.h and fsp<ver>/mma_core.c contains
fsp version specific code.
- whole MMA feature is guarded by CONFIG_MMA flag.
Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/17496
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BootLoaderTolumSize FSP-M UPD is already initialized with cbmem_overhead_size()
inside driver/fsp2_0/memory_init.c, hence remove the duplicate assignment.
Change-Id: I0b1d9769cd2a863bf0547ce5f44928cacc5a63b6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17721
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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In bootblock, cpu flex ratio is set to non-turbo max.
In FSP UPD, if CpuRatioOverride is zero, then it tries to program cpu
ratio to zero. Since it is different than the non-zero value programmed
in bootblock, FSP gives reset.
To avoid the reset, set FSP UPD for CPU flex ratio override to that
value as set in bootblock.
Change-Id: I8cae5530ec97cedfbd71771f291db6f55a9fd5c2
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17555
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Ibad1ad6bb9eedf2805981623e835db071d54c528
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17497
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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RW flag was added to spi_slave structure to get around a requirement on
some AMD flash controllers that need to group together all spi volatile
operations (write/erase). This rw flag is not a property or attribute of
the SPI slave or controller. Thus, instead of saving it in spi_slave
structure, clean up the SPI flash driver interface. This allows
chipsets/mainboards (that require volatile operations to be grouped) to
indicate beginning and end of such grouped operations.
New user APIs are added to allow users to perform probe, read, write,
erase, volatile group begin and end operations. Callbacks defined in
spi_flash structure are expected to be used only by the SPI flash
driver. Any chipset that requires grouping of volatile operations can
select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and
define callbacks for chipset_volatile_group_{begin,end}.
spi_claim_bus/spi_release_bus calls have been removed from the SPI flash
chip drivers which end up calling do_spi_flash_cmd since it already has
required calls for claiming and releasing SPI bus before performing a
read/write operation.
BUG=None
BRANCH=None
TEST=Compiles successfully.
Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17462
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Populate SoC related Memory initialization params.
Post memory init, set DISB, setup stack and MTRRs using the postcar
funtions provided in postcar_loader.c.
TEST=Build and boot kunimitsu, dram initialization done.
ramstage is loaded.
Change-Id: I8d943e29b6e118986189166d92c7891ab6642193
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16315
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add Initial pieces of code to support fsp2.0 in skylake keeping
the fsp1.1 flow intact.
The soc/romstage.h and soc/ramstage.h have a reference to
fsp driver includes, so split these header files for
each version of FSP driver.
Add the below files,
car_stage.S:
Add romstage entry point (car_stage_entry).
This calls into romstage_fsp20.c and aslo handles
the car teardown.
romstage_fsp20.c:
Call fsp_memory_init() and also has the callback
for filling memory init parameters.
Also add monotonic_timer.c to verstage.
With this patchset and relevant change in kunimitsu mainboard,
we are able to boot to romstage.
TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1
Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0
Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16267
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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DCACHE_RAM_SIZE_TOTAL is set to 0x40000 and is being used to
set up CAR. Whereas DCACHE_RAM_SIZE which is set to 0x10000
is used to calculate the _car_region_end in car.ld. If the FSP CAR
requirement is greater than or even close to DCACHE_RAM_SIZE then,
the CAR region for FSP will be determined to be below the overall
CAR region boundary i.e, out of CAR memory range.
This is working with FSP 1.1 because we provide the FspCarSize
and FspCarBase explicitly in a UPD. Hence, FSP is still able to
use the upper region of CAR memory for its purpose.
However, it will be a problem in case of FSP2.0 where FSP usable CAR
is calculated using _car_region_end.
So, Remove the the use of DCACHE_RAM_SIZE_TOTAL and set
DCACHE_RAM_SIZE to correct value i.e, 0x40000(256KB)
Change-Id: Ie2cb8bb0705a37edb3414850d7659f8a3dd6958b
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16236
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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There is a lot of code that is being referred to in bootblock but
resides under skylake/romstage folder. Hence move this code
into skylake/bootblock, and update the relevant header files
and Makefiles.
TEST=Build and Boot kunimitsu.
Change-Id: If94e16fe54ccb7ced9c6b480a661609bdd2dfa41
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16225
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Prepare Skylake for FSP2.0 support.
We do not use FSP-T in FSP2.0 driver, hence guard the
FspTempRamInit call under a switch.
In addition to the current early PCH configuration
program few more register, so all in all we do the following,
* Program and enable ACPI Base.
* Program and enable PWRM Base.
* Program TCO Base.
* Program Interrupt configuration registers.
* Program LPC IO decode range.
* Program SMBUS Base address and enable it.
* Enable upper 128 bytes of CMOS.
And split the above programming into into smaller functions.
Also, as part of bootblock_pch_early_init we enable decoding
for HPET range. This is needed for FspMemoryInit to store and
retrieve a global data pointer.
And also move P2SB related definitions to a new header file.
TEST=Build and boot Kunimitsu
Change-Id: Ia201e03b745836ebb43b8d7cfc77550105c71d16
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16113
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Program MCHBAR, DMIBAR, EPBAR, EDRAMBAR and GDXCBAR.
Also program the PAM registers. The system agent was being
programmed in romstage during pre-console initialization, after
moving to C_ENVIRONMENT bootblock this was missing, restoring
the same.
TEST=Build and Boot Kunimitsu
Change-Id: Iaf310cfb83e58eb8d5affb481dfc343f5d45961b
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16224
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The function name "pmc_tco_regs" is changed to "smbus_tco_regs"
since TCO offsets belongs to SMBUS PCI device.
BUG=none
BRANCH=none
TEST=Built and booted kunimitsu
Change-Id: I4ac26df81a8221329f2b45053dd5243cd02f8ad7
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16155
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Here is the list of items of code cleanup
1. Define TCO registers in smbus.h and not in pmc.h (as per EDS).
2. Include smbus.h wherever these TCO register defines were used.
3. Remove duplication of define in gpio_defs.h.
4. Remove unnecessary console.h include from memmap.h as no prints done.
5. Remove unnecessary comment from pch.c.
BUG=none
BRANCH=none
TEST=Built and boot kunimitsu.
Change-Id: Ibe6d2537ddde3c1c7f8ea5ada1bfaa9be79c0e3b
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16027
Tested-by: build bot (Jenkins)
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
|
|
Adding kabylake device ids for chip inits.
Skylake and Kabylak do not differ much, the intention
is to support both SoCs in the same code base.
Change-Id: I9ff4c6ca08fe681798001ce81cca2c085ce32325
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16049
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Testing for "devfn < 0" on an unsigned doesn't work, and i2c_bus_to_devfn
returns an int (with -1 for "error"), so use int for devfn.
Change-Id: I7d1cdb6af4140f7dc322141c0c018d8418627434
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1357450, #1357449
Reviewed-on: https://review.coreboot.org/15964
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
List of activity performing in this patch
- early PCH programming
- early SA programming
- early CPU programming
- mainborad early gpio programming for UART and SPI
- car setup
- move chipset programming from verstage to post console
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and booted kunimitsu till POST code 0x34
Change-Id: If20ab869de62cd4439f3f014f9362ccbec38e143
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15785
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and
developer mode check functions to vboot. Thus, get rid of the
BOOTMODE_STRAPS option which controlled these functions under src/lib.
BUG=chrome-os-partner:55639
Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15868
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use
of verified boot library without having to stick to CHROMEOS.
BUG=chrome-os-partner:55639
Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15867
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I5f2aa424a167092b570fda020cddce5ef906860a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15671
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
|
|
Have the Skylake SOC generate ACPI timing values for the enabled I2C
controllers instead of passing it in the DSDT with static timings.
The timing values are generated from the controller clock speed and
are more accurate than the hardcoded values that were in the ASL which
were originally copied from Broadwell where the controller is running
at a different clock speed...
Additionally it is now possible for a board to override the values
using devicetree.cb. If zero is passed in for SCL HCNT or LCNT then
the kernel will generate its own timing using the same forumla, but if
the SDA hold time value is zero the kernel will NOT generate a correct
value and the SDA hold time may be incorrect.
This was tested on the Chell platform to ensure all the I2C devices on
the board are still operational with these new timing values.
Change-Id: I4feb3df9e083592792f8fadd7105e081a984a906
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15291
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Support the common Intel LPSS I2C driver for the 6 I2C bus controllers
that are present on the Skylake-LP PCH with a 120 mHz clock. The
required lpss_i2c_base_address() method is implemented separately for
verstage/romstage and ramstage environments.
This provides methods to convert to and from "struct device" and the
I2C controller bus number for that device. These are used to provide
support for the "I2C Bus Operations" that are present in the coreboot
devicetree.
To support the I2C controller before ramstage an early init function
is provided to do minimal initializaiton of the PCI device and assign
a temporary base address for use before memory. The final base
address is assigned during device enumeration and used during ramstage.
Because it is usually not necessary to enable I2C controllers before
ramstage a config register for the devicetree is provided to perform
early initialization of this controller. In addition the bus speed
can be set in the devicetree and that speed will be applied when the
device is initialized. If not provided the default speed is set to
I2C_SPEED_FAST.
This was tested with the google/chell mainboard by reading and writing
from the trackpad and codec devices during both verstage and ramstage.
Change-Id: Ia0270adfaf2843a3be4e00c732c85401a3401ef5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15105
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
The FBC hardware for skylake does not have access to the bios_reserved
range so it always assumes 8MB is used and so the kernel will
therefore need to avoid using the last 8MB of the stolen window.
With the default stolen size of 32MB(-8MB) there is not enough space
for FBC to work with a high resolution panel.
Kernel reference:
http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=a9da512b3ed73045253afd778e40d4298f42905b
BUG=chrome-os-partner:50396
BRANCH=glados
TEST=build and boot on chell DVT
Change-Id: I3049d7d9e7c551aad5b8fd1630d5fbd88ccb2692
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: fff1f4b35e23e77cdc72c5bcc290f199494cdbbb
Original-Change-Id: If468cca5759a320f3cd2d7eb09f4bcc0117b24cb
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/328813
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13833
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
The PCH does not set PM1_STS[WAK_STS] bit when waking from a
G3 state, which is triggered by hibernate now on chell when we
do a PMIC shutdown. This means the checks for S5 wake are not
done and instead it is logged as a wake from S0.
BUG=chrome-os-partner:50076
BRANCH=glados
TEST=pass firmware_EventLog test on chell
Change-Id: I3ca05a4824df3401150a63d4b6555f759de40087
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: de6c9bac447edd06568193f990f1f4e278576783
Original-Change-Id: I4472498468d620fe69f2b68710e818a4ad287382
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/326888
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13696
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
In order to not reboot loop in the face of failed vboot verification
on resume set the PM1 control register to indicate S5. After the
subsequent cold reset the PM1 control register will indicate S5
as it should.
BUG=chrome-os-partner:46049
BRANCH=glados
TEST=On chell injected failed vboot verification. Ensured a reboot
loop doesn't ensue.
Change-Id: Ie5e9e3f6441a217a5e02b4d78aaf21f8249b8a43
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a63b57d7bc59bcaf5518f7cc4afccd3d5da6df1c
Original-Change-Id: I5e467854bf065a138bd46e476a7e7088f51454ca
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/323504
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13579
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
To allow skylake platforms to run with verified memory init
code the chipset needs to implement vboot_platform_is_resuming()
so that the vboot code can make proper decisions.
BUG=chrome-os-partner:46049
BRANCH=glados
TEST=Suspended and resumed on chell. Also, tested with an EC build
which returns a bad hash to ensure that is properly caught.
Change-Id: I508a339c07dcc9e7c56a0df4201660827b3ae07a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a3e11789339bcd8fc8fc99b704c6a1110acf5302
Original-Change-Id: I40264019eb28e85795258112c720056a6a3fc523
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/323503
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13578
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Now coreboot should do BIOS CAR setup along with NEM
mode setup.
This patch also provides a mechanism to use 16MB code caching
benefit although LLC still limited to 1M/1.5M based
on SOC LLC limit.
Here with unlimited cache line gets replaced. Now we could use
unlimited cache size along with well defined data size
[pg: updated to current upstream #defines]
BUG=chrome-os-partner:48412
BRANCH=glados
TEST=Builds and Boots on FAB4 SKU2/3.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: pchandri <preetham.chandrian@intel.com>
Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com>
Change-Id: I96a9cf3a6e41cae9619c683dca28ad31dcaa2536
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ec51f15c874ad2f1f4fad52fa8deced7b27a24b
Original-Change-Id: Id62c15799d98bc27b5e558adfa7c7b3468aa153a
Original-Reviewed-on: https://chromium-review.googlesource.com/320855
Original-Commit-Ready: Subrata Banik <subrata.banik@intel.com>
Original-Tested-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13138
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This patch disables the SaGv feature in recovery mode. Since the memory
training happens at both low and high frequency points when SaGv is
enabled, recovery mode boot time increases by 5 seconds. To reduce this
5 second increase, the SaGv feature is disabled in recovery mode.
The value "0" here means SaGv disable.
Following is the table for same.
0=Disabled (SaGv disabled)
1=FixedLow (Fixed to low frequency)
2=FixedHigh (Fixed to High frequency)
3=Enabled (SaGv Enabled. Dynamically changes)
BRANCH=None
BUG=chrome-os-partner:48534
TEST=Built for kunimitsu.
Results show recovery mode boot time
is not affected (not increased).
Change-Id: I77412a73a183a5dbecf5564a22acc6e63865123e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dc586079052acf9af573b68dff910386cd43484d
Original-Change-Id: Ice3e1a630e119d40d3df52e3a53ca984e999ab0b
Original-Signed-off-by: haridhar <haridhar.kalvala@intel.com>
Original-Signed-off-by: Somayaji, Vishwanath <vishwanath.somayaji@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315759
Original-Commit-Ready: Haridhar Kalvala <haridhar.kalvala@intel.com>
Original-Tested-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-on: https://review.coreboot.org/12998
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
There is a UPD setting exposed by FSP that allows the DDR
frequency to be limited. Expose this for devicetree.
BUG=chrome-os-partner:47346
BRANCH=none
TEST=tested by limiting DDR frequency to 1600 on chell EVT
Change-Id: I1f17b221d9fa4c2dd1e8c5f403deb0f2bc0493a7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91f760ad19823225f7e5bd2dc690164ed253e220
Original-Change-Id: Ibcd4a65a9cfd7d32fbf2ba8843ab25da8e9cf28a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/317243
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12981
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Some MemoryInit UPD parameters have been moved to
SiliconInit in FSP 1.8.0. This patch has the respective
changes in coreboot for this.
BRANCH=none
BUG=none
TEST=Build and booted in kunimitsu
CQ-DEPEND=CL:*237423, CL:*237424
Change-Id: Ic008d22f96fb5f14965e5b5db15e05fb39dd52d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 573c1d8325cd504213528030ecf99559402b5118
Original-Change-Id: I71b893aa7788519ed2ef15f3247945ffcbbbcf4d
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310191
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
Rename soc_display_upd_value to fsp_display_upd_value since the routine
was moved from src/soc/intel/common into src/drivers/intel/fsp1_1.
BRANCH=none
BUG=None
TEST=Build and run on Kunimitsu
Change-Id: Ifadf9dcdf8c81f8de961e074226c349fb9634792
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 95238782702999a178989467694ac1f15c079615
Original-Change-Id: Ibd26ea41bd5c7a54ecd3c237f7fb7bad6dbf7d8a
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306351
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12157
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
|
|
In FSP 1.7.0 SataMode and SataEnable have been moved from
MemoryInit to SiliconInit. Also, GpioTablePtr has been removed.
USB phy settings added to SiliconInit, Enable the configs for USB
equalization settings in coreboot.
Addition of serialIO UPD to indicate FSP not to reinitialise
UART2 controller during MemoryInit.
BRANCH=none BUG=chrome-os-partner:45684, chrome-os-partner:42284, chrome-os-partner:41374
TEST=build for Kunimitsu, boot on FAB3, Also checked for Boot from USB, Boot from eMMC,
USB Audio, Onboard Audio, Touch, Wifi, S3 entry/resume
CQ-DEPEND=CL:*232947, CL:*232946, CL:*232948, CL:*232949
Change-Id: I2e8e6e32fc7074774ddcf1fb4c270bb56372b7df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 623c5a52f3afedaf2c0bfe7361cfd627d093cb73
Original-Change-Id: I8b3be2c49893c564fe2197aa32bde6323bf425e9
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/303661
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12144
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
The right files just need to be added to the verstage
build. Do that so a stand alone verstage builds and
links.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: I2d0c98760494e2f4657ee35b6f155690939d2d18
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11827
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
In order to introduce a verstage which performs vboot
verification the cache-as-ram environment needs to be
generalized and split into pieces that can be utilized
in romstage and/or verstage. Therefore, the romstage
pieces were removed from the cache-as-ram specific pieces
that are generic:
- Add fsp/car.h to house the declarations for functions in
the cache-as-ram environment
- Only have cache_as_ram_params which are isolated form the
cache-as-ram environment aside from FSP_INFO_HEADER.
- Hardware requirements for console initialization is done
in the cache-as-ram specific files.
- Provide after_raminit.S which can be included from a
romstage separated from cache-as-ram as well as one that
is tightly coupled to the cache-as-ram environment.
- Update the fallout from the API changes in
soc/intel/{braswell,common,skylake}.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302481
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11816
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
The report_platform_info() and set_max_freq() are not being
used similarly on skylake and braswell. With the addition
of other SoCs I suspect a similar pattern will emerge. Instead
of having weak functions to ensure things link with the hardcoded
policy push these calls into their respective SoC homes.
For parity, both skylake and braswell were updated to be consistent
with the same calls prior to this patch.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. Built braswell.
Original-Change-Id: I3371d09aff0629503254296955fef28d35754a38
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/303334
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I2de33632ed127cac52d7075cbad95cd6387a1b46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11815
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Eliminate unused parameters from the console initialization.
BRANCH=none
BUG=chrome-os-partner:44827
TEST=Build and run on kunimitsu
Original-Change-Id: Iacacea292d43615e9d2f8e5d3ec67e77f3f08906
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/301204
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Change-Id: I3a0ea948ce106b07cb6aa872375ce588317dc437
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11814
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
This removes the dependency on chromeos and vboot for the sw write protect state
function: vboot_get_sw_write_protect, renamed to get_sw_write_protect_state to
both reflect this change and become consistent with the definition of
get_write_protect_state that is already in use.
Change-Id: I47ce31530a03f6749e0f370e5d868466318b3bb6
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11496
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Set DISB inside romstage right after successful mrc init such that
any reset events afterwards can take fast boot path and in turn
achieve better boot performance
BRANCH=NONE
BUG=chrome-os-partner:43637
TEST=Built for kunimitsu and tested DISB is set correctly and fast
boot path is taken.
Change-Id: I230ff76287f90c5d3655a77bbaca666af37c4aae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7bdc6900012c99187bb90904df18c2b3f9e52c61
Original-Change-Id: Ie08b4a4f29a7c5cb47e508bc59a5e95f8e36fa00
Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295509
Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma@intel.com>
Original-Tested-by: dhaval v sharma <dhaval.v.sharma@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11550
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Remove dead code not called by any part of coreboot.
BRANCH=none
BUG=None
TEST=Build and run on skylake
Change-Id: I3d457a196d12d03340bceb444d1d6c95afef13df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 58ea135813afeef773f37023fda58f36d544beef
Original-Change-Id: Id8f4591f20d41f875348c6583618bbcaaf9d9a3a
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294953
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11544
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
I missed this in code review. This should be under the soc
directory.
BUG=chrome-os-partner:43522
BRANCH=None
TEST=Built glados.
Change-Id: Ia018c20f97f267b8f7592b2459d10eafe5ec7159
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9c081ed6de46605b7d0a72962ac2a041c470b12c
Original-Change-Id: Ic3938fe5d71bd24a395304cfabe40eff48bc4a40
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295239
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11542
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Early(romstage) SPI write protected status read(wpsr) functionality
was broken causing 2 sec timeout issue.Implementing HW Seq based rd
status operation in romstage.
BRANCH=NONE
BUG=chrome-os-partner:42115
TEST=Built for sklrvp and kunimitsu and tested using below command
flashrom -p host --wp-enable [this should enable WP on flash chip]
Read using romstage SPI.c. WPSR=0x80 (CB is reading Bit 7 as locked)
flashrom -p host --wp-disable [this should disable WP on flash chip]
Read using romstage SPI.c. WPSR=0x00 (CB is reading Bit 7 as unlocked)
Change-Id: I79f6767d88f766be1b47adaf7c6e2fa368750d5a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 4b798c44634581ebf7cdeea76c486e95e1f0a488
Original-Change-Id: I7e9b02e313b84765ddfef06724e9921550c4e677
Original-Signed-off-by: Subrata <subrata.banik@intel.com>
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294445
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11423
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The RMT flag that was attempting to disable saved training to
force a full memory train was happening too late. In testing
I was actually hitting a case where FSP was training every time
but it was not because it was properly being told to.
This moves the check of the RMT flag from devicetree to happen
ealier, before it is actually consumed by romstage_common().
BUG=chrome-os-partner:40635
BRANCH=none
TEST=do both power off+on and warm resets to ensure that FSP
is doing a full memory train every time with RMT enabled.
Change-Id: Icf36e7b1ae20e08f6bc24bf832498d69b37dee92
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: f3fa3846d51dec65f22f018acc8fb8c4d18688a7
Original-Change-Id: I2128b4a24bb8b2c8ddcb792c09b6fb0284d1fda4
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294177
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11417
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
RMT is useless if the memory does not do a full training pass,
and since FSP does not seem to handle that case itself have
coreboot not pass in a valid set of saved training data so FSP
will do a full memory train.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot twice on glados with p2 and RMT enabled
and see it do a full memory train on each boot.
Change-Id: Ia4f29a937e726a5a676f056ce8970086988da5b6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: f01e99204409899d4adbaebbe221b0348975cfa6
Original-Change-Id: I0bb193c5f3c9206a67315906745aad96a95b3f74
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294067
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11414
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The SOC handler for memory init params is only taking UPD
as an input which does not allow it to use romstage_params.
In addition the UPD input is called params which is confusing
so rename it to upd so romstage_params can be passed properly.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados p2
Change-Id: I414610fee2b5d03a8e2cebfa548ea8bf49932a48
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: db94d6f3e6cad721de2188a136df10ccf66aff6a
Original-Change-Id: I7ec15edd4a16df121c5967aadd8b2651267ec773
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294066
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11413
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Update the MemoryInit and SilicoInit params as per
FSP 1.3.0 release.
Note: add SvGv and Rmt to Upd.
BRANCH=None
BUG=None
TEST=Build and Boot FAB3 (Kunimitsu)
CQ-DEPEND=CL:*226035, CL:*226045
Original-Change-Id: I62000f6a485fee42ef733c3b548192f2bedfce49
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291573
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Change-Id: Iaafa658b4e710fe512526a521cf6c529efb19bf0
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: http://review.coreboot.org/11238
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Ignore the devicetree.cb setting and use the already
existing IED_REGION_SIZE Kconfig option.
BUG=chrome-os-partner:43636
BRANCH=None
TEST=Built, booted, suspended, resumed on glados.
Original-Change-Id: Ic1e760493635218faddeee4003303949305bc529
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290931
Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Trybot-Ready: David James <davidjames@chromium.org>
Change-Id: I416d4eb186a42d3258682e02a0a2e1db5bb668ac
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11199
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Instead of open coding the UART2 gpio configuration use
the support library.
BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I9637cb995d51b67eb320650d92f8518de0280dca
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289801
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I7f0e6599df983323f773f1ec6600537c20c15b11
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11176
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Many Kconfig options changed in coreboot.org since
skylake was first started. Fix Kconfig option name
changes, and also provide a common option, UART_DEBUG
that can be selected to select all the necessary
options.
Note: It's still a requirement to manually unset the
8250IO option because that's unconditionally set.
BUG=chrome-os-partner:43419
BUG=chrome-os-partner:43463
BRANCH=None
TEST=Built glados. Booted into kernel. Kernel reboots somewhere.
Original-Change-Id: I9e6549ea0f1d6b9ffe64a73856ec87b5bc7b7091
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289951
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I0e6b492d7279cc35d4fb3ac17fd727177adce39d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11172
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
In order to build without CONFIG_CONSOLE_SERIAL the Skylake
SOC Kconfig should not be enabling serial console by default.
Also fix other compile issues when serial console is disabled.
BUG=chrome-os-partner:40857
BRANCH=none
TEST=build glados without serial console enabled
Change-Id: I2b20d9d9cd66e79587525f7bb458782eeeac4a95
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f40fbea8d5dade560c08e4abf15a2a1cc28b9e55
Original-Change-Id: I6c5da8a5eee4090c89deb8feba676479cd834292
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/287438
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11043
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Log the global reset causes in the power state structure.
While working in there pack the struct and use width-specific
types as this struct crosses the romstate <-> ramstage boundary.
Lastly, remove hsio version as it wasn't being written or read.
After global reset induced:
PM1_STS: 0000
PM1_EN: 0000
PM1_CNT: 00000000
TCO_STS: 0000 0000
GPE0_STS: 00000000 00000000 00000000 00000000
GPE0_EN: 00000000 00000000 00000000 00000000
GEN_PMCON: d8010200 00003808
GBLRST_CAUSE: 00000000 00040004
Previous Sleep State: S0
BUG=None
BRANCH=None
TEST=Induced global reset on glados using ETR3 register and write
to cf9.
Change-Id: I97b93de336e74c0e02199241376e74340612f0a7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bbc8f1d62131c0381e9d401f3281ee7a17fc2a47
Original-Change-Id: I1a8e5d07c6c0e09c163effe27491d8f198823617
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286640
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11011
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
If a resume from S3 is occuring one needs to take into account
deep S3 in order to check the proper power failure bits.
When deep S3 is enabled the suspend well will be turned off.
Therefore don't look for that bit when determining a power
failure.
BUG=chrome-os-partner:42847
BRANCH=None
TEST=Suspend and resumed with deep s3 enabled and disabled.
Change-Id: I2b3372a40b3d8295ee881a283b31ca7704e6764a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a3ba22be37d8700f4e8a4a0f5c05fb9290cfc9b2
Original-Change-Id: I890f71a7cbea65f1db942fe2229a220cf0e721b0
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286271
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11007
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
GEN_PMCON_A and GEN_PMCON_B are 32-bits wide. Read out and
save the full 32 bits for completeness.
BUG=chrome-os-partner:42847
BRANCH=None
TEST=Built and booted. Noted output on terminal.
Change-Id: I24e589271d49c8cfc3fab327cfe4999c24fb95d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5a419b2538dc45b1bd0d19b7e6afd45fff9dd4a0
Original-Change-Id: Ie587e886ea34e36d106ff4670781467266a51ddb
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286270
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11006
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This patch adds 32bit uart8250_mem functionality in romstage
console for arch/x86.
BRANCH=None
BUG=chrome-os-partner:40857
TEST=Built for sklrvp; verified romstage logs on RVP3 board.
Change-Id: I6f13216b7f5ba8de48c781cd1791d0fa7ae0d921
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a17efdeec5524cbfc78015c358d1cf4f67485765
Original-Change-Id: I8b4e44c59bfd609a06807243df338763054b5865
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/271800
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/10999
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
FSP will initialize GPIOs during TempRamInit.
So configure LPSS UART2 GPIOs in native mode
after TempRamInit.
BRANCH=none
BUG=chrome-os-partner:41374
EST=Build and boot on RVP3. Check LPSS logs on UART2
Change-Id: I8016dd76a5bc06e90f9460273be7e83c5e8f8bb1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eb72e715ef3f566e900727ac8b9494bca1d5971c
Original-Change-Id: If1b1a1047ebd5e5f170d91972d11c51aa6fd84a9
Original-Signed-off-by: rsatapat <rishavnath.satapathy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/281604
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/10995
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
On Skylake, only UART2 is supported as debug port and the macros
INTEL_PCH_UART_CONSOLE_NUMBER, INTEL_PCH_UART_CONSOLE and the partial
code for UART0, 1 are cleaned up for Skylake and Sklrvp, Kunimitsu and
Glados boards.
BRANCH=none
BUG=chrome-os-partner:40857
TEST=Built for kunimitsu, checked the coreboot logs on LPSS UART2
Change-Id: I2fbcfb1d1ca6f59309a77c67d022cf4f5da7f7c0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e714c18d462bc7bdd7068309fb6be77da6973642
Original-Change-Id: I9343abd90ce685ea2d676047dccbefad7457b69f
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285793
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/10994
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
For some unkonwn reason the pcie root port settings weren't
being honored in the device tree. Fix that omission.
BUG=chrome-os-partner:41861
BRANCH=None
TEST=Built with CONFIG_DISPLAY_UPD_DATA and noted devicetree
settings were being honored.
Change-Id: Id880eca57544efb13f5cbbc06b2634c86b7c5d29
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2d00e68ce6cfcb3d63d69848f4a8ce232f6c1257
Original-Change-Id: Idd37d65374842294f4b0c91eb841c6d1d93e92ee
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285027
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10987
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Unhide the SPI controller PCI device if it is enabled in
devicetree.cb so flashrom can do its job.
BUG=chrome-os-partner:37711
BRANCH=none
TEST=run flashrom -r on glados
Change-Id: Ie567f970149700d29df0ae09db4962f36cf24219
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 172eac55ad6134fe5e347e37c055b383e3b03245
Original-Change-Id: Ia77b559cc607794aecc25d6d469224d855199568
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/284948
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10986
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add the files to support the Skylake SOC.
Matches chromium tree at 927026db
BRANCH=none
BUG=None
TEST=Build and run on a Skylake platform
Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use the Broadwell implementation as the comparison base for Skylake.
BRANCH=none
BUG=None
TEST=None
Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10340
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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