coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2017-07-18	soc/intel/skylake: Enable SMBus based on mainboard config	Naresh G Solanki
2017-07-13	soc/intel/skylake: reduce postcar stack usage for fsp 2.0	Aaron Durbin
2017-07-12	soc/intel/skylake: Remove “disable SaGv” in recovery mode flow	Subrata Banik
2017-04-25	soc/intel/skylake: use postcar stage for fsp 2.0	Aaron Durbin
2017-03-22	soc/intel/skylake: Add configs for enabling DCI and TraceHub	Aamir Bohra
2017-03-14	soc/intel/skylake: Extract DIMM Information from FSP MEM INFO HOB	Barnali Sarkar
2017-02-18	soc/intel/skylake: add PrmrrSize to chip config	Robbie Zhang
2016-12-13	intel MMA: Enable MMA with FSP2.0	Pratik Prajapati
2016-12-07	soc/intel/skylake: Remove redundant BootLoaderTolumSize assignment	Subrata Banik
2016-11-30	soc/intel/skylake: Pass proper CPU flex ratio override to FSP	Naresh G Solanki
2016-11-30	driver/intel/fsp2_0: Add version parameter to FSP platform callback	Andrey Petrov
2016-09-15	soc/intel/skylake: Add FSP 2.0 support in romstage	Barnali Sarkar
2016-08-31	skylake: Add initial FSP2.0 support	Rizwan Qureshi