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2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-05soc/intel/skylake: Enable VT-d and X2APICNico Huber
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX IOMMU and the general IOMMU respectively. These addresses have to be configured in MCHBAR registers (maybe, who knows, the blob is undocu- mented), advertised to FSP and reserved from the OS. The new devicetree option `ignore_vtd` allows to retain the old beha- viour (do whatever pre-set UPD values suggest). We also let FSP set up distinct BDFs for messages originating from the I/O-APIC and the HPET. Change-Id: I77f87c385736615c127143760bbd144f97986b37 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2018-02-08soc/intel/skylake: Clean up SMBIOS Table Type 17 creationSubrata Banik
* Add Memory Channel Status Enum for Channel detection. * Align > 80 characters per line. * Add hob_size == 0 check. Change-Id: I6ad99de53e280a3db431f706310e6cb22b8b3953 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/23636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-01-25soc/intel/skylake: Send correct ddr_type to SMBIOS TableBarnali Sarkar
The FSP 2.0 Memory_Info_HOB for KBL is not sending "MemoryType" value as what is required for SMBIOS Table according to SMBIOS Spec. Thus, converting the value retrieved from FSP HOB to the correct value. This change will not be required for upcoming SOCs since FSP have fixed this issue in its next platforms and thus it will take care and send the correct value in "MemoryType" field based on SMBIOS spec. Thus this conversion from coreboot will not be required in the next platfoms. "MemoryType" value can be directly passed to dimm_info_fill() function. BUG=none BRANCH=none TEST=Tested in Soraka, and getting the value as 0x1D for LPDDR3 memory. dmidecode (latest version 3.1) Command Type 17 will also show correct information. Currently, it was showing "Unknown". Change-Id: I75d6cca464680a88bf836e25bf5440a9cdbc738e Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/23384 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-22security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese
This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-05soc/intel/skylake: Add support in SKL for PMC common codeShaunak Saha
Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/20499 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-05vendor/intel/skykabylake: Update FSP header files to version 2.7.2Balaji Manigandan B
Update FSP header files to version 2.7.2. New UPDs added FspmUpd.h: *CleanMemory FspsUpd.h: *IslVrCmd *ThreeStrikeCounterDisable Structure member names used to specify memory configuration to MRC have been updated, SoC side romstage code is updated to handle this change. CQ-DEPEND=CL:*460573,CL:*460612,CL:*460592 BUG=b:65499724 BRANCH=None TEST= Build and boot soraka, basic sanity check and suspend resume checks. Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151 Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-17soc/intel/skylake: Configure FSP to skip ME MBP stepDuncan Laurie
We do not need or use the Management Engine MBP HOB so that step can be skipped when FSP initializes the ME. BUG=b:64479422 TEST=boot with FSP debug enabled binary and ensure that the output indicates this step is being skipped: Skipping MBP data due to SkipMbpHob set! Change-Id: I5ea22ec4b8b47fa17b1cf2bf562337bfaad5ec0d Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/20951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-07-20soc/intel/skylake: Fix broken memory info HOB scanningNico Huber
It looks like this code was written with completely different semantics in mind. Controllers, channels and DIMMs are all presented in their phy- sical order (i.e. gaps are not closed). So we have to look at the whole structure and not only the first n respective entries. Change-Id: I8a9039f73f1befdd09c1fc8e17cd3f6e08e0cd47 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20650 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-18soc/intel/skylake: Enable SMBus based on mainboard configNaresh G Solanki
Enable SMBus controller based on config in mainboard devicetree.cb BUG=None TEST= Build for Soraka, Verify that SMBus is enabled or disabled (run lspci in OS) based on board devicetree.cb config 'SmbusEnable'. Change-Id: I04c8bc30c03fd8dc7cc8ae239885e740b09e9bc1 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-07-13soc/intel/skylake: reduce postcar stack usage for fsp 2.0Aaron Durbin
The FSP 2.0 path uses postcar to decompress ramstage. Since postcar is entirely RAM based there's no need to have an excessively large stack for the lzma decompression buffer. Therefore, reduce the stack required to 1 KiB like apollolake. Change-Id: I45e5c283f8ae87e701c94d6a123463dddde3f221 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-07-12soc/intel/skylake: Remove “disable SaGv” in recovery mode flowSubrata Banik
This reverts commit 5535cead (intel/skylake: Disable SaGv in recovery mode). Commit 5535cead disables SaGv in recovery mode to save few seconds booting time as we were doing memory training on every recovery flow. Now we don't need to perform MRC training on every recovery boot due to RECOVERY_MRC_CACHE implementation in place. Hence we don't need to define different SaGv policy between Normal (developer) mode and recovery mode to save few seconds. Using different SaGv parameters between recovery and all other mode has some significent drawbacks over warm reboot cycle. We are seeing a MRC traning hang in eve/soraka/poppy devices with below use case. Step 1: Boot system in developer mode (first time RW_MRC training) Step 2: Set recovery_request=1 (using crossystem) and issue “reboot” from OS Step 3: System will perform recovery mode MRC training and boot to OS (first time RECOVERY_MRC training) Step 4: Issue “reboot” from OS console. Step 5: System wil boot in developer mode (using RW_MRC cache) Step 6: Set recovery_request=1 (using crossystem) and issue “reboot” from OS Step 7: System will pick RECOVERY_MRC_CACHE and will hang during MRC training. This patch fixes issue mentioned above and ensures system boot to OS without any hang if we change mode (dev<->recovery) over warm reset. BUG=b:63515071 BRANCH=none TEST=manual stress testing of dev<->recovery mode over warm boot. No MRC hang with this fix on eve/soraka/poppy devices. Change-Id: I8d094a8b6d78ea3bf8f929870a4a179495c29c78 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-25soc/intel/skylake: use postcar stage for fsp 2.0Aaron Durbin
Utilize the postcar stage for tearing down CAR and initializing the MTRRs once ram is up. This flow is consistent with apollolake and allows CAR_GLOBAL variables to be directly accessed and no need for migrating CAR_GLOBAL variables as romstage doesn't run with and without CAR being available. Change-Id: I76de447710ae1d405886eb9420dc4064aa26eccc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19335 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-22soc/intel/skylake: Add configs for enabling DCI and TraceHubAamir Bohra
Add configs for enabling Intel TraceHub and DCI for aid in debugging. Change-Id: Ic40f9499c0125070049856e242e89024ca5a1c4e Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18791 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14soc/intel/skylake: Extract DIMM Information from FSP MEM INFO HOBBarnali Sarkar
Extract SMBIOS memory information from FSP SMBIOS_MEM_INFO_HOB and save it in CBMEM. BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in SMBIOS Table from Kernel command "dmidecode". Change-Id: I593d4ccb0d4866e99913a73c49b2f000b51827d1 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18275 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-18soc/intel/skylake: add PrmrrSize to chip configRobbie Zhang
Prmrr configuration is supported by Kabylake FSP-M with UPD provided. It is required as one of the SGX initialization steps in BIOS. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Tested on Eve, verified uncore PRMRR MSRs get programmed to set size and boot. Change-Id: I2b3dc7c92487505165ee429bd1a37bd60ceac8f3 Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-on: https://review.coreboot.org/18361 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-13intel MMA: Enable MMA with FSP2.0Pratik Prajapati
- Separate mma code for fsp1.1 and fsp2.0 and restructuring the code - common code is placed in mma.c and mma.h - mma_fsp<ver>.h and fsp<ver>/mma_core.c contains fsp version specific code. - whole MMA feature is guarded by CONFIG_MMA flag. Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/17496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07soc/intel/skylake: Remove redundant BootLoaderTolumSize assignmentSubrata Banik
BootLoaderTolumSize FSP-M UPD is already initialized with cbmem_overhead_size() inside driver/fsp2_0/memory_init.c, hence remove the duplicate assignment. Change-Id: I0b1d9769cd2a863bf0547ce5f44928cacc5a63b6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17721 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30soc/intel/skylake: Pass proper CPU flex ratio override to FSPNaresh G Solanki
In bootblock, cpu flex ratio is set to non-turbo max. In FSP UPD, if CpuRatioOverride is zero, then it tries to program cpu ratio to zero. Since it is different than the non-zero value programmed in bootblock, FSP gives reset. To avoid the reset, set FSP UPD for CPU flex ratio override to that value as set in bootblock. Change-Id: I8cae5530ec97cedfbd71771f291db6f55a9fd5c2 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17555 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-30driver/intel/fsp2_0: Add version parameter to FSP platform callbackAndrey Petrov
Change-Id: Ibad1ad6bb9eedf2805981623e835db071d54c528 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17497 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15soc/intel/skylake: Add FSP 2.0 support in romstageBarnali Sarkar
Populate SoC related Memory initialization params. Post memory init, set DISB, setup stack and MTRRs using the postcar funtions provided in postcar_loader.c. TEST=Build and boot kunimitsu, dram initialization done. ramstage is loaded. Change-Id: I8d943e29b6e118986189166d92c7891ab6642193 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16315 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31skylake: Add initial FSP2.0 supportRizwan Qureshi
Add Initial pieces of code to support fsp2.0 in skylake keeping the fsp1.1 flow intact. The soc/romstage.h and soc/ramstage.h have a reference to fsp driver includes, so split these header files for each version of FSP driver. Add the below files, car_stage.S: Add romstage entry point (car_stage_entry). This calls into romstage_fsp20.c and aslo handles the car teardown. romstage_fsp20.c: Call fsp_memory_init() and also has the callback for filling memory init parameters. Also add monotonic_timer.c to verstage. With this patchset and relevant change in kunimitsu mainboard, we are able to boot to romstage. TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1 Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0 Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16267 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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