Age | Commit message (Expand) | Author |
2018-10-10 | soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled | Furquan Shaikh |
2018-06-14 | src: Get rid of device_t | Elyes HAOUAS |
2018-04-20 | pci: Move inline PCI functions to pci_ops.h | Patrick Rudolph |
2017-12-21 | soc/intel/skylake: Move Enable power button SMI code from smi.c to pmc.c | Subrata Banik |
2017-12-21 | soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDS | Subrata Banik |
2017-12-02 | soc/intel/common/block: Add Intel common PMC controller support for KBL, APL | Subrata Banik |
2017-10-05 | soc/intel/skylake: Add support in SKL for PMC common code | Shaunak Saha |
2017-09-20 | soc/intel/skylake: refactor rtc failure checking | Aaron Durbin |
2017-09-20 | vboot: remove init_vbnv_cmos() | Aaron Durbin |
2017-04-13 | soc/intel/skylake: Split AC/DC settings for Deep Sx config | Duncan Laurie |
2017-04-10 | soc/intel/skylake: Use common PCR module | Subrata Banik |
2017-02-16 | soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO... | Sooi, Li Cheng |
2016-10-27 | skylake: Prepare GPE for use in bootblock | Duncan Laurie |
2016-07-28 | soc/intel/skylake: Use init_vbnv_cmos from vboot vbnv | Furquan Shaikh |
2016-07-28 | vboot: Separate vboot from chromeos | Furquan Shaikh |
2016-07-15 | soc/intel/skylake: use common Intel ACPI hardware definitions | Aaron Durbin |
2016-02-09 | chromeos: Remove CONFIG_VBNV_SIZE variable | Duncan Laurie |
2015-11-13 | intel/skylake: ensure the RTC time is set | Aaron Durbin |
2015-09-08 | Skylake:Set DISB inside romstage after mrc init | Dhaval Sharma |
2015-08-14 | skylake: remove ec_smi_gpio and alt_gp_smi_en | Aaron Durbin |
2015-08-14 | skylake: provide GPE0 routing devicetree configuration | Aaron Durbin |
2015-08-14 | skylake: clear write-1-to-clear fields in power regs | Aaron Durbin |
2015-08-14 | skylake: set DISB in GEN_PMCON_A register properly | Aaron Durbin |
2015-08-14 | skylake: fill out gen_pmcon_* bitfields | Aaron Durbin |
2015-08-13 | skylake: Add Deep Sx configuration for wake pins | Duncan Laurie |
2015-07-16 | soc/intel: Add Skylake SOC support | Lee Leahy |