coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2017-08-28	soc/intel/skylake: Fix FSP1.1 booting issue with HW based dram top calculation	Subrata Banik
2017-08-23	soc/intel/skylake: Usable dram top calculation based on HW registers	Subrata Banik
2017-07-17	soc/intel/skylake: remove top_of_32bit_ram() declaration	Aaron Durbin
2016-11-30	soc/intel/skylake: Fix top_of_ram calculation	Naresh G Solanki
2016-08-31	skylake: Add initial FSP2.0 support	Rizwan Qureshi
2016-08-08	soc/intel/skylake: Cleanup patch for Skylake SoC	Barnali Sarkar
2016-07-31	Remove extra newlines from the end of all coreboot files.	Martin Roth
2016-01-31	drivers/intel/fsp1_1: Fix spelling error in API and copyright	Lee Leahy
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-08-19	Skylake: update cbmem_top	Rizwan Qureshi
2015-08-14	intel/common: fix stage_cache_external_region()	Aaron Durbin
2015-08-14	skylake: clean up SMM region calculations	Aaron Durbin
2015-07-21	intel fsp: remove CHIPSET_RESERVED_MEM_BYTES	Aaron Durbin
2015-07-16	soc/intel: Add Skylake SOC support	Lee Leahy
2015-07-16	soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC	Lee Leahy