| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-05-02 | soc/intel/skylake: Clean up code by using common FAST_SPI module | Barnali Sarkar |
| 2017-04-25 | soc/intel/skylake: use postcar stage for fsp 2.0 | Aaron Durbin |
| 2017-03-17 | soc/intel/skylake: Add int to unsigned | Lee Leahy |
| 2017-02-22 | soc/intel/skylake: Fix broken suspend-resume | Furquan Shaikh |
| 2017-02-14 | soc/intel/skylake: Perform CPU MP Init before FSP-S Init | Subrata Banik |
| 2016-12-13 | intel MMA: Enable MMA with FSP2.0 | Pratik Prajapati |
| 2016-09-19 | soc/intel/skylake: Add FSP 2.0 support in ramstage | Naresh G Solanki |
| 2016-09-15 | soc/intel/skylake: Add FSP 2.0 support in romstage | Barnali Sarkar |
| 2016-08-31 | skylake: Add initial FSP2.0 support | Rizwan Qureshi |
 |
index : coreboot.git | |
| my copy of coreboot | gitea |
| aboutsummaryrefslogtreecommitdiff |