| Age | Commit message (Collapse) | Author |
|---|
|
This patch cleans soc/intel/{apollolake/cannonlake/skylake} by moving
common soc code into common/block/i2c.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL/CNL/APL platform.
Change-Id: I88f2f836eee4f80b79486dd8644d1bb3826c5af1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Right now dw_i2c_get_soc_cfg() is expecting the SoC to implement
that callback for obtaining the bus config. However, we're currently
forcing another parameter of struct device so one can do the lookup.
This works for Intel-based systems since the struct device was needed
to program the BAR, etc. However, from an API standpoint, it just
complicates matters by needing to obtain the struct device. The SoC
already has knowlege of its own devices so it can get the config
itself by bus number. Therefore, remove that contraint from the API.
BUG=b:70232394
Change-Id: Id8558f5deedda0963a46a532a7bf984e168fb270
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23420
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Rename the following functions to ensure it's clear that the designware
i2c host controller driver is the one that these functions are
associated with:
i2c_get_soc_cfg() -> dw_i2c_get_soc_cfg()
i2c_get_soc_early_base() -> dw_i2c_get_soc_early_base()
i2c_soc_devfn_to_bus() -> dw_i2c_soc_devfn_to_bus()
i2c_soc_bus_to_devfn() -> dw_i2c_soc_bus_to_devfn()
BUG=b:72121803
Change-Id: Idb7633b45a0bb7cb7433ef5f6b154e28474a7b6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23371
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
BUG=b:70232394
BRANCH=none
TEST=emerge-reef coreboot
emerge-glados
Change-Id: Idb453a4d2411163e6b4a8422310bf272eac5d379
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Reviewed-on: https://review.coreboot.org/22822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
From comment from https://review.coreboot.org/#/c/22238/, the coding
style need to be update.
TEST=N/A
Change-Id: Id022648951c0f11216aa32f422b5095476f82f8c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
In the intel/common/block
* Move I2C common code from intel/common to intel/common/block.
* Split the code into common, early init and post mem init stages and put it
in lpss_i2c.c, i2c_early.c and i2c.c respectively.
* Declare functions for getting platform specific i2c bus config and
mapping bus to devfn and vice versa, that have to be implemented by SoC.
In skylake/apollolake
* Stop using code from soc/intel/common/lpss_i2c.c.
* Remove early i2c initialization code from bootblock.
* Refactor i2c.c file to implement SoC specific methods
required by the I2C IP block.
Change-Id: I4d91a04c22e181e3a995112cce6d5f0324130b81
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/19468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Fix the following warning detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
TEST=Build for glados
Change-Id: Idc2ad265e8ed8cd7fd6d228cfbe4cbbcb9d3ebfc
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18866
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
The default register count calculations are leading to higher
frequencies than expected. Provide an alternative method for
calculating the register counts by utilizing the rise and
fall times of the bus. If the rise time is supplied the
rise/fall time values are used, but the register overrides
take precedence over the rise/fall time calculation. This
allows platforms to choose whichever method works the best.
BUG=chrome-os-partner:58889
Change-Id: I7747613ce51d8151848acd916c09ae97bfc4b86a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17350
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
|
|
The apollolake and skylake had duplicate stanzas of code for
initializing the i2c buses. Additionally, they also had very
similar structures for providing settings for the i2c speed
control. Introduce a new struct lpss_i2c_bus_config and
utilize it in both apollolake and skylake thereby removing
the need for SoC-specific structres. The new structure is
used for initializing a bus fully as the lpss i2c API is
simplified in that lpss_i2c_init() is only required to be
called. The struct lpss_i2c_bus_config structure is passed
in for both initializing and filling in the SSDT information.
The formerly exposed functions are made static to reduce the
external API exposure.
BUG=chrome-os-partner:58889
Change-Id: Ib4fa8a7a4de052da75c778a7658741a5a8e0e6b9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17348
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Testing for "devfn < 0" on an unsigned doesn't work, and i2c_bus_to_devfn
returns an int (with -1 for "error"), so use int for devfn.
Adapt Change-Id I7d1cdb6af4140f7dc322141c0c018d8418627434 to fix more
instances.
Change-Id: I001a9b484a68e018798a65c0fae11f8df7d9f564
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1357450, #1357449
Reviewed-on: https://review.coreboot.org/17054
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Have the Skylake SOC generate ACPI timing values for the enabled I2C
controllers instead of passing it in the DSDT with static timings.
The timing values are generated from the controller clock speed and
are more accurate than the hardcoded values that were in the ASL which
were originally copied from Broadwell where the controller is running
at a different clock speed...
Additionally it is now possible for a board to override the values
using devicetree.cb. If zero is passed in for SCL HCNT or LCNT then
the kernel will generate its own timing using the same forumla, but if
the SDA hold time value is zero the kernel will NOT generate a correct
value and the SDA hold time may be incorrect.
This was tested on the Chell platform to ensure all the I2C devices on
the board are still operational with these new timing values.
Change-Id: I4feb3df9e083592792f8fadd7105e081a984a906
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15291
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Support the common Intel LPSS I2C driver for the 6 I2C bus controllers
that are present on the Skylake-LP PCH with a 120 mHz clock. The
required lpss_i2c_base_address() method is implemented separately for
verstage/romstage and ramstage environments.
This provides methods to convert to and from "struct device" and the
I2C controller bus number for that device. These are used to provide
support for the "I2C Bus Operations" that are present in the coreboot
devicetree.
To support the I2C controller before ramstage an early init function
is provided to do minimal initializaiton of the PCI device and assign
a temporary base address for use before memory. The final base
address is assigned during device enumeration and used during ramstage.
Because it is usually not necessary to enable I2C controllers before
ramstage a config register for the devicetree is provided to perform
early initialization of this controller. In addition the bus speed
can be set in the devicetree and that speed will be applied when the
device is initialized. If not provided the default speed is set to
I2C_SPEED_FAST.
This was tested with the google/chell mainboard by reading and writing
from the trackpad and codec devices during both verstage and ramstage.
Change-Id: Ia0270adfaf2843a3be4e00c732c85401a3401ef5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/15105
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
Add the I2C devices to skylake with the scan_bus handler for SMBUS
devices so that I2C-based devices can be declared in devicetree.cb
and get initialized properly during ramstage.
This does not yet provide the I2C driver, but it allows for devices
that are declared in devicetree.cb to provide ACPI tables to the OS.
Change-Id: I9dfe4a06a8b0bc549a2b0e2d7c033c895188ba30
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14992
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
