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path: root/src/soc/intel/skylake/elog.c
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2017-08-08soc/intel/skylake: Log wakes caused by PME on internal bus and PCIE RPNaresh G Solanki
Internal PME is detected when bit PME_B0_STS is set. Following devices causes internal PME. - Integrated LAN - HD Audio/Audio DSP - SATA - XHCI ('USB3') - ME Maskable Host Wake In SPT, PCIEXPWAK_STS bit isn't getting set due to known bug. So scan all PCIe RP for PME status bit & update event log accordingly. BUG=b:36992859 TEST=Build for Soraka, Verify resume due to PME on root port is logged in elog. Change-Id: I879a7c332e62ab598942b29d31bad84619b35ea7 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/20532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-18soc/intel/skylake: Remove Heci2 and Heci3 from wake resource listSubrata Banik
HECI2 and HECI3 devices are “function disable” during FSP Silicon Init phase. Device will not be visible over PCI bus hence removing these devices from wake source list. Change-Id: I0de665e039d74e49e5a22db9714bc9fee734e681 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-14soc/intel/skylake: Add USB port number information to wake sourceFurquan Shaikh
USB port status register can be used to decide if a particular port was responsible for generating PME# resulting in device wake: 1. CSC bit is set and port is capable of waking on connect/disconnect 2. PLC bit is set and port is in resume state BUG=b:37088992 TEST=Verified with wake on USB2.0 port 3, mosys shows: 19 | 2017-06-08 15:43:30 | Wake Source | PME - XHCI (USB 2.0 port) | 3 Change-Id: Ie4fa87393d8f096c4b3dca5f7a97f194cb065468 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/20122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-27soc/intel/skylake: Add detailed information about PME wake sourcesFurquan Shaikh
Add more fine-grained details about what device caused the PME wake event. This requires checking the PME status bit (bit 15) in PCI PM control and status register for the PCI device. BUG=b:37088992 TEST=Verifed that XHCI wake source was identified correctly: 135 | 2017-05-25 15:28:17 | ACPI Enter | S3 136 | 2017-05-25 15:28:26 | ACPI Wake | S3 137 | 2017-05-25 15:28:26 | Wake Source | PME - XHCI | 0 Change-Id: I6fc6284cd04db311f1f86b8a86d0bb708392e5d5 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19925 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-22soc/intel/skylake: Add entry for deep Sx wakeFurquan Shaikh
If deep Sx is enabled and prev sleep state was not S0, then if SUS power was lost, it means that the platform had entered deep Sx. Add an elog entry for deep Sx variant in this case. BUG=b:38436041 TEST=Verified that elog entries are updated correctly: Deep S5: 59 | 2017-05-19 10:39:08 | Kernel Event | Clean Shutdown 60 | 2017-05-19 10:39:09 | ACPI Enter | S5 61 | 2017-05-19 10:39:17 | System boot | 22 62 | 2017-05-19 10:39:17 | EC Event | Power Button 63 | 2017-05-19 10:39:17 | ACPI Deep Sx Wake | S5 64 | 2017-05-19 10:39:17 | Wake Source | Power Button | 0 65 | 2017-05-19 10:39:17 | Chrome OS Developer Mode Deep S3: 66 | 2017-05-19 10:40:11 | ACPI Enter | S3 67 | 2017-05-19 10:40:16 | EC Event | Power Button 68 | 2017-05-19 10:40:16 | ACPI Deep Sx Wake | S3 69 | 2017-05-19 10:40:16 | Wake Source | Power Button | 0 Normal S3: 77 | 2017-05-19 10:43:22 | ACPI Enter | S3 78 | 2017-05-19 10:43:39 | EC Event | Power Button 79 | 2017-05-19 10:43:39 | ACPI Wake | S3 80 | 2017-05-19 10:43:39 | Wake Source | Power Button | 0 Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-08intel/skylake: Filter suspend well power failure event for Deep SxDuncan Laurie
If Deep Sx is enabled the event log will get entries added on every power sequence transition indicating that the suspend well has failed. When a board is using Deep Sx by design this is intended behavior and just fills the logs with extraneous events. To make this work the device init state has to be executed first so it actually enables the Deep Sx policies in the SOC since this code does not have any hooks back into the devicetree to read the intended setting from there. BUG=b:36042662 BRANCH=none TEST=Perform suspend/resume on Eve device with Deep S3 enabled, and then check the event log to be sure that it does not contain the "SUS Power Fail" event. Change-Id: I3c8242baa63685232025e1dfef5595ec0ec6d14a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18664 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-08soc/intel/skylake: Cleanup patch for Skylake SoCBarnali Sarkar
Here is the list of items of code cleanup 1. Define TCO registers in smbus.h and not in pmc.h (as per EDS). 2. Include smbus.h wherever these TCO register defines were used. 3. Remove duplication of define in gpio_defs.h. 4. Remove unnecessary console.h include from memmap.h as no prints done. 5. Remove unnecessary comment from pch.c. BUG=none BRANCH=none TEST=Built and boot kunimitsu. Change-Id: Ibe6d2537ddde3c1c7f8ea5ada1bfaa9be79c0e3b Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16027 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2016-07-15soc/intel/skylake: use common Intel ACPI hardware definitionsAaron Durbin
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I5f2aa424a167092b570fda020cddce5ef906860a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15671 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
2016-03-12intel/skylake: Do not log wake source on resetDuncan Laurie
Skip logging a wake source when just resetting without coming from S3 or S5 state. This will prevent the occasional spurious event like PCI PME from showing up in the event log. BUG=chrome-os-partner:40635 BRANCH=glados TEST=run warm reboot teset on chell and ensure no wake source is logged Change-Id: If739034dc9022b37c90b9cc849a00c604383e70f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e7b5cc91adc3ed10df7cebd758cf8144216b9890 Original-Change-Id: I16f4f98df8c70fd25986a8b3644334c7209fd083 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329846 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/331173 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13991 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-18intel/skylake: Add elog event for THERMTRIPDuncan Laurie
The THERMTRIP status bit is in GBLRST_CAUSE instead of GEN_PMCON like the EDSv1 indicates. Read this status bit and add an elog event if THERMTRIP has fired. BUG=chrome-os-partner:48438 BRANCH=none TEST=tested on chell EVT after thermtrip fired Change-Id: Icd52b753c7f3ab0d48095279f1255dd2dd08fd59 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b090c7897a8f99a685f523990235d83fafa063b2 Original-Change-Id: I5a287d7fdae2ba8ae8585cb9a4d4dd873393e1e6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/317242 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12980 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-07-29skylake: align power management names with hardwareAaron Durbin
Some of the field and register names in the power management code were not reflecting current chipset documentation. While in there fix 0-sized array in the power_state structure. Lastly, log the entire STD GPE register for visibility in elog. It reports as an extension of other GPIO wake events. BUG=None BRANCH=None TEST=Built and booted. Change-Id: I57a621a418f90103ff92ddbf747e71a11d517c9a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: ed15cc7d0aeee8070e134ed03e28fced9361c00e Original-Change-Id: I19f9463c87e9472608e69d143932e66ea2b3c3e1 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/288296 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11070 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16soc/intel: Add Skylake SOC supportLee Leahy
Add the files to support the Skylake SOC. Matches chromium tree at 927026db BRANCH=none BUG=None TEST=Build and run on a Skylake platform Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10341 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-16soc/intel/skylake: Use Broadwell as comparision base for Skylake SOCLee Leahy
Use the Broadwell implementation as the comparison base for Skylake. BRANCH=none BUG=None TEST=None Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10340 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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