coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2017-06-09	soc/intel/skylake: Enable ACPI PM timer emulation on all CPUs	Subrata Banik
2017-06-09	soc/intel/skylake: Use CPU common library code	Barnali Sarkar
2017-06-09	soc/intel/skylake: Move update microcode from cbfs to mp_ops callbacks	Barnali Sarkar
2017-06-09	soc/intel/skylake: Cache the MMIO BIOS region	Aaron Durbin
2017-06-07	src: change coreboot to lowercase	Martin Roth
2017-06-05	soc/intel/skylake: Add config for cpu base clock frequency	Aamir Bohra
2017-05-16	soc/intel/skylake: Add option to enable/disable EIST	Subrata Banik
2017-05-16	soc/intel/skylake: Configure C-state interrupt response time	Subrata Banik
2017-05-08	soc/intel/skylake: Enable MTRR check	Furquan Shaikh
2017-04-24	soc/intel/skylake: Add ID's for Kabylake-R	Naresh G Solanki
2017-03-23	soc/intel/skylake: Add SGX initialization	Robbie Zhang
2017-03-17	soc/intel/skylake: Fix remaining issues detected by checkpatch	Lee Leahy
2017-03-17	soc/intel/skylake: Wrap lines at 80 columns	Lee Leahy
2017-03-17	soc/intel/skylake: Add int to unsigned	Lee Leahy
2017-03-06	soc/intel/skylake: Clean up CPU code	Subrata Banik
2017-02-22	soc/intel/skylake: Fix broken suspend-resume	Furquan Shaikh
2017-02-17	intel/skylake: add function is_secondary_thread()	Robbie Zhang
2017-02-16	soc/intel/skylake: Add CPU, PCH, MCH, IGD, XHCI and UART IDs for SKL/KBL HALO...	Sooi, Li Cheng
2017-02-14	soc/intel/skylake: Perform CPU MP Init before FSP-S Init	Subrata Banik
2016-12-26	soc/intel/skylake: set TCC activation by BSP only	Sumeet Pawnikar
2016-11-14	skylake: Update the thermal time window for throttling action	Sumeet Pawnikar
2016-08-06	soc/intel/skylake: Add Kabylake device Ids	Rizwan Qureshi
2016-07-31	src/soc: Capitalize CPU, ACPI, RAM and ROM	Elyes HAOUAS
2016-05-06	soc/intel/skylake: convert to using common MP and SMM init	Aaron Durbin
2016-05-02	cpu/x86/mp_init: remove unused callback arguments	Aaron Durbin
2016-03-29	intel/skylake: Enable PROCHOT	Pratik Prajapati
2016-03-08	x86 chipsets: utilize x86_setup_mtrrs_with_detect()	Aaron Durbin
2016-03-01	Skylake: Support Intel Speed Shift Technology based on config	Subrata Banik
2016-01-22	intel/skylake: Thermal Design Power PL1 and PL2 Config Changes	pchandri
2015-11-05	skylake: Set Pkg Power clamping bit in Power Limit MSR	Rizwan Qureshi
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-10-15	cpu/mtrr.h: Fix macro names for MTRR registers	Alexandru Gagniuc
2015-10-11	Skylake: remove the out-dated VR config and un-needed 24mhz calibration	robbie zhang
2015-08-27	skylake: only generate ACPI cpu entries once	Aaron Durbin
2015-07-29	skylake: Update microcode reload in ramstage.	Rizwan Qureshi
2015-07-16	soc/intel: Add Skylake SOC support	Lee Leahy
2015-07-16	soc/intel/skylake: Use Broadwell as comparision base for Skylake SOC	Lee Leahy